阅读说明：本技术 控制芯片、控制电路、电源电路及控制方法 (Control chip, control circuit, power supply circuit and control method ) 是由 陈晓亮 曹锋 于 2019-09-19 设计创作，主要内容包括：本发明揭示了一种控制芯片、控制电路、电源电路及控制方法,所述控制芯片设有复用引脚和公共接地端电压引脚,所述复用引脚作为电压反馈引脚和电流检测引脚的复用引脚,所述公共接地端电压引脚连接控制芯片的公共端；所述控制芯片能在控制芯片处于第一状态下通过所述复用引脚获取电流采样信号；所述控制芯片能在控制芯片处于第二状态下通过所述复用引脚获取电压反馈信号。本发明提出的控制芯片、控制电路、电源电路及控制方法,通过将FB和CS引脚复用的形式,可简化控制芯片电路中的引脚排布,有效降低控制芯片电路的封装成本,系统成本也随之降低。(The invention discloses a control chip, a control circuit, a power supply circuit and a control method, wherein the control chip is provided with a multiplexing pin and a common ground terminal voltage pin, the multiplexing pin is used as a multiplexing pin of a voltage feedback pin and a current detection pin, and the common ground terminal voltage pin is connected with a common terminal of the control chip; the control chip can obtain a current sampling signal through the multiplexing pin when the control chip is in a first state; the control chip can obtain a voltage feedback signal through the multiplexing pin when the control chip is in a second state. According to the control chip, the control circuit, the power supply circuit and the control method, the FB pin and the CS pin are multiplexed, so that pin arrangement in the control chip circuit can be simplified, the packaging cost of the control chip circuit is effectively reduced, and the system cost is reduced.)

1. A control chip is characterized in that the control chip is provided with a multiplexing pin and a common ground terminal voltage pin, the multiplexing pin is used as a multiplexing pin of a voltage feedback pin and a current detection pin, and the common ground terminal voltage pin is connected with a common terminal of the control chip;

the control chip can obtain a current sampling signal through the multiplexing pin when the control chip is in a first state; the control chip can obtain a voltage feedback signal through the multiplexing pin when the control chip is in a second state.

2. The control chip of claim 1, wherein:

the voltage feedback signal is used for representing output voltage, and the current sampling signal is used for representing conduction current of a transistor in a conduction state;

in the first state, a first voltage at the common ground voltage pin varies with a source voltage of the transistor;

in the second state, the first voltage at the common ground voltage pin remains stable.

3. The control chip of claim 1, wherein:

the control chip is internally provided with a pulse width modulation module which outputs a pulse width modulation signal to control the on-off of the transistor;

when the pulse width modulation signal is at a high level, the transistor is conducted; the control chip can acquire the current flowing through the transistor through the multiplexing pin;

when the pulse width modulation signal is at a low level, no current flows through the transistor; the control chip can obtain a voltage feedback signal through the multiplexing pin.

4. The control chip of claim 3, wherein:

the transistor is internally sealed in the control chip, namely the transistor is used as a part of the control chip; or, the transistor is arranged outside the control chip.

5. The control chip of claim 4, wherein:

the multiplexing pin is coupled with a sampling resistor Rcs; the sampling resistor Rcs is internally sealed or integrated on the control chip, or the sampling resistor Rcs is arranged outside the control chip.

6. A control circuit, characterized by: the control circuit comprises the control chip of any one of claims 1 to 5.

7. The control circuit of claim 6, wherein:

the control circuit further comprises a sampling resistor, and the control chip is coupled with the sampling resistor; the control circuit further comprises a transistor; a common ground terminal voltage pin of the control chip is coupled with a first end of the sampling resistor;

the transistor and the control chip are independently arranged, the control chip is coupled with the transistor, a gate control input signal pin of the control chip is coupled with the transistor, and a source electrode of the transistor is coupled with the first end of the sampling resistor; or, the transistor is used as a part of a control chip, the control chip is provided with a drain terminal pin, the drain terminal pin of the control chip is coupled with the drain electrode of the transistor, the gate control input signal end of the control chip is connected with the transistor, and the source electrode of the transistor is coupled with the voltage pin of the common ground terminal;

the control chip outputs a pulse width modulation signal through a pulse width modulation module so as to control the on-off of the transistor.

8. The control circuit of claim 7, wherein:

when the pulse width modulation signal is at a high level, the transistor is conducted; the control chip can acquire the current flowing through the transistor through the multiplexing pin;

when the pulse width modulation signal is at a low level, no current flows through the transistor; the control chip can obtain the voltage feedback signal through the multiplexing pin.

9. The control circuit according to claim 6 or 7, wherein:

the control circuit further comprises a first voltage-dividing resistor R1 and a second voltage-dividing resistor R2, wherein the second end of the first voltage-dividing resistor R1 is connected with the first end of the second voltage-dividing resistor R2, and the second end of the second voltage-dividing resistor R2 is grounded; the multiplexing pin connects the connection node between the first divider resistor R1 and the second divider resistor R2.

10. A power supply circuit, characterized by: the power supply circuit comprising the control circuit of any of claims 6 to 9.

11. The control circuit of claim 10, wherein:

the power supply circuit further comprises a first capacitor C1 and a second capacitor C2; the control chip is provided with a power supply voltage pin and a compensation pin; the power supply voltage pin is coupled to the first capacitor C1, and the compensation pin is coupled to the second capacitor C2.

12. The control circuit of claim 10, wherein:

the power supply circuit further comprises an inductor L, a diode D, a third capacitor C3 and a third resistor R3;

the first end of the inductor L is coupled with the input voltage, and the second end of the inductor L is respectively coupled with the anode of the diode D and the drain of the transistor;

the cathode of the diode D is respectively connected with the output voltage, the first end of the third capacitor C3 and the first end of the third resistor R3; the second terminal of the third capacitor C3 is grounded, and the second terminal of the third resistor R3 is grounded.

13. A control method characterized by: the control method comprises the following steps: acquiring a current sampling signal through a multiplexing pin when a control chip is in a first state; acquiring a voltage feedback signal through the multiplexing pin when the control chip is in a second state; the multiplexing pin is used as a multiplexing pin of a voltage feedback pin FB and a current detection pin CS;

the pulse width modulation module controls the on-off of the transistor by outputting a pulse width modulation signal;

when the pulse width modulation signal is at a high level, the transistor is conducted, and the control chip is in a first state; obtaining the current flowing through the transistor through the multiplexing pin;

when the pulse width modulation signal is at a low level, no current flows through the transistor, and the control chip is in a second state; and acquiring a voltage feedback signal through the multiplexing pin.

14. The control method according to claim 13, characterized in that:

when the pulse width modulation signal is at a low level, no current flows through the transistor and the sampling resistor Rcs; at this time, the voltage VSS of the common ground terminal is 0, and the voltage FB _ sense corresponding to the voltage feedback obtained by the multiplexing pin is FB _ sense;

when the pulse width modulation signal is at a high level, the transistor is conducted; the voltage of the common ground terminal VSS is Imos Rcs, and the voltage at the multiplexing pin is FB _ sense-Imos Rcs, so that the current flowing through the transistor can be obtained; wherein Imos is the magnitude of the current flowing through the transistor, and Rcs is the resistance value of the sampling resistor Rcs.

Technical Field

The invention belongs to the technical field of power supply circuits, and relates to a control chip, a control circuit, a power supply circuit and a control method.

Background

Disclosure of Invention

The invention provides a control chip, a control circuit, a power supply circuit and a control method, which can simplify the pin arrangement in the control chip circuit, effectively reduce the packaging cost of the control chip circuit and reduce the system cost.

In order to solve the technical problem, according to one aspect of the present invention, the following technical solutions are adopted:

a control chip is provided with a multiplexing pin and a common ground terminal voltage pin, wherein the multiplexing pin is used as a multiplexing pin of a voltage feedback pin and a current detection pin, and the common ground terminal voltage pin is connected with the common terminal of the control chip;

the control chip can obtain a current sampling signal through the multiplexing pin when the control chip is in a first state; the control chip can obtain a voltage feedback signal through the multiplexing pin when the control chip is in a second state.

In one embodiment of the present invention, the voltage feedback signal is used to represent the output voltage, and the current sampling signal is used to represent the on-state current of a transistor. In the first state, a first voltage at the common ground voltage pin varies with a source voltage of the transistor; in the second state, the first voltage at the common ground voltage pin remains stable.

As an embodiment of the present invention, a pulse width modulation module is disposed in the control chip, and the pulse width modulation module outputs a pulse width modulation signal to control the on/off of the transistor;

when the pulse width modulation signal is at a high level, the transistor is conducted; the control chip can acquire the current flowing through the transistor through the multiplexing pin;

when the pulse width modulation signal is at a low level, no current flows through the transistor; the control chip can obtain a voltage feedback signal through the multiplexing pin.

As an embodiment of the present invention, the transistor is embedded in the control chip, that is, the transistor is a part of the control chip; or, the transistor is arranged outside the control chip.

As an embodiment of the present invention, the sampling resistor Rcs is encapsulated or integrated on the control chip, or the sampling resistor Rcs is disposed outside the control chip.

According to another aspect of the invention, the following technical scheme is adopted: a control circuit comprises the control chip.

As an embodiment of the present invention, the control circuit further includes a sampling resistor, and the control chip is coupled to the sampling resistor; the control circuit further comprises a transistor; a common ground terminal voltage pin of the control chip is coupled with a first end of the sampling resistor;

the transistor and the control chip are independently arranged, the control chip is coupled with the transistor, a gate control input signal pin of the control chip is coupled with the transistor, and a source electrode of the transistor is coupled with the first end of the sampling resistor; or, the transistor is used as a part of a control chip, the control chip is provided with a drain terminal pin, the drain terminal pin of the control chip is coupled with the drain electrode of the transistor, the gate control input signal end of the control chip is connected with the transistor, and the source electrode of the transistor is coupled with the voltage pin of the common ground terminal;

the control chip outputs a pulse width modulation signal through a pulse width modulation module so as to control the on-off of the transistor.

As an embodiment of the present invention, when the pwm signal is at a high level, the transistor is turned on; the control chip can acquire the current flowing through the transistor through the multiplexing pin;

when the pulse width modulation signal is at a low level, no current flows through the transistor; the control chip can obtain the voltage feedback signal through the multiplexing pin.

As an embodiment of the present invention, the control circuit further includes a first voltage-dividing resistor R1 and a second voltage-dividing resistor R2, a second terminal of the first voltage-dividing resistor R1 is connected to a first terminal of the second voltage-dividing resistor R2, and a second terminal of the second voltage-dividing resistor R2 is grounded; the multiplexing pin connects the connection node between the first divider resistor R1 and the second divider resistor R2.

According to another aspect of the invention, the following technical scheme is adopted: a power supply circuit comprises the control circuit.

As an embodiment of the present invention, the power circuit further includes a first capacitor C1 and a second capacitor C2; the control chip is provided with a power supply voltage pin and a compensation pin; the power supply voltage pin is coupled to the first capacitor C1, and the compensation pin is coupled to the second capacitor C2.

As an embodiment of the present invention, the power supply circuit further includes an inductor L, a diode D, a third capacitor C3, and a third resistor R3;

the first end of the inductor L is coupled with the input voltage, and the second end of the inductor L is respectively coupled with the anode of the diode D and the drain of the transistor;

the cathode of the diode D is respectively connected with the output voltage, the first end of the third capacitor C3 and the first end of the third resistor R3; the second terminal of the third capacitor C3 is grounded, and the second terminal of the third resistor R3 is grounded.

According to another aspect of the invention, the following technical scheme is adopted: a control method, the control method comprising: acquiring a current sampling signal through a multiplexing pin when a control chip is in a first state; acquiring a voltage feedback signal through the multiplexing pin when the control chip is in a second state; the multiplexing pin is used as a multiplexing pin of a voltage feedback pin and a current detection pin;

the pulse width modulation module controls the on-off of the transistor by outputting a pulse width modulation signal;

when the pulse width modulation signal is at a high level, the transistor is conducted, and the control chip is in a first state; obtaining the current flowing through the transistor through the multiplexing pin;

when the pulse width modulation signal is at a low level, no current flows through the transistor, and the control chip is in a second state; and acquiring a voltage feedback signal through the multiplexing pin.

As an embodiment of the present invention, when the pwm signal is at a low level, no current flows through the transistor and the sampling resistor Rcs; at this time, the voltage VSS of the common ground terminal is 0, and the voltage FB _ sense corresponding to the voltage feedback obtained by the multiplexing pin is FB _ sense;

when the pulse width modulation signal is at a high level, the transistor is conducted; the voltage of the common ground terminal VSS is Imos Rcs, and the voltage at the multiplexing pin is FB _ sense-Imos Rcs, so that the current flowing through the transistor can be obtained; wherein Imos is the magnitude of the current flowing through the transistor, and Rcs is the resistance value of the sampling resistor Rcs.

The invention has the beneficial effects that: according to the control chip, the control circuit, the power supply circuit and the control method, the FB pin and the CS pin are multiplexed, so that pin arrangement in the control chip circuit can be simplified, the packaging cost of the control chip circuit is effectively reduced, and the system cost is reduced. The invention completes the maximum current detection by time-sharing multiplexing FB without an additional CS pin. The maximum current detection value can be freely set by adjusting the VSS-to-ground resistance.

Drawings

Fig. 1 is a circuit diagram of a boost power supply circuit in the prior art.

Fig. 2 is a circuit signal timing diagram of the power circuit.

Fig. 3 is a circuit diagram of a control chip (and a control circuit) according to an embodiment of the invention.

FIG. 4 is a circuit signal timing diagram of the control circuit according to an embodiment of the present invention.

Fig. 5 is a circuit diagram illustrating an embodiment of a control chip and a control circuit applied to a power circuit.

Fig. 6 is a circuit diagram illustrating an embodiment of a control chip and a control circuit applied to a Buck circuit.

Fig. 7 is a circuit diagram of a control chip and a control circuit applied in a flyback circuit according to an embodiment of the present invention.

FIG. 8 is a circuit signal timing diagram of the control circuit according to an embodiment of the present invention.

Fig. 9 is a circuit diagram of a control chip and a control circuit according to an embodiment of the invention.

Detailed Description

Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

For a further understanding of the invention, reference will now be made to the preferred embodiments of the invention by way of example, and it is to be understood that the description is intended to further illustrate features and advantages of the invention, and not to limit the scope of the claims.

The description in this section is for several exemplary embodiments only, and the present invention is not limited only to the scope of the embodiments described. It is within the scope of the present disclosure and protection that the same or similar prior art means and some features of the embodiments may be interchanged.

The "plurality" in the specification means two or more. "coupled" or "connected" in this specification includes both direct and indirect connections, such as through some active device, passive device, or electrically conductive medium; but also may include connections through other active or passive devices, such as through switches, follower circuits, etc., that are known to those skilled in the art for achieving the same or similar functional objectives.

The invention discloses a control chip which is provided with a multiplexing pin and a VSS pin (namely a common ground terminal voltage pin), wherein the multiplexing pin is used as a multiplexing pin of a voltage feedback pin FB and a current detection pin CS, and the VSS pin is connected with a common terminal GND of the chip. The control chip can obtain a current sampling signal through the multiplexing pin when the control chip is in a first state; the control chip can obtain a voltage feedback signal through the multiplexing pin when the control chip is in a second state. Compared with the prior art, the control chip has a larger range of output power of a power supply system, and has lower requirements on the input voltage range of the comparator used for overcurrent protection in the control chip. That is, in the present invention, the same comparator can be used for different output powers. The prior art needs to design the corresponding comparators according to different output powers.

In an embodiment of the invention, the voltage feedback signal is used for representing the output voltage, and the current sampling signal is used for representing the on-state current of a transistor in the on-state. In the first state, a first voltage at the common ground voltage pin varies with a source voltage of the transistor; in the second state, the first voltage at the common ground voltage pin remains stable. For example, the on-current may be a current flowing through a transistor, a current flowing through a device coupled to a drain of the transistor, or a current flowing through a device coupled to a source of the transistor. The first state is a transistor on state, and the second state is a transistor off state. In the first state, the first voltage at the voltage pin of the common ground terminal changes along with the voltage of the source electrode of the transistor, and after the current flowing in the transistor gradually increases, the voltage of the source electrode gradually increases because the source electrode terminal of the transistor is coupled with the sampling resistor, so that the first voltage also changes according to the change of the conduction current, and the first voltage can reflect the change trend information of the conduction current. In the second state, the first voltage is stable, and the first voltage may be a constant value or may vary slightly within a certain range.

In an embodiment of the present invention, a pulse width modulation module is disposed in the control chip, and the pulse width modulation module outputs a PWM signal to control on/off of the transistor. When the pulse width modulation signal PWM is at a high level, the transistor is conducted; the control chip can acquire the magnitude of current flowing through the transistor through the multiplexing pin to acquire a current sampling signal; when the pulse width modulation signal PWM is at a low level, no current flows through the transistor; the control chip can obtain a voltage feedback signal through the multiplexing pin.

In an embodiment of the invention, the control chip includes a GATE control input signal pin GATE, and the pulse width modulation module is coupled to the GATE control input signal pin GATE.

FIG. 3 is a circuit diagram of a control chip according to an embodiment of the present invention; referring to fig. 3, in an embodiment of the invention, the voltage feedback pin FB and the current detection pin CS are multiplexed, and the VSS pin is connected to the sampling resistor Rcs. The control chip is provided with a pulse width modulation module which is coupled with the GATE pin. The pulse width modulation module controls the on-off of the transistor by outputting a PWM signal.

In an embodiment of the present invention, the transistor M may be an MOS transistor, and of course, the transistor may also be another transistor besides the MOS transistor.

In an embodiment of the invention, the control chip includes a transistor, that is, the transistor is enclosed in the control chip, and the transistor is used as a part of the control chip. FIG. 9 is a circuit diagram of a control chip and a control circuit according to an embodiment of the invention; referring to fig. 9, a transistor M is embedded in the control chip, and the transistor M is used as a part of the control chip. The Drain of the transistor M is coupled to a Drain pin of the control chip, and the source of the transistor M is coupled to a common ground voltage pin VSS of the control chip.

In another embodiment of the present invention, the transistor is disposed outside the control chip. As shown in fig. 3, the transistor M is disposed outside the control chip, a GATE of the transistor M is coupled to a GATE pin of the control chip, and a source of the transistor M is coupled to a VSS pin.

In an embodiment of the invention, the common ground voltage pin VSS is connected to the sampling resistor Rcs. The multiplexing pin connects the connection node between the first divider resistor R1 and the second divider resistor R2.

In an embodiment of the present invention, the sampling resistor Rcs is enclosed or integrated on the control chip to provide a constant CS current limit; in another embodiment of the present invention, the sampling resistor Rcs is disposed outside the control chip.

In an embodiment of the present invention, the control chip is provided with a power voltage pin VCC and a compensation pin COMP; the power supply voltage pin VCC is coupled to the first capacitor C1, and the compensation pin COMP is coupled to the second capacitor C2.

FIG. 4 is a timing diagram of circuit signals of the control chip according to an embodiment of the present invention; referring to fig. 4, in an embodiment of the invention, when the PWM signal is at a high level (on state), the transistor is turned on, and the control chip is in the first state, and the current sampling signal is obtained through the multiplexing pin. When the PWM signal is at a low level (off state), no current flows through the transistor and the resistor Rcs, and the control chip is in the second state, and acquires the voltage feedback signal through the multiplexing pin.

FIG. 8 is a timing diagram of circuit signals of the control chip according to an embodiment of the present invention, and FIG. 8 shows V in the switching process of the PWM signal Gate_FB/CSTiming diagrams of signals, FB signals, CS signals, and CS +0.5V signals; referring to fig. 8, in an embodiment of the invention, when the PWM signal is at a high level (on state), the transistor is turned on, and the control chip is in the first state, and the current sampling signal is obtained through the multiplexing pin. At this time, the voltage of the common ground terminal VSS is Imos Rcs, so that the voltage of the common ground terminal of the control chip is raised, and at this time, the voltage corresponding to the voltage feedback obtained by the multiplexing pin is FB _ sense-Imos Rcs, and the voltage is reflected in the stage of the Gate on stateThe VFB/CS line is in a descending trend; wherein Imos is the magnitude of the current flowing through the transistor, and Rcs is the resistance value of the sampling resistor Rcs. When the PWM signal is at a low level (off state), no current flows through the transistor and the resistor Rcs, and the control chip is in the second state, and acquires the voltage feedback signal through the multiplexing pin. At this time, the voltage VSS of the common ground terminal is 0, and the voltage FB _ sense corresponding to the voltage feedback obtained by the multiplexing pin is FB _ sense. To prevent interference, the sampled voltage feedback signal is masked after Gate off. The overcurrent protection OCP of the control chip is realized by comparing the CS superposed with the OCP voltage with the FB. When Vocp ═ 0.5V, OCP protection is triggered when the voltage is monitored to meet the condition.

Therefore, when the PWM signal is at a high level, the control chip can know the current flowing through the transistor through the FB/CS pin (multiplexing pin) (obtain a current sampling signal); when the PWM signal is at low level, the control chip can obtain the voltage feedback signal through the FB/CS pin. Through FB/CS pin multiplexing, can learn voltage feedback signal and current sampling signal in real time, simplified the pin arrangement in the control chip.

In an embodiment of the present invention, the CS current may be detected by detecting a voltage difference (Δ V) of the multiplexing pin FB/CS dropping at the on time, or may be detected by detecting a minimum voltage (Vmin) of the dropping point at the on time.

In an embodiment of the present invention, the waveform may start to be detected at the on time, or may start to be detected after a certain time delay (for example, 0.5us or other time).

The invention discloses a control circuit which comprises the control chip.

In an embodiment of the present invention, the control circuit further includes a sampling resistor, and the control chip is coupled to the sampling resistor; the control circuit further comprises a transistor; and a common ground terminal voltage pin of the control chip is coupled with the first end of the sampling resistor. In an embodiment of the present invention, the transistor and the control chip are independently disposed, the control chip is coupled to the transistor, a gate control input signal pin of the control chip is coupled to the transistor, and a source of the transistor is coupled to the first end of the sampling resistor; in another embodiment of the present invention, the transistor is used as a part of a control chip, the control chip has a drain terminal pin, the drain terminal pin of the control chip is coupled to a drain of the transistor, a gate control input signal terminal of the control chip is connected to the transistor, and a source of the transistor is coupled to the common ground terminal voltage pin. The control chip outputs a pulse width modulation signal through a pulse width modulation module so as to control the on-off of the transistor.

In an embodiment of the present invention, referring to fig. 3, fig. 3 discloses a circuit schematic diagram of a control circuit in an embodiment of the present invention, where the control circuit further includes a MOS transistor M (of course, other transistors may also be used), and a sampling resistor Rcs, a source of the MOS transistor is connected to a first end of the sampling resistor Rcs, a second end of the sampling resistor Rcs is grounded, and the VSS pin is connected to the first end of the sampling resistor Rcs; a GATE control input signal pin GATE of the control chip is connected with a grid electrode of the MOS tube M; the control chip outputs a PWM signal through a pulse width modulation module to control the on-off of the MOS tube; may be combined with fig. 3.

In an embodiment of the invention, the transistor is disposed outside the control chip. As shown in fig. 3, the transistor M is disposed outside the control chip, a GATE of the transistor M is coupled to a GATE pin of the control chip, and a source of the transistor M is coupled to a VSS pin.

In another embodiment of the present invention, the transistor is used as a part of the control chip, that is, the control chip includes the transistor, and the transistor is sealed in the control chip. In an embodiment of the invention, the control chip has a drain terminal pin, the drain terminal pin of the control chip is coupled to the drain of the transistor, the gate control input signal terminal of the control chip is connected to the transistor, and the source of the transistor is coupled to the common ground terminal voltage pin. FIG. 9 is a circuit diagram of a control chip and a control circuit according to an embodiment of the invention; referring to fig. 9, a transistor M is embedded in the control chip, and the transistor M is used as a part of the control chip. The Drain of the transistor M is coupled to the Drain terminal pin Drain of the control chip, and the source of the transistor M is coupled to the common ground terminal voltage pin VSS of the control chip.

In an embodiment of the present invention, when the PWM signal is at a high level, the MOS transistor is turned on; the control chip can obtain the current flowing through the MOS tube through the multiplexing pin; when the pulse width modulation signal PWM is at a low level, no current flows through the MOS tube; the control chip can obtain the voltage feedback signal through the multiplexing pin.

In an embodiment of the invention, the control circuit further includes a first voltage-dividing resistor R1 and a second voltage-dividing resistor R2, a second terminal of the first voltage-dividing resistor R1 is connected to a first terminal of the second voltage-dividing resistor R2, and a second terminal of the second voltage-dividing resistor R2 is grounded; the multiplexing pin is connected with a connection node between the first divider resistor R1 and the second divider resistor R2; may be combined with fig. 3.

The invention discloses a power supply circuit which comprises the control circuit.

In an embodiment of the invention, the power circuit further includes a first capacitor C1 and a second capacitor C2; the control chip is provided with a power supply voltage pin VCC and a compensation pin COMP; the power supply voltage pin VCC is coupled to the first capacitor C1, and the compensation pin COMP is coupled to the second capacitor C2.

In an embodiment of the invention, the power circuit further includes an inductor L, a diode D, a third capacitor C3, and a third resistor R3; the first end of the inductor L is coupled with the input voltage Vin, and the second end of the inductor L is respectively coupled with the anode of the diode D and the drain of the transistor; the cathode of the diode D is respectively connected with the output voltage Vout, the first end of the third capacitor C3 and the first end of the third resistor R3; the second terminal of the third capacitor C3 is grounded, and the second terminal of the third resistor R3 is grounded.

FIG. 5 is a schematic circuit diagram of a control chip and a control circuit applied in a power circuit (boost power circuit) according to an embodiment of the present invention; referring to fig. 5, in an embodiment of the invention, in the boost power supply circuit, the FB/CS pin is multiplexed, and the FB/CS pin is connected to a connection node between the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2. The common ground terminal voltage pin VSS is connected to the sampling resistor Rcs. The VCC pin and the COMP pin are coupled to a first capacitor C1 and a second capacitor C2, respectively. Through multiplexing of the FB/CS pins, a voltage feedback signal and a current sampling signal in the boost power supply circuit can be obtained in real time, so that pin arrangement in a control chip circuit is simplified. The COMP pin has the following functions: the output point of the internal error amplifier, the external capacitor stabilizes the voltage, and the loop stability is adjusted.

FIG. 6 is a circuit diagram of a Buck circuit to which the control chip and the control circuit are applied according to an embodiment of the present invention; referring to fig. 6, in an embodiment of the invention, in the Buck circuit, the FB/CS pin of the control chip is multiplexed, and the FB/CS pin is connected to a connection node between the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2. The common ground terminal voltage pin VSS is connected to the sampling resistor Rcs. The VCC pin and the COMP pin are coupled to a first capacitor C1 and a second capacitor C2, respectively. Through FB/CS pin multiplexing, still can know voltage feedback signal and current sampling signal in the Buck circuit in real time to pin arrangement in the simplified control chip circuit.

Fig. 7 is a circuit diagram of a control chip and a control circuit applied in a flyback circuit according to an embodiment of the present invention; referring to fig. 7, in an embodiment of the invention, in the flyback circuit, the FB/CS pin of the control chip is multiplexed, and the FB/CS pin is connected to a connection node between the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2. The common ground terminal voltage pin VSS is connected to the sampling resistor Rcs. The VCC pin and the COMP pin are coupled to a first capacitor C1 and a second capacitor C2, respectively. Through FB/CS pin multiplexing, still can learn voltage feedback signal and current sampling signal in the flyback circuit in real time to pin arrangement in the control chip circuit is simplified.

The invention discloses a control method, which comprises the following steps: acquiring a current sampling signal through a multiplexing pin when a control chip is in a first state; acquiring a voltage feedback signal through the multiplexing pin when the control chip is in a second state; the multiplexing pin serves as a multiplexing pin for the voltage feedback pin FB and the current detection pin CS.

In an embodiment of the present invention, the PWM module controls the on/off of the transistor by outputting a PWM signal; when the pulse width modulation signal PWM is at a high level, the transistor is conducted, and the control chip is in a first state; the magnitude of the current flowing through the transistor is acquired through the multiplexing pin (a current sampling signal is acquired). When the pulse width modulation signal PWM is at a low level, no current flows through the transistor, and the control chip is in a second state; and acquiring a voltage feedback signal through the multiplexing pin.

In an embodiment of the present invention, the control method further includes: when the PWM signal is at low level, no current flows through the transistor and the sampling resistor Rcs; at this time, the voltage VSS of the common ground terminal is 0, and the voltage FB _ sense corresponding to the voltage feedback obtained by the multiplexing pin is FB _ sense.

When the pulse width modulation signal PWM signal is at high level, the transistor is conducted; the voltage of the common ground terminal VSS is Imos Rcs, and the voltage at the multiplexing pin is FB _ sense-Imos Rcs, so that the current flowing through the transistor can be obtained; wherein Imos is the magnitude of the current flowing through the transistor, and Rcs is the resistance value of the sampling resistor Rcs.

In summary, the control chip, the control circuit, the power circuit and the control method provided by the invention can simplify the pin arrangement in the control chip circuit by multiplexing the FB pin and the CS pin, thereby effectively reducing the packaging cost of the control chip circuit and reducing the system cost. The invention completes the maximum current detection by time-sharing multiplexing FB without an additional CS pin. The maximum current detection value can be freely set by adjusting the VSS-to-ground resistance.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The description and applications of the invention herein are illustrative and are not intended to limit the scope of the invention to the embodiments described above. Variations and modifications of the embodiments disclosed herein are possible, and alternative and equivalent various components of the embodiments will be apparent to those skilled in the art. It will be clear to those skilled in the art that the present invention may be embodied in other forms, structures, arrangements, proportions, and with other components, materials, and parts, without departing from the spirit or essential characteristics thereof. Other variations and modifications of the embodiments disclosed herein may be made without departing from the scope and spirit of the invention.