阅读说明：本技术 一种电动汽车用降压型dc-dc转换电路 (Step-down DC-DC conversion circuit for electric automobile ) 是由 丁左武 倪永娟 于 2019-09-16 设计创作，主要内容包括：本发明涉及一种电动汽车用降压型DC-DC转换电路,包括输出电压值控制电路,输出电压值控制电路CPU的脉宽调制信号输出端与光耦的输入端相连,光耦的输出端与驱动模块的控制脉冲输入端相连,驱动模块的驱动脉冲输出端分别与各IGBT的栅极相连；各IGBT的集电极均与动力电池正极相连,负载连接在各IGBT的发射极与动力电池负极之间；各IGBT的发射极与动力电池负极之间连接有多个相互并联的负载续流二极管。本发明由动力电池通过DC-DC转换器产生+5V电源供CPU使用,产生+15V电源供驱动模块使用。本发明还设有输入电压值显示电路、输出电压设定及显示电路和实际输出电压值显示电路。无需安装低压蓄电池,节约了汽车的安装空间,节省了采购及更换电池的成本且运行可靠。(The invention relates to a step-down DC-DC conversion circuit for an electric automobile, which comprises an output voltage value control circuit, wherein the pulse width modulation signal output end of a CPU (Central processing Unit) of the output voltage value control circuit is connected with the input end of an optical coupler, the output end of the optical coupler is connected with the control pulse input end of a driving module, and the driving pulse output end of the driving module is respectively connected with the grid electrode of each IGBT; the collector of each IGBT is connected with the anode of the power battery, and the load is connected between the emitter of each IGBT and the cathode of the power battery; and a plurality of load freewheeling diodes which are mutually connected in parallel are connected between the emitting electrode of each IGBT and the negative electrode of the power battery. The invention uses the power battery to generate +5V power supply for CPU through DC-DC converter, and generates +15V power supply for driving module. The invention also comprises an input voltage value display circuit, an output voltage setting and display circuit and an actual output voltage value display circuit. The low-voltage storage battery is not required to be installed, the installation space of the automobile is saved, the cost for purchasing and replacing the battery is saved, and the operation is reliable.)

1. The utility model provides a step-down DC-DC converting circuit for electric automobile, includes output voltage value control circuit, its characterized in that: the output voltage value control circuit comprises a CPU, a pulse width modulation signal output end (CPU-PWM1) of the CPU is connected with an input end of an optical coupler (G1), an output end of the optical coupler (G1) is connected with a control pulse input end (U10-IN) of a driving module (U10), and driving pulse output ends (U10-HO) of the driving module are respectively connected with grids of IGBTs; the collectors of the IGBTs are connected in parallel and then are connected with the positive pole (VIN +) of the power battery through a fuse (RX) and a main switch (K1), and a load (FZ) is connected between the emitter of each IGBT and the negative pole (VIN-) of the power battery; and a plurality of load freewheeling diodes which are mutually connected in parallel are connected between the emitting electrode of each IGBT and the negative electrode (VIN-) of the power battery.

2. The step-down DC-DC converter circuit for an electric vehicle according to claim 1, characterized in that: a pulse width modulation signal output end (CPU-PWM1) of the CPU is connected with an input anode of an optocoupler (G1) through a current limiting resistor R1, an input cathode of the optocoupler (G1) is connected with the CPU-GND, and a pull-down resistor R2 is connected between the input anode and the input cathode of the optocoupler (G1); the collector of the output end of the optical coupler (G1) is connected with a +15V power supply, the emitter of the output end of the optical coupler (G1) is connected with the control pulse input end (U10-IN) of the driving module (U10), the control pulse input end (U10-IN) is connected with the driving ground end (QD-GND) through a pull-down resistor R3, and the output end of the optical coupler (G1) is connected with a freewheeling diode D1 IN parallel; the working power supply end (U10-Vcc) of the driving module (U10) is connected with a +15V power supply, the input ground end (U10-COM) of the driving module (U10) is connected with the driving ground end (QD-GND) and is connected with the +15V power supply through a capacitor C1, the upper end of a load (FZ) is connected with an output stage reference ground end (U10-Vs), the output stage reference ground end (U10-Vs) is connected with the output stage working power supply end (U10-VB) through a capacitor C2, and the output stage working power supply end (U10-VB) is connected with the +15V power supply through a diode D2; the two ends of the load (FZ) are connected in series with a resistor R4 and a capacitor C3.

3. The step-down DC-DC converter circuit for an electric vehicle according to claim 1, characterized in that: an inductor L1 is connected in series between the emitter of each IGBT and the load (FZ), and a capacitor C4 is connected in parallel to both ends of the load (FZ).

4. The step-down DC-DC converter circuit for an electric vehicle according to claim 1, characterized in that: a resistor R5 and a resistor R6 are connected in series between the positive electrode (VIN +) of the power battery and the CPU-GND, an input voltage detection end is connected between the resistor R5 and the resistor R6, and the input voltage detection end is connected with a PAD1 port of the CPU; a resistor R7 and a resistor R8 are connected in series between the upper end of the load (FZ) and the CPU-GND, an output voltage detection end is connected between the resistor R7 and the resistor R8, and the output voltage detection end is connected with the PAD2 port of the CPU.

5. The step-down DC-DC converter circuit for an electric vehicle according to claim 1, characterized in that: the positive pole (VIN +) of the power battery is connected with a thermistor (RM) and a diode D3 in series in sequence and then connected with the positive pole (Vi +) of the input voltage of the DC-DC converter, a piezoresistor (YM) is connected in series between the thermistor (RM) and the negative pole (VIN-) of the power battery and between the thermistor (RM) and the negative pole (Vi-) of the input voltage of the DC-DC converter, and a freewheeling diode D4 and a capacitor C5 are connected in parallel between the positive pole (Vi +) of the input voltage of the DC-DC converter and the negative pole (VIN-) of the power battery; the output cathode I (VO1-) of the DC-DC converter is connected with the CPU-GND, and the output anode I (VO1+) of the DC-DC converter provides +5V power supply for the CPU; the output cathode II (VO2-) of the DC-DC converter is connected with a driving ground terminal (QD-GND), and the output anode II (VO2+) of the DC-DC converter provides +15V power for the driving module (U10); the driving ground terminal (QD-GND) and the negative electrode (VIN-) of the power battery are connected with each other through an inductor L2.

6. The step-down DC-DC converter circuit for an electric vehicle according to claim 5, characterized in that: a freewheeling diode D5 is connected between the output cathode I (VO1-) and the output anode I (VO1+) of the DC-DC converter, an inductor L3 is connected in series between the output anode I (VO1+) of the DC-DC converter and a CPU +5V power supply, and a capacitor C6 and a capacitor C7 are connected in parallel between the CPU +5V power supply and a CPU-GND power supply; a freewheeling diode D6 is connected between the output cathode II (VO2-) and the output anode II (VO2+) of the DC-DC converter, an inductor L4 is connected in series between the output anode II (VO2+) of the DC-DC converter and a driving module +15V power supply, and a capacitor C8 and a capacitor C9 are connected in parallel between the driving module +15V power supply and a driving ground end (QD-GND).

7. The step-down DC-DC converter circuit for an electric vehicle according to claim 3, characterized in that: a temperature sensor (T1) is mounted on the circuit board, a temperature signal output end of the temperature sensor (T1) is connected with a PAD0 port of the CPU, a pull-up resistor R9 is connected in series between the PAD0 port and the CPU +5V power supply, a grounding end of the temperature sensor (T1) is connected with the CPU-GND, and a capacitor C10 is arranged between the PAD0 port of the CPU and the CPU-GND.

8. The step-down DC-DC converter circuit for an electric vehicle according to any one of claims 1 to 7, characterized in that: the conversion circuit is further provided with an input voltage value display circuit, the input voltage value display circuit comprises a first data latch (U1), a second data latch (U2) and a third data latch (U3), data input ends of the first data latch (U1), the second data latch (U2) and the third data latch (U3) are respectively connected with PB0, PB1 to PB7 ends of the CPU, data output ends of the first data latch (U1), the second data latch (U2) and the third data latch (U3) are respectively connected with an input voltage value display digital tube, a chip selection input end of the first data latch (U1) is connected with a PA0 port of the CPU, a chip selection input end of the second data latch (U2) is connected with a PA1 port of the CPU, and a chip selection input end of the third data latch (U3) is connected with a PA2 port of the CPU.

9. The step-down DC-DC converter circuit for an electric vehicle according to any one of claims 1 to 7, characterized in that: the conversion circuit is also provided with an output voltage setting and displaying circuit, wherein the output voltage setting and displaying circuit comprises a data latch four (U4), a data latch five (U5) and a data latch six (U6), the data input ends of the data latch four (U4), the data latch five (U5) and the data latch six (U6) are respectively connected with PB0, PB1 to PB7 ends of the CPU, the data output ends of the data latch four (U4), the data latch five (U5) and the data latch six (U6) are respectively connected with an output voltage setting and displaying digital tube, the chip selection input end of the data latch four (U4) is connected with a PA3 port of the CPU, the chip selection input end of the data latch five (U5) is connected with a PA4 port of the CPU, and the chip selection input end of the data latch six (U6) is connected with a PA5 port of the CPU; the +5V power supply of the CPU is connected with the CPU-GND through a slide rheostat (HR1), and the middle output end of the slide rheostat (HR1) is connected with the PAD0 port of the CPU.

10. The step-down DC-DC converter circuit for an electric vehicle according to any one of claims 1 to 7, characterized in that: the conversion circuit is also provided with an actual output voltage value display circuit, wherein the actual output voltage value display circuit comprises a data latch seven (U7), a data latch eight (U8) and a data latch nine (U9), the data input ends of the data latch seven (U7), the data latch eight (U8) and the data latch nine (U9) are respectively connected with PB0, PB1 to PB7 ends of the CPU, the data output ends of the data latch seven (U7), the data latch eight (U8) and the data latch nine (U9) are respectively connected with an actual output voltage display digital tube, the chip selection input end of the data latch seven (U7) is connected with a PA6 port of the CPU, the chip selection input end of the data latch eight (U8) is connected with a PA7 port of the CPU, and the chip selection input end of the data latch nine (U9) is connected with a PT7 port of the CPU.

Technical Field

The invention relates to a power supply circuit, in particular to a voltage reduction type DC-DC conversion circuit for an electric automobile, and belongs to the technical field of direct-current power supplies for electric automobiles.

Background

With the popularization of electric vehicles, the application of the DC-DC control technology is more and more extensive. The voltage of a power battery on the automobile reaches or exceeds DC500V, and the rated working voltage of high-power automobile electric appliances such as an air conditioner, a blower, a compressor, a headlamp, a horn and the like on the electric automobile is DC12V or DC 24V. The conventional scheme of the electric automobile is to utilize a special storage battery for the vehicle-mounted electric appliance of DC12V or DC24V, utilize a DC-DC converter to convert the high voltage of a power battery into lower voltage, and charge the storage battery for the vehicle-mounted electric appliance of DC12V or DC 24V.

The traditional scheme has the following defects: 1. on the basis of the high-voltage power battery, the low-voltage storage battery is added, the purchasing and replacing cost of the battery is increased, the battery needs to occupy larger installation space, and the no-load weight of the automobile is increased.

2. In order to ensure the normal operation of the vehicle-mounted electrical equipment in the running process of the automobile, a storage battery for the vehicle-mounted electrical equipment is charged by a power battery by using a DC-DC converter.

3. The storage battery for the vehicle-mounted electric appliance is charged through twice conversion between electric energy and chemical energy, so that the electricity utilization efficiency is greatly reduced.

Disclosure of Invention

The invention aims to overcome the problems in the prior art and provide a voltage-reducing DC-DC conversion circuit for an electric automobile, wherein vehicle-mounted electric appliances can share a power battery, a low-voltage storage battery does not need to be additionally installed, or only a storage battery with smaller capacity needs to be installed, so that the installation space of the automobile is saved, the cost for purchasing and replacing the battery is saved, and the operation is reliable.

IN order to solve the technical problem, the step-down DC-DC conversion circuit for the electric automobile comprises an output voltage value control circuit, wherein the output voltage value control circuit comprises a CPU (Central processing Unit), a pulse width modulation signal output end CPU-PWM1 of the CPU is connected with an input end of an optical coupler G1, an output end of the optical coupler G1 is connected with a control pulse input end U10-IN of a driving module U10, and driving pulse output ends U10-HO of the driving module are respectively connected with grids of IGBTs; the collectors of the IGBTs are connected in parallel and then are connected with the positive electrode VIN + of the power battery through a fuse RX and a main switch K1, and a load FZ is connected between the emitter of each IGBT and the negative electrode VIN-of the power battery; and a plurality of load freewheeling diodes which are mutually connected in parallel are connected between the emitting electrode of each IGBT and the negative electrode VIN-of the power battery.

Compared with the prior art, the invention has the following beneficial effects: the load FZ can be air conditioners, blowers, compressors, headlights, loudspeakers and other high-power automotive electrical appliances on the electric automobile, and a plurality of automotive electrical appliances can generate larger working current when being started simultaneously, so that the rated working current of a single IGBT can reach 150A, but the heat dissipation of the IGBT in practical application cannot reach the optimal state; the pins of the IGBT cannot bear large current for a long time; the excessive current causes the internal resistance of the IGBT to generate heat seriously. The heat generated during the turn-on and turn-off of the IGBT seriously affects the safe operation of the controller. The invention adopts a plurality of IGBTs 1 and 2 to IGBTn which are connected in parallel to drive the load FZ, and adopts a plurality of load freewheeling diodes EJG1 and EJG2 to EJGn which are connected in parallel to freewheel. An MC9S12XS128MAA single chip microcomputer is used as a control system CPU of the high-power DC-DC converter. When the IGBT1, the IGBT2 to IGBTn are turned off, the self-inductance current of the load FZ generated by the self-inductance electromotive force can be consumed inside the load FZ through the load freewheel diodes EJG1, EJG2 to EJGn. A duty ratio signal output by a pulse width modulation signal output end CPU-PWM1 of the CPU is isolated by high voltage and low voltage of an optical coupler G1 and sent to a control pulse input end U10-IN of a driving module U10, the duty ratio signal is output by a driving pulse output end U10-HO after being amplified by the driving module U10, and the duty ratios of the IGBT1, the IGBT2 and the IGBTn are controlled after current limiting through current limiting resistors XLR1 and XLR2 to XLRn, so that the rated voltage requirement of a load FZ is met.

As an improvement of the invention, a pulse width modulation signal output end CPU-PWM1 of the CPU is connected with an input anode of an optocoupler G1 through a current-limiting resistor R1, an input cathode of the optocoupler G1 is connected with a CPU-GND, and a pull-down resistor R2 is connected between the input anode and the input cathode of the optocoupler G1; a collector at the output end of the optical coupler G1 is connected with a +15V power supply, an emitter at the output end of the optical coupler G1 is connected with a control pulse input end U10-IN of the driving module U10, the control pulse input end U10-IN is connected with a QD-GND (ground level) end through a pull-down resistor R3, and an output end of the optical coupler G1 is connected with a freewheeling diode D1 IN parallel; the working power supply end U10-Vcc of the driving module U10 is connected with a +15V power supply, the input ground end U10-COM of the driving module U10 is connected with a driving ground end QD-GND and is connected with a +15V power supply through a capacitor C1, the upper end of a load FZ is connected with an output stage reference ground end U10-Vs, the output stage reference ground end U10-Vs is connected with an output stage working power supply end U10-VB through a capacitor C2, and the output stage working power supply end U10-VB is connected with a +15V power supply through a diode D2; the two ends of the load FZ are connected in series with a resistor R4 and a capacitor C3. A duty ratio signal output by a pulse width modulation signal output end CPU-PWM1 of the CPU is limited by a current limiting resistor R1 and then is sent to an input end of an optical coupler G1, when a pull-down resistor R2 ensures that the CPU-PWM1 outputs a logic level '0', the level of the input end of the optical coupler G1 is also logic '0', and a light-emitting diode ensures that the light-emitting diode can be reliably cut off; when the voltage at the control pulse input end U10-IN of the driving module U10 suddenly rises, the freewheeling diode D1 freewheels; the capacitor C1 is used as a voltage stabilizing capacitor, and the capacitor C2 and the diode D2 form a bootstrap circuit to generate VB voltage; the resistor R4 and the capacitor C3 form a tank circuit. After the drive module U10 amplifies the duty ratio signal input by the control pulse input end U10-IN, the same duty ratio is output by the drive pulse output end U10-HO to control the on-off of the IGBT1, the IGBT2 and the IGBTn.

As a further improvement of the present invention, an inductor L1 is connected in series between the emitter of each IGBT and the load FZ, and a capacitor C4 is connected in parallel to both ends of the load FZ. The inductor L1 and the capacitor C4 form an LC filter circuit and a voltage stabilizing circuit, and the stability of the terminal voltage of the load FZ can be improved.

As a further improvement of the invention, a resistor R5 and a resistor R6 are connected in series between the positive electrode VIN + of the power battery and the CPU-GND, an input voltage detection end is connected between the resistor R5 and the resistor R6, and the input voltage detection end is connected with a PAD1 port of the CPU; a resistor R7 and a resistor R8 are connected in series between the upper end of the load FZ and the CPU-GND, an output voltage detection end is connected between the resistor R7 and the resistor R8, and the output voltage detection end is connected with the PAD2 port of the CPU. The CPU reads the PAD1 value, and through interpolation, the input voltage value can be calculated to judge the power of the power battery. The CPU reads the PAD2 value and through interpolation, calculates the actual output voltage value to determine whether the rated voltage requirement of the load FZ is met.

As a further improvement of the invention, a power battery anode VIN + is connected with a thermistor RM and a diode D3 in series in sequence and then is connected with an input voltage anode Vi + of the DC-DC converter, a piezoresistor YM is connected in series between the thermistor RM and a power battery cathode VIN-and between the thermistor RM and the input voltage cathode Vi-of the DC-DC converter, and a fly-wheel diode D4 and a capacitor C5 are connected in parallel between the input voltage anode Vi + of the DC-DC converter and the power battery cathode VIN-; the output cathode I VO 1-of the DC-DC converter is connected with the CPU-GND, and the output anode I VO1+ of the DC-DC converter provides +5V power supply for the CPU; an output cathode two VO 2-of the DC-DC converter is connected with a driving ground end QD-GND, and an output anode two VO2+ of the DC-DC converter provides a +15V power supply for a driving module U10; the driving ground QD-GND and the negative electrode VIN-of the power battery are connected with each other through an inductor L2. The power supply voltage for the CPU is +5V, and the power supply voltage for the driving module U10 is + 15V; and a +5V power supply and a +15V power supply are provided by using a low-power finished product DC-DC converter with low power and two-way voltage output. The input VIN-, CPU-GND \ QD-GND of the low-power finished product DC-DC converter are mutually isolated. When the working current of the load FZ is relatively large, the end voltage of the power battery is easily reduced, and the end voltage is unstable. The thermistor RM is a positive temperature coefficient, so that the impact of the terminal voltage of the power battery on the input voltage of the DC-DC converter when the terminal voltage of the power battery is greatly changed can be effectively buffered; the piezoresistor YM can further buffer the impact of the self-induced electromotive force of the load FZ on the DC-DC converter when the IGBT is switched off; after the terminal voltage of the power battery is reduced to be lower than the allowable input voltage of the DC-DC converter, the diode D3 can effectively prevent the current from flowing backwards; the capacitor C5 acts as a voltage regulator to keep the input voltage of the DC-DC converter above the minimum allowable input voltage for a longer period of time. The inductance L2 can reduce the influence of the voltage variation at the VIN-terminal of the power battery on the driving module QD-GND.

As a further improvement of the invention, a fly-wheel diode D5 is connected between an output cathode VO 1-and an output anode VO1+ of the DC-DC converter, an inductor L3 is connected in series between an output anode VO1+ of the DC-DC converter and a CPU +5V power supply, and a capacitor C6 and a capacitor C7 are connected in parallel between the CPU +5V and the CPU-GND; a freewheeling diode D6 is connected between the output cathode two VO2 & lt- & gt and the output anode two VO2 & lt- & gt of the DC-DC converter, an inductor L4 is connected in series between the output anode two VO2 & lt + & gt of the DC-DC converter and a driving module +15V power supply, and a capacitor C8 and a capacitor C9 are connected in parallel between the driving module +15V power supply and a driving ground end QD-GND. The inductor L3, the capacitor C6 and the capacitor C7 form a filter circuit and a voltage stabilizing circuit of the +5V power supply, so that the voltage of the +5V power supply of the CPU can be more stable, and when the voltage of the CPU-GND suddenly rises, the freewheeling diode D5 freewheels. The inductor L4, the capacitor C8 and the capacitor C9 form a filter circuit and a voltage stabilizing circuit of the +15V power supply, so that the voltage of the +15V power supply of the driving module U10 can be more stable, and when the voltage of the driving ground end QD-GND suddenly rises, the freewheeling diode D6 freewheels.

As a further improvement of the invention, a T1 of a temperature sensor is mounted on the circuit board, a temperature signal output end of the T1 of the temperature sensor is connected with a PAD0 port of the CPU, a pull-up resistor R9 is connected in series between the PAD0 port and a CPU +5V power supply, a grounding end of the T1 of the temperature sensor is connected with the CPU-GND, and a capacitor C10 is arranged between the PAD0 port of the CPU and the CPU-GND. T1 of the temperature sensor is a negative temperature coefficient, the resistance value at 100 ℃ is 4.52k omega, and the resistance value at 20 ℃ is 42.16k omega; the CPU reads the PAD0 value, and calculates the temperature value of the circuit board by interpolation, if the temperature of the circuit board is too high, the duty ratio output by the pulse width modulation signal output end CPU-PWM1 of the CPU can be 0/4, and the load FZ stops working.

As a further improvement of the invention, the conversion circuit is further provided with an input voltage value display circuit, the input voltage value display circuit comprises a first data latch U1, a second data latch U2 and a third data latch U3, data input ends of the first data latch U1, the second data latch U2 and the third data latch U3 are respectively connected with PB0, PB1 to PB7 ends of the CPU, data output ends of the first data latch U1, the second data latch U2 and the third data latch U3 are respectively connected with an input voltage value display digital tube, a chip selection input end of the first data latch U1 is connected with a PA0 port of the CPU, a chip selection input end of the second data latch U2 is connected with a PA1 port of the CPU, and a chip selection input end of the third data latch U3 is connected with a PA2 port of the CPU. The CPU sends the calculated input voltage values to data input ends of a first data latch U1, a second data latch U2 and a third data latch U3 through ports PB0, PB1 and PB7, a PA0 port of the CPU controls a chip selection input end of the first data latch U1, a PA1 port controls a chip selection input end of a second data latch U2, and a PA2 port controls a chip selection input end of the third data latch U3, so that the input voltage value display nixie tube can correctly display the input voltage values, and a driver can know and judge the electric quantity of the power battery in time.

As a further improvement of the present invention, the conversion circuit is further provided with an output voltage setting and display circuit, the output voltage setting and display circuit comprises a data latch four U4, a data latch five U5 and a data latch six U6, data input ends of the data latch four U4, the data latch five U5 and the data latch six U6 are respectively connected with PB0, PB1 to PB7 ends of the CPU, data output ends of the data latch four U4, the data latch five U5 and the data latch six U6 are respectively connected with an output voltage setting and display digital tube, a chip selection input end of the data latch four U4 is connected with a PA3 port of the CPU, a chip selection input end of the data latch five U5 is connected with a PA4 port of the CPU, and a chip selection input end of the data latch six U6 is connected with a PA5 port of the CPU; the +5V power supply of the CPU is connected with the CPU-GND through a sliding rheostat HR1, and the middle output end of the sliding rheostat HR1 is connected with the PAD0 port of the CPU. The CPU calculates the set value of the output voltage to be 12V, 24V or other voltage values by adjusting the resistance value of the sliding rheostat HR1 and changes the voltage value received by the PAD0 port of the CPU, and sends the set value of the output voltage to the data input ends of the data latch four U4, the data latch five U5 and the data latch six U6 through the ports PB0, PB1 to PB7 of the CPU, the PA3 port controls the chip selection input end of the data latch four U4, the PA4 port controls the chip selection input end of the data latch five U5, and the PA5 port controls the chip selection input end of the data latch six U6, so that the set value of the output voltage is set and displayed by a display nixie tube. After the output voltage set value is accurately adjusted, the sliding rheostat HR1 can be sealed by glue. Therefore, the DC-DC conversion circuit can meet the requirements of different load voltages of various vehicle types and has great adaptability.

As a further improvement of the invention, the conversion circuit is further provided with an actual output voltage value display circuit, the actual output voltage value display circuit comprises a data latch seven U7, a data latch eight U8 and a data latch nine U9, data input ends of the data latch seven U7, the data latch eight U8 and the data latch nine U9 are respectively connected with PB0, PB1 to PB7 ends of the CPU, data output ends of the data latch seven U7, the data latch eight U8 and the data latch nine U9 are respectively connected with an actual output voltage display digital tube, a chip selection input end of the data latch seven U7 is connected with a PA6 port of the CPU, a chip selection input end of the data latch eight U8 is connected with a PA7 port of the CPU, and a chip selection input end of the data latch nine U9 is connected with a PT7 port of the CPU. The CPU sends the calculated actual output voltage value to the data input ends of a data latch seven U7, a data latch eight U8 and a data latch nine U9 through PB0, PB1 and PB7 ports, a PA6 port of the CPU controls the chip selection input end of the data latch seven U7, a PA7 port controls the chip selection input end of the data latch eight U8, and a PT7 port controls the chip selection input end of the data latch nine U9, so that the actual output voltage display nixie tube can correctly display the actual output voltage value, and the output voltage value is constant by utilizing a PID algorithm.

Drawings

The invention will be described in further detail with reference to the following drawings and detailed description, which are provided for reference and illustration purposes only and are not intended to limit the invention.

FIG. 1 is a schematic diagram of an input voltage value display circuit according to the present invention.

FIG. 2 is a schematic diagram of an output voltage setting and display circuit according to the present invention.

FIG. 3 is a schematic diagram of an actual output voltage display circuit according to the present invention.

FIG. 4 is a schematic diagram of an output voltage control circuit according to the present invention.

FIG. 5 is a circuit diagram of the +5V/+15V power supply for the control system of the present invention.

FIG. 6 is a circuit diagram of the temperature detection circuit of the circuit board of the present invention.

FIG. 7 is a circuit diagram of the CPU according to the present invention.

Detailed Description

As shown in fig. 1, the buck DC-DC conversion circuit for an electric vehicle of the present invention is provided with an input voltage value display circuit, the input voltage value display circuit includes a first data latch U1, a second data latch U2, and a third data latch U3, data input terminals of the first data latch U1, the second data latch U2, and the third data latch U3 are respectively connected to PB0, PB1 to PB7 terminals of the CPU, data output terminals of the first data latch U1, the second data latch U2, and the third data latch U3 are respectively connected to an input voltage value display digital pipe, a chip select input terminal of the first data latch U1 is connected to a PA0 port of the CPU, a chip select input terminal of the second data latch U2 is connected to a PA1 port of the CPU, and a chip select input terminal of the third data latch U3 is connected to a PA2 port of the CPU.

As shown in fig. 2, the step-down DC-DC conversion circuit for an electric vehicle of the present invention is provided with an output voltage setting and display circuit, the output voltage setting and display circuit includes a data latch four U4, a data latch five U5 and a data latch six U6, data input terminals of the data latch four U4, the data latch five U5 and the data latch six U6 are respectively connected to PB0, PB1 to PB7 terminals of the CPU, data output terminals of the data latch four U4, the data latch five U5 and the data latch six U6 are respectively connected to an output voltage setting and display digital tube, a chip selection input terminal of the data latch four U4 is connected to a PA3 port of the CPU, a chip selection input terminal of the data latch five U5 is connected to a PA4 port of the CPU, and a chip selection input terminal of the data latch six U6 is connected to a PA5 port of the CPU; the +5V power supply of the CPU is connected with the CPU-GND through a sliding rheostat HR1, and the middle output end of the sliding rheostat HR1 is connected with the PAD0 port of the CPU.

As shown in fig. 3, the actual output voltage value display circuit in the step-down DC-DC conversion circuit for the electric vehicle of the present invention includes a data latch seven U7, a data latch eight U8, and a data latch nine U9, data input terminals of the data latch seven U7, the data latch eight U8, and the data latch nine U9 are respectively connected to PB0, PB1 to PB7 terminals of the CPU, data output terminals of the data latch seven U7, the data latch eight U8, and the data latch nine U9 are respectively connected to an actual output voltage display digital pipe, a chip select input terminal of the data latch seven U7 is connected to a PA6 port of the CPU, a chip select input terminal of the data latch eight U8 is connected to a PA7 port of the CPU, and a chip select input terminal of the data latch nine U9 is connected to a PT7 port of the CPU.

As shown in fig. 1, the CPU reads the value of the CPU-PAD1, and sends the calculated hundred bits of the input voltage value to the data input terminals of the data latch one U1 to the data latch nine U9 through the ports PB0, PB1 to PB7, the chip select PA0 port of the CPU sets logic "1", the PA1, PA2, PA3, PA4, PA5, PA6, PA7, and PT7 all set logic "0", and the hundred bits of the input voltage value are displayed through the LED nixie tube connected to the data latch one U1.

The CPU sends ten bits of the calculated input voltage value to data input ends of a first data latch U1 to a ninth data latch U9 through ports PB0 and PB1 to PB7, a chip selection PA1 port of the CPU is used for setting logic '1', PA0, PA2, PA3, PA4, PA5, PA6, PA7 and PT7 are all set to logic '0', and ten bits of the input voltage value are displayed through an LED nixie tube connected with the second data latch U2.

The CPU sends the calculated bits of the input voltage value to the data input ends of the first data latch U1 to the ninth data latch U9 through PB0 and PB1 to PB7 ports, a logic '1' is set at a chip selection PA2 port of the CPU, PA0, PA1, PA3, PA4, PA5, PA6, PA7 and PT7 are all set to be logic '0', and the bits of the input voltage value are displayed through an LED nixie tube connected with the third data latch U3. The input voltage value is used for the driver to know and judge the electric quantity of the power battery in time.

As shown in fig. 2, the voltage value received by the PAD0 port of the CPU is changed by adjusting the resistance value of the sliding rheostat HR1, the CPU reads the value of the CPU-PAD0, and sends the hundred bits of the calculated output voltage set value to the data input end of the data latch one U1 to the data latch nine U9 through the PB0, PB1 to PB7 ports, logic "1" is set by the chip selection PA3 port of the CPU, and logic "0" is set by the PA0, PA1, PA2, PA4, PA5, PA6, PA7 and PT7, and the hundred bits of the output voltage set value are displayed by the LED nixie tube connected with the data latch four U4.

The CPU sends ten bits of the calculated output voltage set value to data input ends of a first data latch U1 to a ninth data latch U9 through ports PB0 and PB1 to PB7, a chip selection PA4 port of the CPU is used for setting logic '1', PA0, PA1, PA2, PA3, PA5, PA6, PA7 and PT7 are all set to logic '0', and ten bits of the output voltage set value are displayed through an LED nixie tube connected with the fifth data latch U5.

The CPU sends the calculated bits of the output voltage set value to data input ends of a data latch I1-a data latch nine U9 through ports PB0 and PB 1-PB 7, a chip selection PA5 port of the CPU sets logic '1', PA0, PA1, PA2, PA3, PA4, PA6, PA7 and PT7 all set logic '0', and the bits of the output voltage set value are displayed through an LED nixie tube connected with the data latch six U6. The set value of the output voltage is provided for a driver to know and judge the output voltage condition of the power battery in time. After the output voltage set value is accurately adjusted, the sliding rheostat HR1 can be sealed by glue. Therefore, the DC-DC conversion circuit can meet the requirements of different load voltages of various vehicle types and has great adaptability.

As shown in fig. 3, the CPU reads the value of the CPU-PAD2, and sends the calculated hundreds of actual output voltage values to the data input terminals of the data latch one U1 to the data latch nine U9 through the ports PB0, PB1 to PB7, the CPU sets logic "1" at the port PA6, and sets logic "0" at the ports PA0, PA1, PA2, PA3, PA4, PA5, PA7, and PT7, and the hundreds of actual output voltage values are displayed through the LED nixie tube connected to the data latch seven U7.

The CPU sends ten bits of the actual output voltage value obtained through calculation to data input ends of a data latch I U1 to a data latch nine U9 through ports PB0 and PB1 to PB7, a chip selection PA7 port of the CPU is used for setting logic '1', PA0, PA1, PA2, PA3, PA4, PA5, PA6 and PT7 are all used for setting logic '0', and ten bits of the actual output voltage value are displayed through an LED nixie tube connected with the data latch eight U8.

The CPU sends the calculated bits of the actual output voltage value to the data input ends of a data latch I1 to a data latch nine U9 through ports PB0 and PB1 to PB7, a logic '1' is set by a chip selection PT7 port of the CPU, PA0, PA1, PA2, PA3, PA4, PA5, PA6 and PA7 are all set to be logic '0', and the bits of the actual output voltage value are displayed through an LED nixie tube connected with the data latch nine U9. The actual output voltage display nixie tube can correctly display the actual output voltage value, and the PID algorithm is utilized to realize the constancy of the actual output voltage value.

As shown IN fig. 4 and 7, the step-down DC-DC conversion circuit for an electric vehicle of the present invention is provided with an output voltage value control circuit, the output voltage value control circuit includes a CPU, a pulse width modulation signal output terminal CPU-PWM1 of the CPU is connected to an input terminal of an optocoupler G1, an output terminal of the optocoupler G1 is connected to a control pulse input terminal U10-IN of a driving module U10, and driving pulse output terminals U10-HO of the driving module are respectively connected to gates of IGBTs; the collectors of the IGBTs are connected in parallel and then are connected with the positive electrode VIN + of the power battery through a fuse RX and a main switch K1, and a load FZ is connected between the emitter of each IGBT and the negative electrode VIN-of the power battery; and a plurality of load freewheeling diodes which are mutually connected in parallel are connected between the emitting electrode of each IGBT and the negative electrode VIN-of the power battery.

The load FZ can be air conditioners, blowers, compressors, headlights, loudspeakers and other high-power automotive electrical appliances on the electric automobile, and a plurality of automotive electrical appliances can generate larger working current when being started simultaneously, so that the rated working current of a single IGBT can reach 150A, but the heat dissipation of the IGBT in practical application cannot reach the optimal state; the pins of the IGBT cannot bear large current for a long time; the excessive current causes the internal resistance of the IGBT to generate heat seriously. The heat generated during the turn-on and turn-off of the IGBT seriously affects the safe operation of the controller.

The invention adopts a plurality of IGBTs 1 and 2 to IGBTn which are connected in parallel to drive the load FZ, and adopts a plurality of load freewheeling diodes EJG1 and EJG2 to EJGn which are connected in parallel to freewheel. An MC9S12XS128MAA single chip microcomputer or other similar single chip microcomputers can be used as a control system CPU of the high-power DC-DC converter. When the IGBT1, the IGBT2 to IGBTn are turned off, the self-inductance current of the load FZ generated by the self-inductance electromotive force can be consumed inside the load FZ through the load freewheel diodes EJG1, EJG2 to EJGn. A duty ratio signal output by a pulse width modulation signal output end CPU-PWM1 of the CPU is isolated by high voltage and low voltage of an optical coupler G1 and sent to a control pulse input end U10-IN of a driving module U10, the duty ratio signal is output by a driving pulse output end U10-HO after being amplified by the driving module U10, and the duty ratios of the IGBT1, the IGBT2 and the IGBTn are controlled after current limiting through current limiting resistors XLR1 and XLR2 to XLRn, so that the rated voltage requirement of a load FZ is met.

A pulse width modulation signal output end CPU-PWM1 of the CPU is connected with an input anode of an optocoupler G1 through a current limiting resistor R1, an input cathode of the optocoupler G1 is connected with a CPU-GND, and a pull-down resistor R2 is connected between the input anode and the input cathode of the optocoupler G1; a collector at the output end of the optical coupler G1 is connected with a +15V power supply, an emitter at the output end of the optical coupler G1 is connected with a control pulse input end U10-IN of the driving module U10, the control pulse input end U10-IN is connected with a QD-GND (ground level) end through a pull-down resistor R3, and an output end of the optical coupler G1 is connected with a freewheeling diode D1 IN parallel; the working power supply end U10-Vcc of the driving module U10 is connected with a +15V power supply, the input ground end U10-COM of the driving module U10 is connected with a driving ground end QD-GND and is connected with a +15V power supply through a capacitor C1, the upper end of a load FZ is connected with an output stage reference ground end U10-Vs, the output stage reference ground end U10-Vs is connected with an output stage working power supply end U10-VB through a capacitor C2, and the output stage working power supply end U10-VB is connected with a +15V power supply through a diode D2; the two ends of the load FZ are connected in series with a resistor R4 and a capacitor C3.

A duty ratio signal output by a pulse width modulation signal output end CPU-PWM1 of the CPU is limited by a current limiting resistor R1 and then is sent to an input end of an optical coupler G1, when a pull-down resistor R2 ensures that the CPU-PWM1 outputs a logic level '0', the level of the input end of the optical coupler G1 is also logic '0', and a light-emitting diode ensures that the light-emitting diode can be reliably cut off; when the voltage at the control pulse input end U10-IN of the driving module U10 suddenly rises, the freewheeling diode D1 freewheels; the capacitor C1 is used as a voltage stabilizing capacitor, and the capacitor C2 and the diode D2 form a bootstrap circuit to generate VB voltage; the resistor R4 and the capacitor C3 form a tank circuit. After the drive module U10 amplifies the duty ratio signal input by the control pulse input end U10-IN, the same duty ratio is output by the drive pulse output end U10-HO to control the on-off of the IGBT1, the IGBT2 and the IGBTn.

An inductor L1 is connected in series between the emitter of each IGBT and the load FZ, and a capacitor C4 is connected in parallel to both ends of the load FZ. The inductor L1 and the capacitor C4 form an LC filter circuit and a voltage stabilizing circuit, and the stability of the terminal voltage of the load FZ can be improved.

A resistor R5 and a resistor R6 are connected in series between the positive electrode VIN + of the power battery and the CPU-GND, an input voltage detection end is connected between the resistor R5 and the resistor R6, and the input voltage detection end is connected with the PAD1 port of the CPU; a resistor R7 and a resistor R8 are connected in series between the upper end of the load FZ and the CPU-GND, an output voltage detection end is connected between the resistor R7 and the resistor R8, and the output voltage detection end is connected with the PAD2 port of the CPU. The CPU reads the PAD1 value, and through interpolation, the input voltage value can be calculated to judge the power of the power battery. The CPU reads the PAD2 value and through interpolation, calculates the actual output voltage value to determine whether the rated voltage requirement of the load FZ is met.

As shown in fig. 5, a positive electrode VIN + of the power battery, a thermistor RM and a diode D3 are sequentially connected in series and then connected with a positive electrode Vi + of an input voltage of the DC-DC converter, a piezoresistor YM is connected in series between the thermistor RM and a negative electrode VIN-of the power battery and between the thermistor RM and the negative electrode Vi-of the input voltage of the DC-DC converter, and a freewheeling diode D4 and a capacitor C5 are connected in parallel between the positive electrode Vi + of the input voltage of the DC-DC converter and the negative electrode VIN-of the power battery; the output cathode I VO 1-of the DC-DC converter is connected with the CPU-GND, and the output anode I VO1+ of the DC-DC converter provides +5V power supply for the CPU; an output cathode two VO 2-of the DC-DC converter is connected with a driving ground end QD-GND, and an output anode two VO2+ of the DC-DC converter provides a +15V power supply for a driving module U10; the driving ground QD-GND and the negative electrode VIN-of the power battery are connected with each other through an inductor L2.

The power supply voltage for the CPU is +5V, and the power supply voltage for the driving module U10 is + 15V; and a +5V power supply and a +15V power supply are provided by using a low-power finished product DC-DC converter with low power and two-way voltage output. The input VIN-, CPU-GND \ QD-GND of the low-power finished product DC-DC converter are mutually isolated. When the working current of the load FZ is relatively large, the end voltage of the power battery is easily reduced, and the end voltage is unstable. The thermistor RM is a positive temperature coefficient, so that the impact of the terminal voltage of the power battery on the input voltage of the DC-DC converter when the terminal voltage of the power battery is greatly changed can be effectively buffered; the piezoresistor YM can further buffer the impact of the self-induced electromotive force of the load FZ on the DC-DC converter when the IGBT is switched off; after the terminal voltage of the power battery is reduced to be lower than the allowable input voltage of the DC-DC converter, the diode D3 can effectively prevent the current from flowing backwards; the capacitor C5 acts as a voltage regulator to keep the input voltage of the DC-DC converter above the minimum allowable input voltage for a longer period of time. The inductance L2 can reduce the influence of the voltage variation at the VIN-terminal of the power battery on the driving module QD-GND.

A freewheeling diode D5 is connected between an output cathode VO1 & lt- & gt and an output anode VO1 & lt- & gt of the DC-DC converter, an inductor L3 is connected in series between an output anode VO1 & lt + & gt of the DC-DC converter and a CPU & lt + & gt 5V power supply, and a capacitor C6 and a capacitor C7 are connected in parallel between the CPU & lt + & gt 5V power supply and a CPU-GND power supply; a freewheeling diode D6 is connected between the output cathode two VO2 & lt- & gt and the output anode two VO2 & lt- & gt of the DC-DC converter, an inductor L4 is connected in series between the output anode two VO2 & lt + & gt of the DC-DC converter and a driving module +15V power supply, and a capacitor C8 and a capacitor C9 are connected in parallel between the driving module +15V power supply and a driving ground end QD-GND.

The inductor L3, the capacitor C6 and the capacitor C7 form a filter circuit and a voltage stabilizing circuit of the +5V power supply, so that the voltage of the +5V power supply of the CPU can be more stable, and when the voltage of the CPU-GND suddenly rises, the freewheeling diode D5 freewheels. The inductor L4, the capacitor C8 and the capacitor C9 form a filter circuit and a voltage stabilizing circuit of the +15V power supply, so that the voltage of the +15V power supply of the driving module U10 can be more stable, and when the voltage of the driving ground end QD-GND suddenly rises, the freewheeling diode D6 freewheels.

As shown in FIG. 6, a temperature sensor T1 is mounted on the circuit board, a temperature signal output end of the temperature sensor T1 is connected with a PAD0 port of the CPU, a pull-up resistor R9 is connected in series between the PAD0 port and the CPU +5V power supply, a grounding end of the temperature sensor T1 is connected with the CPU-GND, and a capacitor C10 is arranged between the PAD0 port of the CPU and the CPU-GND. T1 of the temperature sensor is a negative temperature coefficient, the resistance value at 100 ℃ is 4.52k omega, and the resistance value at 20 ℃ is 42.16k omega; the CPU reads the PAD0 value, and calculates the temperature value of the circuit board by interpolation, if the temperature of the circuit board is too high, the duty ratio output by the pulse width modulation signal output end CPU-PWM1 of the CPU can be 0/4, and the load FZ stops working.

The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention. In addition to the above embodiments, the present invention may have other embodiments. All technical solutions formed by adopting equivalent substitutions or equivalent transformations fall within the protection scope of the claims of the present invention. Technical features of the present invention which are not described may be implemented by or using the prior art, and will not be described herein.