阅读说明：本技术 处理设备、网络节点、客户端设备及其方法 (Processing device, network node, client device and method thereof ) 是由 王鹏 富兰崛克·伯根 于 2017-06-07 设计创作，主要内容包括：本发明涉及一种处理设备,用于生成待与主同步信号序列一起用于同步的辅同步信号序列,所述处理设备用于：至少基于小区标识确定第一循环移位和第二循环移位,其中,所述第一循环移位和所述第二循环移位中的至少一个与所述主同步信号序列相关联,所述主同步信号序列还基于所述主同步信号序列的索引确定；以及基于被循环移位第一循环移位的第一二进制序列和被循环移位第二循环移位的第二二进制序列的模2求和来生成所述辅同步信号序列,或者基于被循环移位第一循环移位m<Sub>0</Sub>的第一二进制序列和被循环移位第二循环移位m<Sub>1</Sub>的第二二进制序列的相乘来生成辅同步信号SSS序列,使得如果与主同步信号序列相关联的两个生成的辅同步信号序列为彼此的循环移位版本,则所述两个生成的辅同步信号序列为彼此的非连续移位版本。此外,本发明还涉及网络节点、客户端设备、对应方法、计算机程序以及计算机程序产品。(The invention relates to a processing device for generating a secondary synchronization signal sequence to be used for synchronization together with a primary synchronization signal sequence, the processing device being configured to: determining a first cyclic shift and a second cyclic shift based at least on a cell identity, wherein at least one of the first cyclic shift and the second cyclic shift is associated with the primary synchronization signal sequence, the primary synchronization signal sequence further determined based on an index of the primary synchronization signal sequence; and generating the secondary synchronization signal sequence based on a modulo-2 summation of the cyclically shifted first binary sequence and the cyclically shifted second binary sequence, or based on a cyclically shifted second binary sequenceRing shift first cyclic shift m 0 And is cyclically shifted by a second cyclic shift m 1 Generates a secondary synchronization signal SSS sequence such that two generated secondary synchronization signal sequences associated with a primary synchronization signal sequence are non-consecutive shifted versions of each other if the two generated secondary synchronization signal sequences are cyclic shifted versions of each other. Furthermore, the invention relates to a network node, a client device, a corresponding method, a computer program and a computer program product.)

1. A processing device configured to generate a secondary synchronization signal sequence to be used for synchronization with a primary synchronization signal sequence, the processing device configured to:

based at least on cell identity N_IDDetermining a first cyclic shift m₀And a second cyclic shift m₁Wherein the first cyclic shift is m₀And the second cyclic shift m₁Is associated with the primary synchronization signal sequence, the primary synchronization signal sequence being based on an index of the primary synchronization signal sequenceDetermining; and

first cyclic shift m based on being cyclically shifted₀And is cyclically shifted by a second cyclic shift m₁Generates the secondary synchronization signal sequence based on a modulo-2 summation of the second binary sequence of (a) or (b) is cyclically shifted by a first cyclic shift m₀And is cyclically shifted by a second cyclic shift m₁Generates a secondary synchronization signal SSS sequence such that two generated secondary synchronization signal sequences associated with a primary synchronization signal sequence are non-consecutively shifted versions of each other if they are cyclically shifted versions of each other.

2. The processing device (100) according to claim 1, wherein the first and second binary sequences are one of:

m sequence; and

resulting in the generated secondary synchronization signal sequence belonging to an m-sequence of a set of Gold sequences.

3. The processing device (100) according to claims 1 to 2, wherein the plurality of master synchronization signal sequences available for synchronization is one of:

a primary synchronization signal sequence;

two or more primary synchronization signal sequences; and

three primary synchronization signal sequences.

4. The processing device (100) according to any of claims 1 to 3, wherein the generated secondary synchronization signal sequence has a length L of 127; i.e., L127.

5. The processing device (100) according to any of claims 1 to 4, further configured to determine the at least one cell identity N based on one or more of_IDThe associated first cyclic shift m₀And the second cyclic shift m₁：

The first cyclic shift m₀And the second cyclic shift m₁Equal; i.e. m₀＝m₁；

The first cyclic shift m₀And the second cyclic shift m₁Different; i.e. m₀≠m₁；

The first cyclic shift m₀Greater than the second cyclic shift m₁(ii) a I.e. m₀＞m₁；

The first cyclic shift m₀Less than the second cyclic shift m₁(ii) a I.e. m₀＜m₁；

Two cyclic shift pairs (m)₀，m₁) And (m'₀，m′₁) M 'is satisfied'₀＝m₀+1 and m'₁＝m₁At most one of + 1;

two cyclic shift pairs (m)₀，m₁) And (m'₀，m′₁) M 'is satisfied'₀＝m₀+1 and m'₁＝m₁At most one of +1, and the first cyclic shift m₀Greater than the second cyclic shift m₁(ii) a I.e. m₀＞m₁；

Two cyclic shift pairs (m)₀，m₁) And (m'₀，m′₁) M 'is satisfied'₀＝m₀+1 and m'₁＝m₁At most one of +1, and the first cyclic shift m₀Less than the second cyclic shift m₁(ii) a I.e. m₀＜m₁；

All satisfy m'₀＝m₀+1 and m'₁＝m₁+1 two cyclically shifted pairs (m)₀，m₁) And (m'₀，m′₁) With different primary synchronization signal sequence indicesAssociating;

all satisfy m'₀＝m₀+1 and m'₁＝m₁+1 two cyclically shifted pairs (m)₀，m₁) And (m'₀，m′₁) With different primary synchronization signal sequence indicesIs associated with, and the first cyclic shift m₀Greater than the second cyclic shift m₁I.e. m₀＞m₁(ii) a And

all satisfy m'₀＝m₀+1 and m'₁＝m₁+1 two cyclically shifted pairs (m)₀，m₁) And (m'₀，m′₁) With different primary synchronization signal sequence indicesIs associated with, and the first cyclic shift m₀Less than the second cyclic shift m₁I.e. m₀＜m₁。

6. The processing apparatus (100) according to any of claims 1 to 5, further configured to determine the first cycleRing shift m₀And the second cyclic shift m₁Wherein m is₀，m₁Satisfies the following conditions:

wherein the content of the first and second substances,

g is an integer greater than 1;

l' is a positive integer less than or equal to the length L of the secondary synchronization signal sequence;

is an index of the secondary synchronization signal sequence; wherein

Is an index of the primary synchronization signal sequence; wherein

Is a floor function; and

mod is a modulo operation.

7. The processing device (100) according to any of claims 1 to 5, further configured to determine the first cyclic shift m₀And the second cyclic shift m₁Wherein m is₀，m₁Satisfies the following conditions:

wherein the content of the first and second substances,

g is an integer greater than 1;

l' is a positive integer less than or equal to the length L of the secondary synchronization signal sequence;

is an index of the secondary synchronization signal sequence; wherein

Is an index of the Primary Synchronization Signal (PSS) sequence; wherein

Is a floor function; and

mod is a modulo operation.

8. The processing device (100) according to any of claims 1 to 5, further configured to determine the first cyclic shift m₀And the second cyclic shift m₁Wherein m is₀，m₁Satisfies the following conditions:

wherein the content of the first and second substances,

g is an integer equal to or greater than 1;

l' is a positive integer less than or equal to the length L of the secondary synchronization signal sequence;

is an index of the secondary synchronization signal sequence; wherein

Is an index of the primary synchronization signal sequence; wherein

Is a floor function; and

mod is a modulo operation.

9. The processing device (100) according to any of claims 1 to 5, further configured to determine the first cyclic shift m₀And the second cyclic shift m₁Wherein m is₀，m₁Satisfies the following conditions:

wherein the content of the first and second substances,

g is an integer equal to or greater than 1;

l' is a positive integer less than or equal to the length L of the secondary synchronization signal sequence;

is an index of the secondary synchronization signal sequence, wherein

Is an index of the primary synchronization signal sequence; wherein

Is a floor function; and

mod is a modulo operation.

10. A network node (300), characterized by comprising:

processing device (100) according to any of claims 1 to 9, for generating a secondary synchronization signal (sequence; and

a transceiver (302) configured to transmit a synchronization signal based on a primary synchronization signal sequence and the secondary synchronization signal sequence.

11. A client device (500), comprising:

the processing device (100) of any of claims 1 to 9, configured to generate a secondary synchronization signal sequence;

a transceiver (502) for receiving a secondary synchronization signal by using the generated secondary synchronization signal sequence; and

the processing device (100) is further configured to shift m based on the first cycle₀And a second cyclic shift m₁Determining a cell identity N_IDThe first and second cyclic shifts are determined based on a received primary synchronization signal and the received secondary synchronization signal.

12. A method (200) for determining a secondary synchronization signal sequence for synchronization with a primary synchronization signal sequence, the method (200) comprising:

based at least on cell identity N_IDDetermining (202) a first cyclic shift m₀And a second cyclic shift m₁Wherein the first cyclic shift is m₀And the second cyclic shift m₁Is associated with the primary synchronization signal sequence, the primary synchronization signal sequence being based on an index of the primary synchronization signal sequenceDetermining; and

first cyclic shift m based on being cyclically shifted₀And is cyclically shifted by a second cyclic shift m₁Generates (204) the secondary synchronization signal sequence based on a modulo-2 summation of the second binary sequence of (a), or based on a cyclic shift by a first cyclic shift m₀And is cyclically shifted by a second cyclic shift m₁Generates a secondary synchronization signal SSS sequence such that two generated secondary synchronization signal sequences associated with a primary synchronization signal sequence are non-consecutively shifted versions of each other if they are cyclically shifted versions of each other.

13. A method (400) for a network node (300), comprising:

generating (402) a secondary synchronization signal sequence according to claim 12; and

transmitting (404) a synchronization signal based on a primary synchronization signal sequence and the secondary synchronization signal sequence.

14. A method (600) for a client device (500), comprising:

generating (602) a secondary synchronization signal sequence according to claim 12;

receiving (604) a secondary synchronization signal by using the generated secondary synchronization signal sequence; and

based on a first cyclic shift m₀And a second cyclic shift m₁Determining (606) a cell identity N_IDThe first and second cyclic shifts are determined based on a received primary synchronization signal and the received secondary synchronization signal.

15. Computer program with a program code for performing a method according to any of claims 12-14 when the computer program runs on a computer.

16. The processing device (100) of claims 1 and 2, wherein the first and second binary sequences generate a polynomial g based on m-sequences, respectively₀(x)＝x⁷+x⁴+1 and g₁(x)＝x⁷+ x + 1.

17. The processing device (100) of claims 1 and 2, wherein the first binary sequence is based on an m-sequence generator polynomial of g₀(x)＝x⁷+x⁴+1。

Technical Field

The present invention relates to a processing device and to a network node and a client device comprising the processing device. The invention also relates to a corresponding method and a computer program.

Background

Synchronization is the basis of most telecommunication systems, such as those based on Long Term Evolution (LTE) or LTE-Advanced. In order to allow the client device to perform synchronization with the network, there is at least one transmit-receive point (TRP) periodically transmitted synchronization signal in each cell of the network. These synchronization signals are detected by client devices located nearby and used by each client device to identify the appropriate cell as its serving cell. Thus, synchronization allows the client device to acquire the connection to the TRP and track the connection between them for subsequent data communication.

In the LTE cellular system, the synchronization signals include Primary Synchronization Signal (PSS) and Secondary Synchronization Signal (SSS). Both PSS and SSS are transmitted on unique Orthogonal Frequency Division Multiplexing (OFDM) symbols in each period, i.e., every 5 milliseconds (ms). There are 3 PSS and 168 SSS, which are used together to carry 504 cell Identity (ID) N, 3 × 168 ═ 504_ID. The 168 SSS are further scrambled by the PSS sequence index, and the scrambling is used to indicate the first and second half frame timing. Different PSS and SSS sequence pairs carry different cell IDs and are transmitted by TRP in different cells. The client device first obtains rough time-frequency synchronization and indexes carried in the PSS by detecting the PSS in the time domainClient equipment acquires indexes carried in SSS by detecting SSS in frequency domainThen pass throughObtaining a cell identifier N_ID. Specifically, the PSS sequence is constructed based on a length-63 Zadoff Chu (ZC) sequence with three different root indices, by two length-31 m-sequences m with different cyclic shifts₀And m₁The SSS sequences are constructed from the interleaved concatenation of. Based onThe two short m-sequences are further scrambled, i.e., there are 168 SSS sequences associated with each PSS sequence, and the second m-sequence is scrambled based on the cyclic shift of the first m-sequence. By indexingAndand cyclic shift m₀And m₁Unique reversible mapping between cell ID N in SSS sequence_IDAnd (6) coding is carried out.

The third generation partnership project (3 GPP) is currently working on defining New Radio (NR) access technologies. It has been agreed that synchronization in NR uses 3 NR PSS sequences based on pure binary phase-shifting keying (BPSK) modulated m-sequences with 3 different cyclic shifts. In addition, the number of NR SSS after scrambling should be about 1000, i.e. each PSS sequence should correspond to about 333 SSS sequences. Therefore, with these 3 NR PSS, about 3 × 333 ≈ 1000 cell IDs can be provided, which is about twice as many as the number of cell IDs provided in LTE.

Current LTE SSS designs concatenate two short m-sequences, with a high risk of cross-correlation due to the presence of many SSS sequence pairs where one of the two short m-sequences has the same cyclic shift. The high risk of such cross-correlation may lead to a high probability of false cell ID detection, especially during handover procedures.

Disclosure of Invention

It is an object of embodiments of the present invention to provide a solution that alleviates or solves the disadvantages and problems of conventional solutions.

The above and other objects are achieved by the measures provided in the independent claims. Further advantageous embodiments are provided in the dependent claims.

According to a first aspect of the present invention, there is provided a processing device for achieving a fire or other objective, the processing device being configured to generate a secondary synchronization signal to be used for synchronization with a primary synchronization signal sequence, the processing device being configured to:

based at least on cell ID N_IDDetermining a first cyclic shift m₀And a second cyclic shift m₁Wherein the first cyclic shift is m₀And the second cyclic shift m₁Is associated with the primary synchronization signal sequence, the primary synchronization signal sequence being based on an index of the primary synchronization signal sequenceDetermining; and

first cyclic shift m based on cyclic shift₀And cyclically shifts the second cyclic shift m₁Generates the secondary synchronization signal sequence based on a modulo-2 summation of the second binary sequence of (a) or (b) the cyclic shift of the first cyclic shift m₀And cyclically shifts the second cyclic shift m₁Is generated such that if two generated secondary synchronization signal sequences associated with the primary synchronization signal sequence are cyclically shifted versions of each other, the two generated secondary synchronization signal sequences are non-consecutively shifted versions of each other.

Thus, the two secondary synchronization signal sequences associated with the primary synchronization signal sequence are cyclically shifted versions of each other, and should not be successively shifted versions of each other. In other words, the generated first secondary synchronization signal sequence and the generated second secondary synchronization signal sequence are both associated with the same primary synchronization signal sequence, wherein the first secondary synchronization signal sequence may be implemented by cyclically shifting the second generated secondary synchronization signal sequence, and/or the second secondary synchronization signal sequence may be implemented by cyclically shifting the first secondary synchronization signal sequence, this applies when the first and second secondary synchronization signal sequences are non-contiguously shifted versions of each other, that is, the first generated secondary synchronization signal sequence may be implemented by cyclically shifting the second generated secondary synchronization signal sequence by two or more steps, and/or the second generated secondary synchronization signal sequence may be implemented by cyclically shifting the first generated secondary synchronization signal sequence by two or more steps.

The processing device according to the first aspect provides a number of advantages over conventional solutions. An advantage of the processing device is that the secondary synchronization signal SSS sequence is generated in a simple and efficient way to facilitate low complexity and efficient coding of the cell ID.

By generating secondary synchronization signal SSS sequences, low cross-correlation between secondary synchronization signal SSS sequences taking into account frequency offset is provided, thereby improving reliability of secondary synchronization signal SSS sequence detection in client devices and thus reducing cell search time.

Furthermore, by generating and using the secondary synchronization signal SSS sequence, a closed codec mapping function for efficiently and with low complexity acquiring a sequence index from a cell ID or acquiring a cell ID from a sequence index may be made possible. This reduces the complexity of the network node and client device and provides a fast and efficient method for determining the cell ID. At the client device, the descrambled received signal can be efficiently detected, for example, by utilizing a fast Walsh-Hadamard transform (FWHT).

Thus, embodiments described herein enable efficient coding of cell IDs into secondary synchronization SSS sequences, which guarantees low cross-correlation between SSS sequences even at large residual frequency offsets, and simple mapping of cell IDs to first and second cyclic shift values, and vice versa.

In an embodiment of the processing device according to the first aspect, the first and second binary sequences are one of the group:

m sequence; or

Resulting in the generated secondary synchronization signal sequence belonging to an m-sequence of a set of Gold sequences.

This embodiment has the advantage that when the first and second binary sequences used for generating the secondary synchronization signal SSS sequences are m-sequences, especially if they are m-sequences that result in the generated secondary synchronization signal SSS sequences belonging to a set of Gold sequences, a low cross-correlation between the generated SSS sequences is ensured.

In an implementation form of the processing device according to the first aspect, the first and second binary sequences each generate a polynomial g based on an m-sequence₀(x)＝x⁷+x⁴+1 and g₁(x)＝x⁷+ x + 1.

The advantage of this implementation is that it will generate a set of Gold sequences of length L127, where the absolute inner product of any two sequences is 1,2^(n+1)/2-1 ═ 15, or2^(n+1)/2+1 ═ 17. Wherein n-7 is g₀(x) And g₁(x) The highest order of (a).

In an implementation form of the processing device according to the first aspect, the first binary sequence is a generator polynomial g based on an m-sequence₀(x)＝x⁷+x⁴+1。

This implementation has the advantage that the first m-sequence may be a cyclically shifted sequence of the PSS sequence, using the same generator polynomial g₀(x)＝x⁷+x⁴+1. This makes the cross-correlation between the PSS and SSS sequences low.

According to the first aspect, in an embodiment of the processing device, one of the first and second binary sequences used for generating the secondary synchronization signal SSS sequence is the same sequence as the sequence used for generating the one or more primary synchronization signal PSS sequences, e.g. is the same pseudo-random maximum length sequence.

According to the first aspect, in one implementation of the processing device, the plurality of primary synchronization signal sequences available for synchronization is one of:

a primary synchronization signal sequence;

two or more primary synchronization signal sequences; or

Three primary synchronization signal sequences.

One advantage of this embodiment is that the synchronization signal can be flexibly generated for a large number of cell IDs. The use of one primary synchronization signal PSS sequence reduces the complexity of primary synchronization signal detection. Using two or more, e.g., three, primary synchronization signal PSS sequences such that a subset of secondary synchronization signal SSS sequences may be associated with each primary synchronization signal PSS sequence. Accordingly, only a subset of the secondary synchronization signal SSS sequences need to be detected after the primary synchronization signal detection is successful, thereby reducing the complexity of secondary synchronization signal SSS detection. This embodiment is therefore advantageous as it provides a compromise between the detection complexity of the primary and secondary synchronization signals.

According to the first aspect, in an embodiment of the processing device, the length L of the generated secondary synchronization signal sequence is 127; i.e., L127.

One advantage of this embodiment is that the generation of Secondary Synchronization Signals (SSS) may be used for many available and future wireless systems.

In an embodiment of the processing device according to the first aspect, the processing device is further configured to determine the at least one cell ID N from one or more of the group_IDThe associated first cyclic shift m₀And the second cyclic shift m₁：

The first cyclic shift m₀And the second cyclic shift m₁Equal; i.e. m₀＝m₁；

The first cyclic shift m₀And the second cyclic shift m₁Different; i.e. m₀≠m₁；

The first cyclic shift m₀Greater than the second cyclic shift m₁(ii) a I.e. m₀＞m₁；

The first cyclic shift m₀Less than the second cyclic shift m₁(ii) a I.e. m₀＜m₁；

Two cyclic shift pairs (m)₀，m₁) And (m'₀，m′₁) M 'is satisfied'₀＝m₀+1 and m'₁＝m₁At most one of + 1;

two cyclic shift pairs (m)₀，m₁) And (m'₀，m′₁) M 'is satisfied'₀＝m₀+1 and m'₁＝m₁At most one of +1, and the first cyclic shift m₀Greater than the second cyclic shift m₁(ii) a I.e. m₀＞m1；

Two cyclic shift pairs (m)₀，m₁) And (m'₀，m′₁) M 'is satisfied'₀＝m₀+1 and m'₁＝m₁At most one of +1, and the first cyclic shift m₀Less than the second cyclic shift m₁(ii) a I.e. m₀＜m₁；

All satisfy m'₀＝m₀+1 and m'₁＝m₁+1 two cyclically shifted pairs (m)₀，m₁) And (m'₀，m′₁) Associated with different primary synchronization signal sequence indices;

all satisfy m'₀＝m₀+1 and m'₁＝m₁+1 two cyclically shifted pairs (m)₀，m₁) And (m'₀，m′₁) Associated with different primary synchronization signal sequence indices, and the first cyclic shift m₀Greater than the second cyclic shift m₁(ii) a I.e. m₀＞m₁(ii) a And

all satisfy m'₀＝m₀+1 and m'₁＝m₁+1 two cyclically shifted pairs (m)₀，m₁) And (m'₀，m′₁) Associated with different primary synchronization signal sequence indices, and the first cyclic shift m₀Less than the second cyclic shift m₁(ii) a I.e. m₀＜m₁。

One advantage of this embodiment is that the secondary synchronization signal SSS sequence can be generated flexibly, which is robust against large frequency offsets. It is also advantageous since 5ms timing and/or other additional information can be further encoded into the secondary synchronization signal SSS sequence.

In an embodiment of the processing device according to the first aspect, the processing device is further configured to determine the first cyclic shift m₀And the second cyclic shift m₁Wherein m is₀，m₁Satisfies the following conditions:

wherein the content of the first and second substances,

g is an integer greater than 1;

l' is a positive integer less than or equal to the length L of the secondary synchronization signal sequence;

is an index of the secondary synchronization signal sequence; wherein

Is an index of the primary synchronization signal sequence; wherein

Is a floor function; and

mod is a modulo operation.

One advantage of this embodiment is robustness against large frequency offsets. This embodiment may also exploit all cyclic shifts m of the second binary sequence₁For example, by setting L' ═ L, such that for a given total number of cell IDs to be coded into the secondary synchronization signal SSS sequence, the candidate cyclic shift m for the first binary sequence is m₀Kept to a minimum. Detection of the secondary synchronization signal SSS sequence at the client device can thus be achieved with low complexity and is thus also advantageous. In other words, the client device may first descramble the received signal sequence with a minimum number of cyclic shift hypotheses for the first binary sequence, such that after descrambling under the correct cyclic shift hypothesis for the first binary sequence, the remaining received signal sequence is the second binary sequence with some unknown cyclic shift and may be detected by using a low-cost fast Walsh-Hadamard transform FWHT operation.

In an embodiment of the processing device according to the first aspect, the processing device is further configured to determine the first cyclic shift m₀And the second cyclic shift m₁Wherein m is₀，m₁Satisfies the following conditions:

wherein the content of the first and second substances,

g is an integer greater than 1;

l' is a positive integer less than or equal to the length L of the secondary synchronization signal sequence;

is an index of the secondary synchronization signal sequence; wherein

Is an index of the primary synchronization signal sequence; wherein

Is a floor function; and

mod is a modulo operation.

An advantage of this embodiment is that robustness against large frequency offsets can be ensured. This embodiment also allows for low cost detection of secondary synchronization signal SSS sequences at the client device based on descrambling and FWHT operations. Furthermore, this embodiment generates a first cyclic shift m₀And a second cyclic shift m₁All satisfy m₀＜m₁(or m)₀＞m₁). This enables to exchange m simply₀And m₁To further encode 5ms timing and/or other additional information into the secondary synchronization signal SSS sequence. Alternatively, if it is considered useful to subsequently increase the assumed number in the secondary synchronization signal SSS sequence, a future-oriented solution is constituted.

In an embodiment of the processing device according to the first aspect, the processing device is further configured to determine the first cyclic shift m₀And the second cyclic shift m₁Wherein m is₀，m₁Satisfies the following conditions:

wherein the content of the first and second substances,

g is an integer equal to or greater than 1;

l' is a positive integer less than or equal to the length L of the secondary synchronization signal sequence;

is an index of the secondary synchronization signal sequence; wherein

Is an index of the primary synchronization signal sequence; wherein

Is a floor function; and

mod is a modulo operation.

An advantage of this embodiment is that robustness against large frequency offsets can be ensured. This embodiment also allows for low cost detection of secondary synchronization signal SSS sequences at the client device based on descrambling and FWHT operations. Further, when g ═ 1, this embodiment allows selection of all satisfying m'₀＝m₀+1 and m'₁＝m₁+1 two cyclically shifted pairs (m)₀，m₁) And (m'₀，m′₁) But will associate a corresponding pair of two secondary synchronization signal SSS sequences with different primary synchronization signal PSS sequence indices. Thus, the cyclic shift pair (m)₀，m₁) May be selected, which may beEnabling a greater number of cell IDs to be encoded into the secondary synchronization signal SSS sequence without increasing the SSS sequence length.

In an embodiment of the processing device according to the first aspect, the processing device is further configured to determine the first cyclic shift m₀And the second cyclic shift m₁Wherein m is₀，m₁Satisfies the following conditions:

wherein the content of the first and second substances,

g is an integer equal to or greater than 1;

l' is a positive integer less than or equal to the length L of the secondary synchronization signal sequence;

is an index of the secondary synchronization signal sequence; wherein

Is an index of the primary synchronization signal sequence; wherein

Is a floor function; and

mod is a modulo operation.

An advantage of this embodiment is that robustness against large frequency offsets can be ensured. This embodiment also allows for operation in descrambling and FWHT basedDetecting a secondary synchronization signal SSS sequence at a client device at low cost. Further, when g ═ 1, this embodiment allows selection of all satisfying m'₀＝m₀+1 and m'₁＝m₁+1 two cyclically shifted pairs (m)₀，m₁) And (m'₀，m′₁) But will associate a corresponding pair of two secondary synchronization signal SSS sequences with different primary synchronization signal PSS sequence indices. Thus, the cyclic shift pair (m)₀，m₁) May be selected, which may enable a greater number of cell IDs to be encoded into the secondary synchronization signal SSS sequence without increasing the length of the SSS sequence. Furthermore, this embodiment generates a first cyclic shift m₀And a second cyclic shift m₁All satisfy m₀＜m₁(or m)₀＞m₁). This enables to exchange m simply₀And m₁To further encode 5ms timing and/or other additional information into the secondary synchronization signal SSS sequence. Alternatively, if it is considered useful to subsequently increase the assumed number in the secondary synchronization signal SSS sequence, a future-oriented solution is constituted.

According to a second aspect of the present invention, the above or other objects are achieved by a network node comprising:

a processing device configured to generate a secondary synchronization signal sequence according to the first aspect or any implementation of the first aspect; and

a transceiver for transmitting a synchronization signal based on a primary synchronization signal sequence and the secondary synchronization signal sequence.

The network node according to the second aspect provides a number of advantages over conventional solutions. The network node has the advantage that it is able to generate a secondary synchronization signal SSS sequence in a simple and efficient way.

According to a third aspect of the present invention, the above and other objects are fulfilled by a client device comprising:

a processing device for shifting m based on the first cycle₀And a second cyclic shift m₁Determining cell ID N_IDThe first and second cyclic shifts are determined based on a received primary synchronization signal and the received secondary synchronization signal;

a transceiver for receiving a secondary synchronization signal by using the secondary synchronization signal sequence.

The processing device is further configured to generate a secondary synchronization signal according to the first aspect or any implementation of the first aspect.

The client device according to the third aspect provides a number of advantages over conventional solutions. The client device has the advantages that: m can be shifted from the first cycle in a simple and efficient way₀And a second cyclic shift m₁Medium decoding cell ID N_IDThe first and second cyclic shifts are determined from a detected Secondary Synchronization Signal (SSS) sequence. The secondary synchronization signal SSS sequence can be detected in a low-complexity mode, and can be generated in a simple and effective method.

According to a fourth aspect of the present invention, the above or other objects are achieved by a method for determining a secondary synchronization signal sequence to be used for synchronization with a primary synchronization signal sequence, comprising:

based at least on cell ID N_IDDetermining a first cyclic shift m₀And a second cyclic shift m₁Wherein the first cyclic shift is m₀And the second cyclic shift m₁Is associated with the primary synchronization signal sequence, the primary synchronization signal sequence being further based on an index of the primary synchronization signal sequenceDetermining; and

first cyclic shift m based on cyclic shift₀And cyclically shifts the second cyclic shift m₁Generates the secondary synchronization signal sequence based on a modulo-2 summation of the second binary sequence of (a) or (b) a cyclic shift of (a) a first cyclic shift m₀And cyclically shifts the second cyclic shift m₁Second binary order ofThe column multiplication generates the secondary synchronization signal sequences such that if two secondary synchronization signal sequences associated with the primary synchronization signal sequence are cyclically shifted versions of each other, the two secondary synchronization signal sequences are non-consecutively shifted versions of each other.

The method of the fourth aspect, in one embodiment, the first and second binary sequences are one of:

m sequence; and

so that the generated secondary synchronization signal sequence belongs to an m-sequence of a set of Gold sequences.

In an implementation form of the processing device according to the fourth aspect, the first and second binary sequences each generate a polynomial g based on an m-sequence₀(x)＝x⁷+x⁴+1 and g₁(x)＝x⁷+ x + 1.

In an implementation form of the processing device according to the fourth aspect, the first binary sequence is a generator polynomial g based on an m-sequence₀(x)＝x⁷+x⁴+1. According to the fourth aspect, in one embodiment of the method, the plurality of primary synchronization signal sequences available for synchronization is one of:

a primary synchronization signal sequence;

two or more primary synchronization signal sequences; and

three primary synchronization signal sequences.

According to the fourth aspect, in one embodiment of the method, the length L of the secondary synchronization signal sequence is 127; i.e., L127.

According to the fourth aspect, in one embodiment of the method, the method further comprises: determining a cell ID N with at least one cell according to one or more of_IDThe associated first cyclic shift m₀And the second cyclic shift m₁：

The first cyclic shift m₀And the second cyclic shift m₁Equal; i.e. m₀＝m₁；

The first cyclic shiftm₀And the second cyclic shift m₁Different; i.e. m₀≠m₁；

The first cyclic shift m₀Greater than the second cyclic shift m₁(ii) a I.e. m₀＞m₁；

The first cyclic shift m₀Less than the second cyclic shift m₁(ii) a I.e. m₀＜m₁；

Two cyclic shift pairs (m)₀，m₁) And (m'₀，m′₁) M 'is satisfied'₀＝m₀+1 and m'₁＝m₁At most one of + 1;

two cyclic shift pairs (m)₀，m₁) And (m'₀，m′₁) M 'is satisfied'₀＝m₀+1 and m'₁＝m₁At most one of +1, and the first cyclic shift m₀Greater than the second cyclic shift m₁(ii) a I.e. m₀＞m₁；

Two cyclic shift pairs (m)₀，m₁) And (m'₀，m′₁) M 'is satisfied'₀＝m₀+1 and m'₁＝m₁At most one of +1, and the first cyclic shift m₀Less than the second cyclic shift m₁(ii) a I.e. m₀＜m₁；

All satisfy m'₀＝m₀+1 and m'₁＝m₁+1 two cyclically shifted pairs (m)₀，m₁) And (m'₀，m′₁) Associated with different primary synchronization signal sequence indices;

all satisfy m'₀＝m₀+1 and m'₁＝m₁+1 two cyclically shifted pairs (m)₀，m₁) And (m'₀，m′₁) Associated with different primary synchronization signal sequence indices, and the first cyclic shift m₀Greater than the second cyclic shift m₁(ii) a I.e. m₀＞m₁(ii) a And

all satisfy m'₀＝m₀+1 and m'₁＝m₁+1 two cyclically shifted pairs (m)₀，m₁) And (m'₀，m′₁) Associated with different primary synchronization signal sequence indices, and the first cyclic shift m₀Less than the second cyclic shift m₁(ii) a I.e. m₀＜m₁。

According to the fourth aspect, in one embodiment of the method, the method further comprises determining the first cyclic shift m₀And the second cyclic shift m₁Wherein m is₀，m₁Satisfies the following conditions:

wherein the content of the first and second substances,

g is an integer greater than 1;

l' is a positive integer less than or equal to the length L of the secondary synchronization signal sequence;

is an index of the secondary synchronization signal sequence; wherein

Is an index of the primary synchronization signal sequence; wherein

Is a floor function; and

mod is a modulo operation.

According to the fourth aspect, in one embodiment of the method, the method further comprises determining the first cyclic shift m₀And the second cyclic shift m₁Wherein m is₀，m₁Satisfies the following conditions:

wherein the content of the first and second substances,

g is an integer greater than 1;

l' is a positive integer less than or equal to the length L of the secondary synchronization signal sequence;

is an index of the secondary synchronization signal sequence; wherein

Is an index of the primary synchronization signal sequence; wherein

Is a floor function; and

mod is a modulo operation.

According to the fourth aspect, in one embodiment of the method, the method further comprises determining the first cyclic shift m₀And the second cyclic shift m₁Wherein m is₀，m₁Satisfies the following conditions:

wherein the content of the first and second substances,

g is an integer equal to or greater than 1;

l' is a positive integer less than or equal to the length L of the secondary synchronization signal sequence;

is an index of the secondary synchronization signal sequence; wherein

Is an index of the primary synchronization signal sequence; wherein

Is a floor function; and

mod is a modulo operation.

According to the fourth aspect, in one embodiment of the method, the method further comprises determining the first cyclic shift m₀And the second cyclic shift m₁Wherein m is₀，m₁Satisfies the following conditions:

wherein the content of the first and second substances,

g is an integer equal to or greater than 1;

l' is a positive integer less than or equal to the length L of the secondary synchronization signal sequence;

is an index of the secondary synchronization signal sequence; wherein

Is an index of the primary synchronization signal sequence; wherein

Is a floor function; and

mod is a modulo operation.

The advantages of which method of the fourth aspect may refer to the advantages of the respective processing apparatus claims of the first aspect.

According to a fifth aspect of the present invention, the above or other objects are achieved by a method for a network node, the method comprising:

generating a secondary synchronization signal sequence according to the method of the fourth aspect; and

transmitting a synchronization signal based on a primary synchronization signal sequence and the secondary synchronization signal sequence.

The advantages of the method of the fifth aspect may refer to the advantages of the respective network node claims of the second aspect.

According to a sixth aspect of the present invention, the above and other objects are achieved by a method for a client device, comprising:

receiving an auxiliary synchronization signal; and

based on a first cyclic shift m₀And a second cyclic shift m₁Determining cell ID N_IDThe first and second cyclic shifts are determined based on a received primary synchronization signal and the received secondary synchronization signal.

Optionally, the method may further include generating a secondary synchronization signal sequence according to the method of the fourth aspect, and receiving a secondary synchronization signal using the generated secondary synchronization signal sequence.

The advantages of the method of the sixth aspect may be found in the advantages of the corresponding client device claims of the third aspect.

The invention also relates to a computer program, characterized by code means, which when run by processing means causes said processing means to execute the method according to any aspect of the invention. Furthermore, the invention relates to a computer program product comprising a computer readable medium and a computer program as described above, wherein the computer program is contained in the computer readable medium and comprises one or more of the following group of means: Read-Only Memory (ROM), Programmable ROM (PROM), Erasable PROM (EPROM), flash Memory, Electrically Erasable EPROM (EEPROM), and hard disk drives.

Other applications and advantages of the present invention will become apparent from the following detailed description.

Drawings

The accompanying drawings are included to illustrate and explain various embodiments of the present invention, in which:

figure 1 shows a processing device according to an embodiment of the invention;

figure 2 shows a method for processing a device according to an embodiment of the invention;

figure 3 shows a network node according to an embodiment of the invention;

figure 4 shows a method for a network node according to an embodiment of the invention;

figure 5 shows a client device according to an embodiment of the invention;

FIG. 6 shows a method for a client device according to an embodiment of the invention;

figure 7 shows a wireless system according to an embodiment of the invention;

figure 8 shows a diagram of determining a cyclic shift according to an embodiment of the invention;

fig. 9 shows another diagram of determining a cyclic shift according to an embodiment of the invention;

fig. 10 shows another diagram of determining a cyclic shift according to an embodiment of the invention;

fig. 11 shows another diagram of determining a cyclic shift according to an embodiment of the invention;

figure 12 shows another diagram of determining a cyclic shift according to an embodiment of the invention;

fig. 13 shows another diagram of determining a cyclic shift according to an embodiment of the invention.

Detailed Description

Fig. 1 shows a processing apparatus 100 according to an embodiment of the invention. The processing device 100 includes a processor 102 coupled to a memory 104. The processor 102 and the memory 104 are coupled to each other by a communication device 106 as is known in the art. In one embodiment, the processor 102 may be a dedicated processor for performing secondary synchronization signal SSS sequence generation in accordance with the present invention. In some embodiments, processor 102 is a processor in a network node or client device, and may have other additional functionality.

Processing device 100 for generating a secondary synchronization signal SSS sequence to be used for synchronization with a primary synchronization signal PSS sequence is configured, e.g., by processor 102, based at least on cell ID N_IDDetermining a first cyclic shift m₀And a second cyclic shift m₁Wherein the first cyclic shift is m₀And a second cyclic shift m₁Is associated with a primary synchronization signal PSS sequence based on its indexAnd (4) determining.

The processing device 100 is further configured to, e.g., by the processor 102, perform a first cyclic shift m based on being cyclically shifted₀And is cyclically shifted by a second cyclic shift m₁Generates a secondary synchronization signal SSS sequence based on a modulo-2 summation of the second binary sequence of (a) or (b) is cyclically shifted by a first cyclic shift m₀And is cyclically shifted by a second cyclic shift m₁Generates a secondary synchronization signal SSS sequence such that two generated secondary synchronization signal SSS sequences associated with a primary synchronization signal PSS sequence are non-consecutive shifted versions of each other if the two generated secondary synchronization signal SSS sequences are cyclic shifted versions of each other.

Fig. 2 shows a flow chart of a corresponding method 200 that may be performed in the processing device 100 as shown in fig. 1.

The method 200 comprises a first step 202 of basing at least on a cell ID N_IDDetermining a first cyclic shift m₀And a second cyclic shift m₁Wherein the first cyclic shift is m₀And the second cyclic shift m₁Is associated with a primary synchronization signal sequence that is also based on an index of the primary synchronization signal sequenceAnd (4) determining.

The method further comprises a second step 204 of cyclically shifting by a first cyclic shift m based on being cyclically shifted₀And is cyclically shifted by a second cyclic shift m₁Generates a secondary synchronization signal SSS sequence based on a modulo-2 summation of the second binary sequence of (a) or (b) is cyclically shifted by a first cyclic shift m₀And is cyclically shifted by a second cyclic shift m₁Generates a secondary synchronization signal SSS sequence such that two generated secondary synchronization signal SSS sequences associated with a primary synchronization signal PSS sequence are non-consecutive shifted versions of each other if the two generated secondary synchronization signal SSS sequences are cyclic shifted versions of each other.

Fig. 3 shows a network node 300 according to an embodiment of the invention. In the embodiment shown in fig. 3, the network node 300 comprises a processing device 100, a transceiver 302 and a memory 304. The processing device 100 is coupled to a transceiver 302 and a memory 304 by communication means 306 as is known in the art. The network node 300 further comprises an antenna 308 coupled to the transceiver 302, which means that the network node 300 is used for wireless communication in a wireless communication system.

The processing device 100 of the network node 300 is configured to generate a secondary synchronization signal SSS sequence according to any of the embodiments of the method 200 described herein. The transceiver 302 of the network node 300 is configured to transmit synchronization signals based on a primary synchronization signal PSS sequence and a secondary synchronization signal SSS sequence.

Fig. 4 shows a flow chart of a corresponding method 400 that may be performed in a network node 300, such as the network node 300 shown in fig. 3. The method 400 comprises a first step 402 of generating a secondary synchronization signal, SSS, sequence according to any of the embodiments of the method 200 described herein. The method further comprises a second step 404 of transmitting a synchronization signal based on a primary synchronization signal PSS sequence and a secondary synchronization signal SSS sequence.

Fig. 5 shows a client device according to an embodiment of the invention. In the embodiment shown in fig. 5, client device 500 includes processing device 100, transceiver 502, and memory 504. The processing device 100 is coupled to the transceiver 502 and the memory 504 by communication means 506 as is known in the art. Client device 500 also includes an antenna 508 coupled to transceiver 502, meaning that client device 500 is used for wireless communications in a wireless communication system.

The processing device 100 of the client device 500 is configured to generate a secondary synchronization signal SSS sequence according to any of the embodiments described herein. The transceiver 502 of the client device 500 is configured to receive a secondary synchronization signal SSS. For example, the secondary synchronization signal SSS is received with the generated secondary synchronization signal SSS sequence. The processing device 100 is further configured to shift m based on the first cycle₀And a second cyclic shift m₁Determining cell ID N_IDThe first cyclic shift m₀And the second cyclic shift m₁Based on received primary synchronization signal PSS and receivedSecondary synchronization signal SSS determination.

Fig. 6 illustrates a flow chart of a corresponding method 600 that may be performed in a client device 500, such as the client device 500 illustrated in fig. 5. The method 600 comprises a first step 602 of generating a secondary synchronization signal, SSS, sequence according to any of the embodiments of the method 200 described herein. The method further comprises a second step 604 of receiving a secondary synchronization signal SSS using the generated secondary synchronization signal SSS sequence. The method further comprises a third step 606 of shifting m based on the first cycle₀And a second cyclic shift m₁Determining cell ID N_IDThe first and second cyclic shifts are determined based on a received primary synchronization signal PSS and a received secondary synchronization signal SSS.

Fig. 7 illustrates a wireless communication system 700 according to an embodiment. The wireless communication system 700 comprises a network node 300 and a client device 500 for operating in the wireless communication system 700. Network node 300 and client device 500 may each comprise processing device 100. In the wireless communication system 700, the synchronization signal is transmitted by the network node 300 and received by the client device 500. Based on the synchronization signal, the client device 500 performs synchronization with the network node 300 and acquires the cell ID of the network node 300 as described in this document. The synchronization signals include a primary synchronization signal PSS and a secondary synchronization signal SSS. The processing device 100 in the network node 300 generates a secondary synchronization signal SSS sequence. The client device 500 receives the synchronization signal. The processing device 100 of the client device 500 may also generate a sequence of secondary synchronization signals SSS for performing relevant operations or the like in the client device 500, as described in this document.

For simplicity, the wireless communication system 700 is only shown in fig. 7 as comprising one network node 300 and one client device 500. However, the wireless communication system 700 may include any number of network nodes 300 and any number of client devices 500 without departing from the scope of the present invention.

The network node 300 herein may also be denoted as a Radio network node, an access point or a Base Station, e.g. a Radio Base Station (RBS), and in some networks may be referred to as a transmitter, "gNB", "eNB", "eNodeB", "NodeB" or "B node", depending on the technology and terminology used. The radio network nodes may be of different classes, e.g. macro base station eNodeB, home base station eNodeB or pico base station, based on the transmission power and its cell size. A radio network node may be a Station (STA) which is any device that includes IEEE 802.11 compliant Media Access Control (MAC) and Physical Layer (PHY) interfaces to the Wireless Medium (WM). The network node 300 may also be a base station corresponding to a fifth generation wireless system.

The client device 500 may be a User Equipment (UE), a mobile station, an internet of things (IoT) device, a sensor device, a wireless terminal and/or a mobile terminal, and is capable of performing wireless communication in a wireless communication system, which is sometimes referred to as a cellular wireless system. The UE may also be a mobile phone, a cellular phone, a tablet, or a laptop with wireless capabilities. A UE herein may be a portable, storable, handheld, computer-comprised, or vehicle-mounted mobile device or the like capable of voice and/or data communication with another entity, such as another receiver or server, via a radio access network. The UE may be a Station (STA), which is any IEEE 802.11 compliant device that includes a Media Access Control (MAC) and Physical Layer (PHY) interface to the Wireless Medium (WM). Client device 500 may also be used to communicate in fifth generation wireless technologies related to 3GPP, such as LTE and LTE-Advanced, WiMAX and its evolution, and new wireless.

Furthermore, any method according to embodiments of the present invention may be implemented in a computer program having code means which when run by processing means causes the processing means to perform the steps of the method. The computer program is embodied in a computer-readable medium of a computer program product. The computer-readable medium may include substantially any Memory, such as Read-Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable PROM (EPROM), flash Memory, Electrically Erasable PROM (EEPROM), or a hard drive.

Furthermore, the skilled person realizes that the processing device 100, the network node 300 and the client device 500 of embodiments of the present invention comprise the necessary communication capabilities, e.g. in the form of functions, means, units, elements, etc. to carry out the present solution. Examples of other such means, units and functions are: processors, memories, buffers, control logic, encoders, decoders, rate matchers, speed down matchers, mapping units, multipliers, decision units, selection units, switches, interleavers, deinterleavers, modulators, demodulators, inputs, outputs, antennas, amplifiers, receiving units, transmitting units, DSPs, MSDs, TCM encoders, TCM decoders, power supply units, power feeders, communication interfaces, communication protocols, etc., suitably arranged together to implement the present solution.

In particular, the processors of the devices and nodes of the present invention may include, for example, one or more instances of a Central Processing Unit (CPU), a Processing Unit, Processing circuitry, a processor, an Application Specific Integrated Circuit (ASIC), a microprocessor, or other Processing logic that may compile and execute instructions. The term "processor" may thus refer to a processing circuit that includes a plurality of processing circuits, any, some, or all of the items listed above. The processing circuitry may further perform data processing functions to input, output, and process data, including data buffering and device control functions, such as call processing control, user interface control, and the like.

According to an embodiment, the first and second binary sequences used for generating the secondary synchronization signal SSS sequence are pseudo-random maximal length sequences, i.e. m-sequences.

According to an embodiment, the first and second binary sequences used for generating the secondary synchronization signal SSS sequence are pseudo-random maximal length sequences, i.e. m-sequences, which may be m-sequences based on a set of Gold sequences, thereby ensuring low cross-correlation between the generated SSS sequences. Gold sequences are described in more detail below.

According to an embodiment, one of the first and second binary sequences used for generating the secondary synchronization signal SSS sequence is the same as the binary sequence used for generating the one or more primary synchronization signal PSS sequences, e.g. the same pseudo-random maximum length sequence.

As described below, according to various embodiments, different numbers of primary synchronization signal PSS sequences may be used for synchronization signals, e.g. one primary synchronization signal PSS sequence, two or more primary synchronization signal PSS sequences, such as three primary synchronization signal PSS sequences. Thus, the secondary synchronization signal SSS sequences described herein may be generated for use with different numbers of primary synchronization signal PSS sequences, such that flexible synchronization signal generation may be provided to accommodate a large number of cell IDs and/or wireless systems.

According to an embodiment, as shown below, the length L of the generated secondary synchronization signal SSS sequence is 127, i.e., L127, which is applicable to some available wireless systems and future wireless systems, such that the embodiments described herein may be implemented in these systems.

The invention discloses SSS sequences d (k), k 0, 1,2, L-1, which may be based on having different cyclic shifts m₀And m₁Is constructed as a modulo-2 sum of two binary sequences of length L. According to an embodiment, BPSK modulation is used. For example, d (k) of an SSS sequence may be represented as follows:

d(k)＝1-2((s₀((k+m₀)modL)+s₁((k+m₁) modL)) mod2), k 0, 1,2,., L-1 (equation 1)

Those skilled in the art will appreciate that an equivalent representation of d (k) can be obtained by first modulating (e.g., BPSK modulation) and then multiplying the constituent modulated sequences;

y₀(k)＝1-2s₀(k)

y₁(k)＝1-2s₁(k)

d(k)＝y₀(k+m₀modL)·y₁(k+m₁modL)，k＝0，1，2，...，L-1

alternatively, the first and second electrodes may be,

y₀(k)＝1-2s₀(k+m₀modL)

y₁(k)＝1-2s₁(k+m₁modL)

d(k)＝y₀(k)·y₁(k)＝(1-2s₀(k+m₀modL))·(1-2s₁(k+m₁modL))，k＝0，1，2，...，L-1

the above examples are not exhaustive and those skilled in the art will appreciate that the sequences d (k) may be equivalently represented in other various forms. In its most general form, the present application discloses a cyclically shifted first cyclic shift m₀And is cyclically shifted by a second cyclic shift m₁To generate a secondary synchronization signal SSS sequence.

In this example, the SSS sequence d (k) may be based on two sequences S of length L₀(k),S₁(k) Is generated in which S₀(k) Is cyclically shifted by a first cyclic shift m₀That is, S₀(k) With a first cyclic shift m₀。S₁(k) Is cyclically shifted by a second cyclic shift m₁. That is to say S₁(k) With a second cyclic shift m₁。

The two binary sequences, for example, may be two m-sequences of the same length L selected by a carefully selected generator polynomial, such that all generated SSS sequences belong to the same set of Gold sequences, thereby ensuring low cross-correlation between the generated SSS sequences.

For example, the generator polynomials may be individually selected as g₀(x)＝x⁷+x⁴+1 and g₁(x)＝x⁷+ x + 1. This produces a set of Gold sequences of length L127, where the absolute inner product of any two sequences is 1,2^(n+1)/2-1 ═ 15 or2^(n+1)/2+ 1-17, n-7 is g₀(x) And g₁(x) The highest order of (a).

In one implementation, the processing device 100 as in claims 1 and 2 wherein the first and second binary sequences generate the polynomial g based on m-sequences, respectively₀(x)＝x⁷+x⁴+1 and g₁(x)＝x⁷+ x + 1.

In another implementation, the processing device 100 as in claims 1 and 2, the first binary sequence being g based on an m-sequence generator polynomial₀(x)＝x⁷+x⁴+1。

According to an embodiment, one of the first and second binary sequences used for generating the secondary synchronization signal SSS sequence may be selected to be the same sequence as the binary sequence used for generating the primary synchronization signal PSS sequence, e.g. the same pseudo-random maximum length sequence. Thus, the same binary sequence, e.g., the same m-sequence, is selected for generating the primary synchronization signal PSS sequence and the first binary sequence, or the second binary sequence, for generating the secondary synchronization signal SSS sequence. Those skilled in the art will appreciate that the meaning of the same binary sequence includes using the same common sequence for the PSS sequence and one of the first and second binary SSS sequences, but with different cyclic shifts. For example, to obtain a common m-sequence, the PSS sequence and one of the first and second binary SSS sequences use the same generator polynomial. For example, both the generated primary synchronization signal PSS sequence and the generated secondary synchronization signal SSS sequence may thus belong to the same set of Gold sequences, so that a low cross-correlation between the generated secondary synchronization signal SSS sequence and the generated primary synchronization signal PSS sequence is also ensured.

Cell ID, i.e. N_IDSatisfies the following conditions:wherein the cell ID is carried by the sequence index of SSS and PSS, whereinAndthe cell ID is encoded into the first cyclic shift m of two binary sequences, e.g., two m sequences₀And a second cyclic shift m₁Such that if there are multiple PSSs, the first cyclic shift is m₀And a second cyclic shift m₁Depends on the PSS sequence index. Furthermore, if the generated SSS sequences are associated with the same PSS sequence index, it is guaranteed that these SSS sequences have low cross-correlation even at large residual frequency offset, since one SSS sequence cannot be obtained by cyclically shifting another SSS sequence associated with the same PSS index by one step.

According to an embodiment, m 'are not satisfied simultaneously'₀＝m₀+1 and m'₁＝m₁+1 two determined cyclic shift pairs (m)₀，m₁) And (m'₀，m′₁). In other words, this may be expressed as any two SSS cyclic shift pairs (m)₀，m₁) And (m'₀，m′₁) Can only satisfy m'₀＝m₀+1 and m'₁＝m₁At most one of + 1. Accordingly, the robustness advantage against large frequency offsets is ensured. According to the present embodiment, e.g. by indexing the sequences carried in the PSS, i.e.Design of cyclic shift pairs by coding the cyclic shift as one of two binary sequences, e.g. for a first cyclic shift m₀And requires a first cyclic shift m₀Are spaced from each other by more than one (1) cyclic shift step. Thus, consecutive cyclic shifts of the first binary sequence may not be selected simultaneously, which also means that non-consecutive cyclic shifts of the first binary sequence may be selected. At this time, the first cyclic shift m₀May be kept to a minimum, such that SSS detection based on low complexity/low cost scrambling-FWHT may be utilized in the client device 500.

The sequence carried by the SSS can be indexed, i.e.First cyclic shift m encoded as first and second binary sequences₀And a second cyclic shift m₁Wherein a second cyclic shift m is allowed₁Including all or most of its significant values 0, 1, 2. This SSS design avoids the situation where one SSS sequence can be obtained by cyclically shifting another SSS sequence by one cyclic shift step, thus ensuring robustness against large frequency offsets.

It should be noted that the index of the PSS sequence is usedEncoding to a first cyclic shift m₀And indexing of SSS sequencesEncoding to a first cyclic shift m₀And a second cyclic shift m₁Can be done in any way, e.g. m₀And m₁May be exchanged or substituted in the equations below. Given a first cyclic shift m₀Of (d), then for the first cyclic shift m₀By a different value of, a second cyclic shift of m₁May be the same or different.

According to an embodiment of the present embodiment, the index of the SSS sequence has been changedAnd the index of the PSS sequenceEncoding to a first cyclic shift m₀And a second cyclic shift m₁I.e. shift the first cycle by m₀And a second cyclic shift m₁The determination is as follows:

where g is the first cyclic shift m₀Is smallest cyclic shift step between the candidate values ofLong, which is an integer greater than 1. L 'is a positive integer less than or equal to the length L of the SSS sequence, i.e. L' ≦ L; for a given first cyclic shift m₀Which is also the second cyclic shift m₁Is determined by the maximum number of candidates. Here, and in this document,representing a rounding down function and mod a modulo operation. Since g > 1, any two SSS sequences (m)₀，m₁) And (m'₀，m′₁) Can only satisfy m 'in cyclic shift'₀＝m₀+1 and m'₁＝m₁At most one of + 1.

As a non-limiting example, it is to be mentioned that for a new wireless synchronization signal implementation, where L is 127 andfor example, setting g to 2,And L' 112, a total of 336 × 3-1008 cell IDs may be implemented.

To is directed atFig. 8 shows a schematic and non-limiting illustration of an example of this embodiment, L15, g 2 and L' 8. M 'is not satisfied all the time since g is 2'₀＝m₀+1 and m'₁＝m₁+1 two cyclically shifted pairs (m)₀，m₁) And (m'₀，m′₁). This is illustrated in fig. 8, where every second position in the diagonal direction is not used, i.e. the positions that can be selected (black dots) are separated in the diagonal direction by positions that may not be selected (white dots). In this document, the diagonal direction with respect to the drawing includes satisfying m₀＝m₁+ c, where c is any integer. Therefore, m 'is not satisfied at the same time in the diagram of FIG. 8'₀＝m₀+1 and m'₁＝m₁+1. In FIG. 8, PSS sequence indexIs the y-axis, where m₀0 and m₀All have the same PSS sequence index 2I.e. m₀0 and m₀2 are all indexed with the same PSS sequenceAnd (4) associating. Accordingly, m₀4 and m₀6 are all indexed with the same PSS sequenceAnd (4) associating. It should be noted that the PSS sequence indexAnd a first cyclic shift m₀And SSS indexAnd m₀And m₁The association of (c) is not limited to the order shown in fig. 8. Rather, any other order is possible.

In addition, according to an embodiment, m may be shifted based on the first cycle₀And a second cyclic shift m₁To determine cell ID N_ID. Because there is a shift value m from the first cycle₀And a second cyclic shift value m₁To PSS sequence indexingAnd SSS sequence indexSo this is possible, for example, by satisfying:

shifting m based on the first cycle in a simplified manner₀And a second cyclic shift m₁Determining PSS sequence indexAnd SSS sequence indexMitigating implementation of large tables in client devices to shift m based on first cycle₀And a second cyclic shift m₁The need for a cell ID is determined.

According to an embodiment, all are not satisfied with m'₀＝m₀+1 and m'₁＝m₁+1 two determined cyclic shift pairs (m)₀，m₁) And (m'₀，m′₁) I.e. two cyclic shift pairs (m)₀，m₁) And (m'₀，m′₁) Can only satisfy m'₀＝m₀+1 and m'₁＝m₁At most one of +1, while the determined cyclic shift pair always satisfies m₀＜m₁(or m)₀＞m₁). Accordingly, the robustness advantage against large frequency offsets is ensured.

According to the implementation of this embodiment, the sequence carried in the PSS has been indexedAnd sequence index carried in SSSEncoding to a first cyclic shift m₀And a second cyclic shift m₁The first cyclic shift m₀And a second cyclic shift m₁Satisfies the following conditions:

wherein g > 1 is the first cyclic shift m₀Is given, and L' ≦ L is the given first cyclic shift m₀Second cyclic shift m₁Is determined by the maximum number of candidates. Since g > 1, for any two SSS sequence cyclic shift pairs, e.g. (m)₀，m₁) And (m'₀，m′₁) M 'is satisfied'₀＝m₀+1 and m'₁＝m₁At most one of + 1. Furthermore, the generated cyclic shift pair always satisfies m₀＜m₁(or m)₀＞m₁). This is advantageous if the SSS is transmitted twice every 10ms, i.e. once in each field, since it allows m to be simply exchanged between two fields₀And m₁To indicate 5ms timing using SSS sequences (e.g., done in LTE). Alternatively, if later thought helpful in increasing the number of assumptions in the SSS, embodiments provide a future-oriented solution, e.g., for future new wireless release systems.

As a non-limiting example, it is to be mentioned that for a new wireless synchronization signal implementation, where L is 127 andone possible implementation, for example, sets g 2,And L' 115, etc. to carry 336 x 3 1008 cell identities.

Fig. 9 shows a non-limiting example illustration of this embodiment. To be provided withIn fig. 9, the PSS sequence index is illustrated by L ═ 15, g ═ 2, and L ═ 8 as examplesIs the y-axis, where m₀0 and m₀All have the same PSS sequence index 2I.e. m₀0 and m₀2 are all indexed with the same PSS sequenceAnd (4) associating. Accordingly, m₀4 and m₀6 are all indexed with the same PSS sequenceAnd (4) associating. It should be noted that the PSS sequence indexAnd a first cyclic shift m₀And SSS indexAnd a first cyclic shift m₀And a second cyclic shift m₁The association of (c) is not limited to the order shown in fig. 9, for example, any other order is also possible.

In addition, according to an embodiment, m may be shifted based on the first cycle₀And a second cyclic shift m₁To determine cell ID N_ID. Because there is a shift value m from the first cycle₀And a second cyclic shift value m₁To PSS sequence indexingAnd SSS sequence indexSo that this is possible, e.g. by simple inverse mapping ofSatisfies the following conditions:

shifting m based on the first cycle in a simple manner₀And a second cyclic shift m₁Determining PSS sequence indexAnd SSS sequence indexMitigating implementation of a large table in a client device to be based on a first cyclic shift m0 and a second cyclic shift m₁The need for a cell ID is determined.

According to an embodiment of the present embodiment, the index of the SSS sequence is determined by the index of the SSS sequenceAnd the index of the PSS sequenceEncoding to a first cyclic shift m₀And a second cyclic shift m₁First cyclic shift m₀And a second cyclic shift m₁Satisfies the following conditions:

where g is the first cyclic shift m₀Is an integer greater than 1, i.e. g > 1. L 'is a positive integer less than or equal to the length L of the SSS sequence, i.e. L' ≦ L; for a given first cyclic shift m₀Which is also the second cyclic shift m₁Is determined by the maximum number of candidates. Since g > 1, any two SSS sequences (m)₀，m₁) And (m'₀，m′₁) Can only satisfy m 'for cyclic shift pair'₀＝m₀+1 and m'₁＝m₁At most one of + 1.

As a non-limiting example, it is noted that for a new wireless system synchronization signal implementation, where L is 127 andin one possible implementation, for example, g 2 is provided,And L' 112, etc. to carry a total of 336 x 3-1008 cell IDs.

Fig. 10 shows a schematic and non-limiting illustration of an example of this embodiment. To be provided withL ═ 15, g ═ 2, and L ═ 8 are examples, and since g ═ 2, m 'is not satisfied in all cases'₀＝m₀+1 and m'₁＝m₁+1 two cyclically shifted pairs (m)₀，m₁) And (m'₀，m′₁). This is illustrated in fig. 10, where every second position along the diagonal is not used, i.e. the positions that can be selected (black dots) are separated on the diagonal by positions that may not be selected (white dots). Therefore, m 'is not satisfied at the same time in the diagram of FIG. 10'₀＝m₀+1 and m'₁＝m₁+1. In FIG. 10, PSS sequence indexIs the y-axis, where m₀0 and m₀All have the same PSS sequence index as 4I.e. m₀0 and m₀4 are all indexed with the same PSS sequenceAnd (4) associating. Accordingly, m₀2 and m₀6 are all indexed with the same PSS sequenceAnd (4) associating. It should be noted that the PSS sequence indexAnd a first cyclic shift m₀And SSS indexAnd m₀And m₁The association of (a) is not limited to the order shown in fig. 10. Rather, any other order is possible.

In addition, according to an embodiment, m may be shifted based on the first cycle₀And a second cyclic shift m₁To determine cell ID N_ID. Because there is a shift value m from the first cycle₀And a second cyclic shift value m₁To PSS sequence indexingAnd SSS sequence indexSo that this is possible, e.g. by simple inverse mapping ofSatisfies the following conditions:

shifting m based on the first cycle in a simplified manner₀And a second cyclic shift m₁Determining PSS sequence indexAnd SSS sequence indexMitigating implementation of large tables in client devices to shift m based on first cycle₀And a second cyclic shift m₁The need for a cell ID is determined.

According to the implementation manner of the embodiment, the sequence index carried in the PSSAnd sequence index carried in SSSEncoding to a first cyclic shift m₀And a second cyclic shift m₁First cyclic shift m₀And a second cyclic shift m₁Satisfies the following conditions:

wherein g > 1 is a second cyclic shift m₁Is given, and L' ≦ L is the given first cyclic shift m₀Second cyclic shift m₁Is determined by the maximum number of candidates. Since g > 1, any two SSS sequences, e.g. (m)₀，m₁) And (m'₀，m′₁) Of cyclic shift pair can only satisfy m'₀＝m₀+1 and m'₁＝m₁At most one of + 1. At the same time, the generated/selected cyclic shift pair always satisfies m₀＜m₁(or equivalent to m)₀＞m₁). This is advantageous if the SSS is transmitted twice every 10ms, i.e. once in each field, since it allows to pass simply between two fieldsGround exchange m₀And m₁To indicate 5ms timing using SSS sequences (e.g., done in LTE). Alternatively, if later thought helpful in increasing the number of hypotheses in the SSS, embodiments provide a future-oriented solution, e.g., for future new wireless releases.

As a non-limiting example, it is to be mentioned that for a new wireless synchronization signal implementation, where L is 127 andin one possible implementation, for example, g 2 is provided,And L' 115, etc. to implement the present embodiment to carry 336 × 3 to 1008 cell IDs in total.

Fig. 11 shows a non-limiting example illustration of this embodiment. To be provided withFor example, in fig. 11, the PSS sequence index is illustrated as L ═ 15, g ═ 2, and L ═ 8Is the y-axis, where m₀0 and m₀All have the same PSS sequence index as 4I.e. m₀0 and m₀4 are all indexed with the same PSS sequenceAnd (4) associating. Accordingly, m₀2 and m₀6 are all indexed with the same PSS sequenceAnd (4) associating. It should be noted that the PSS sequence indexAnd a first cyclic shift m₀And SSS indexAnd a first cyclic shift m₀And a second cyclic shift m₁The association of (c) is not limited to the order shown in fig. 11, for example, any other order is also possible.

In addition, according to an embodiment, m may be shifted based on the first cycle₀And a second cyclic shift m₁To determine cell ID N_ID. Because there is a shift value m from the first cycle₀And a second cyclic shift value m₁To PSS sequence indexingAnd SSS sequence indexSo that this is possible, e.g. by simple inverse mapping ofSatisfies the following conditions:

shifting m based on the first cycle in a simple manner₀And a second cyclic shift m₁Determining PSS sequence indexAnd SSS sequence indexMitigating implementation of large tables in client devices to shift m based on first cycle₀And a second cyclic shift m₁The need for a cell ID is determined.

According to an embodiment, if two cyclic shift pairs (m)₀，m₁) And (m'₀，m′₁) Different PSS sequence indexAssociated, then two cyclic shift pairs (m) are allowed₀，m₁) And (m'₀，m′₁) All satisfy m'₀＝m₀+1 and m'₁＝m₁+1. Accordingly, robustness against a large frequency offset is ensured.

According to the cyclic shift pair of the present embodiment, for example, the sequence carried in the PSS can be indexed, i.e., byCoding to one of the two binary sequences, e.g. for the first cyclic shift m₀And requires a first cyclic shift m associated with the same primary synchronization signal PSS sequence index₀Are spaced from each other by more than one cyclic shift step while allowing different PSS sequence indicesEncoding to a first cyclic shift m₀A continuous value of (c). First cyclic shift m₀May be kept to a minimum so that SSS detection based on low-cost/low-complexity scrambling-FWHT may be utilized in the client device 500.

The sequence carried by the SSS can be indexed, i.e.Coded into two m-sequences m₀And m₁Cyclic shift of (1), wherein m is allowed₁Including all or most of its significant values 0, 1, 2. This SSS design results in the case where one SSS sequence can be obtained by cyclically shifting another SSS sequence by one cyclic shift step. However, according to an embodiment, such a pair of SSS sequences is always indexed with different PSS sequencesAre associated and are not detected simultaneously after successful PSS detection in client device 500.

It should be noted that the index of the PSS sequence is usedEncoding to a first cyclic shift m₀And indexing of SSS sequencesEncoding to a first cyclic shift m₀And a second cyclic shift m₁Can be done in any way, e.g. m₀And m₁Can be exchanged in the equations below. Given a first cyclic shift m₀Of (d), then for the first cyclic shift m₀By a different value of, a second cyclic shift of m₁May be the same or different.

According to an implementation of an embodiment, the sequence may be indexedAndencoding to a first cyclic shift m₀And a second cyclic shift m₁For example, the first cycle may be shifted by m₀And a second cyclic shift m₁M determined to satisfy the following₀And m₁：

Equations 18 and 19 may also be understood as limited/restricted versions of the encoding methods in equations (10) and (11) above, g being exemplified here with a value of 1, i.e. g ═ 1. According to implementationBy way, if two SSS sequences are associated with different PSS indices according to equations (18) and (19), two SSS sequences are allowed to coexist, with cyclic shift pairs (m) of the two sequences₀，m₁) And (m'₀，m′₁) M 'is satisfied'₀＝m₀+1 and m'₁＝m₁+1. This is advantageous because a cyclic shift pair (m) can be selected₀，m₁) Makes it possible to encode a greater number of cell IDs and possibly other additional information into the SSS sequence without increasing the length of the SSS sequence.

As a non-limiting example, it is to be mentioned that for a new wireless synchronization signal implementation, where L is 127 andfor example, by lettingAnd L' 112, etc. the present embodiment is used to carry 336 × 3 to 1008 cell IDs in total.

Figure 12 gives an illustration of the present example. To be provided withAs examples of L15 and L' 8, in fig. 12, PSS sequence indexIs the y-axis, where m₀0 and m₀All have the same PSS sequence index 2I.e. m₀0 and m₀2 are all indexed with the same PSS sequenceAnd (4) associating. Accordingly, m₀1 and m₀3 are all indexed with the same PSS sequenceAnd (4) associating. It should be noted that the PSS sequence indexAnd a first cyclic shift m₀And SSS sequence indexAnd a first cyclic shift m₀And a second cyclic shift m₁The association of (c) is not limited to the order shown in fig. 12. On the contrary, as long as the same PSS indexCyclic shift pairs of any two SSS sequences in association, e.g. (m)₀，m₁) And (m'₀，m′₁) M 'is satisfied'₀＝m₀+1 and m'₁＝m₁+1, any other order is possible.

In addition, according to an embodiment, m may be shifted based on the first cycle₀And a second cyclic shift m₁To determine cell ID N_ID. Because there is a shift value m from the first cycle₀And a second cyclic shift value m₁To PSS sequence indexingAnd SSS sequence indexSo that this is possible, e.g. by simple inverse mapping ofSatisfies the following conditions:

equations 20 and 21 may also be understood as limited/restricted versions of the inverse mappings in equations (12) and (13) above, e.g., where g is exemplified by the value 1, i.e., g ═ 1. This mitigates implementing a large table in the client device 500 to shift m based on the first cycle₀And a second cyclic shift m₁The need for a cell ID is determined.

According to an embodiment, if two cyclic shift pairs (m)₀，m₁) And (m'₀，m′₁) Different PSS sequence indexAre correlated and the generated cyclic shift pair always satisfies m₀＜m₁(or m)₀＞m₁) Then two cyclic shift pairs (m) are allowed₀，m₁) And (m'₀，m′₁) All satisfy m'₀＝m₀+1 and m'₁＝m₁+1。

According to an implementation of an embodiment, the sequence may be indexedAndencoding to a first cyclic shift m₀And a second cyclic shift m₁The first cycle may be shifted by m₀And a second cyclic shift m₁Is determined to satisfy the following:

equations 22 and 23 may be understood as restricted/limited versions of the encoding methods in equations (14) and (15) above, e.g., where g is exemplified by the value 1, i.e., g ═ 1. According to an embodiment, if according to equations (22) and (b)(23) The two SSS sequences are associated with different PSS indices, and the generated cyclic shift pair always satisfies m₀＜m₁(or equivalent to m)₀＞m₁) Then two SSS sequences are allowed to coexist, with cyclic shift pairs (m0, m1) and (m'₀，m′₁) All satisfy m'₀＝m₀+1 and m'₁＝m₁+1. As mentioned above, this is advantageous because it allows for the exchange of m₀And m₁To indicate 5ms timing using SSS sequences, as used in systems in LTE. Or if later thought to be helpful in increasing the number of assumptions in the SSS, constitutes a future-oriented solution for future new wireless release systems.

As a non-limiting example, it is to be mentioned that for a new wireless synchronization signal implementation, where L is 127 andin one possible implementation, settingAnd L' 112, etc. the present embodiment is used to carry 336 × 3 to 1008 cell IDs in total. To be provided withFig. 13 shows a non-limiting illustration of this embodiment, taking L15 and L' 8 as examples. In FIG. 13, PSS sequence indexIs the y-axis, where m₀0 and m₀All have the same PSS sequence index 2I.e. m₀0 and m₀2 are all indexed with the same PSS sequenceAnd (4) associating. Accordingly, m₀1 and m₀3 are all indexed with the same PSS sequenceAnd (4) associating. It should be noted that the PSS sequence indexAnd a first cyclic shift m₀And SSS sequence indexAnd a first cyclic shift m₀And a second cyclic shift m₁The association of (c) is not limited to the order shown in fig. 13. On the contrary, as long as the same PSS indexCyclic shift pairs of any two SSS sequences in association, e.g. (m)₀，m₁) And (m'₀，m′₁) M 'is satisfied'₀＝m₀+1 and m'₁＝m₁At most one of +1, and if the generated cyclic shift pair always satisfies m₀＜m₁(or m)₀＞m₁) Any other order is possible.

In addition, according to an embodiment, m may be shifted based on the first cycle₀And a second cyclic shift m₁To determine cell ID N_ID. Because there is a shift value m from the first cycle₀And a second cyclic shift value m₁To PSS sequence indexingAnd SSS sequence indexSo that this is possible, e.g. by simple inverse mapping ofSatisfies the following conditions:

equations 24 and 25 may also be understood as limited/restricted versions of the inverse mappings in equations (16) and (17) above, here exemplified with the value of g being 1, i.e. g ═ 1. This mitigates implementing a large table in the client device 500 to base the first cyclic shift value m₀And a second cyclic shift value m₁The need for a cell ID is determined.

As described above, the determination of at least one cell ID N may be made in accordance with various embodiments described herein_IDAssociated first cyclic shift m₀And a second cyclic shift m₁And thus will have various interrelationships.

According to some embodiments described herein, the first cyclic shift m may be shifted as shown, for example, in fig. 8, 10 and 12₀And a second cyclic shift m₁Making a determination such that the first cyclic shift m₀And a second cyclic shift m₁Equal, i.e. m₀＝m₁That is to say there are positions available on the diagonal through the origin of coordinates.

According to some embodiments described herein, the first cyclic shift m may be shifted as shown, for example, in fig. 9, 11 and 13₀And a second cyclic shift m₁Making a determination such that the first cyclic shift m₀And a second cyclic shift m₁Different, i.e. m₀≠m₁I.e. there is no position available on the diagonal through the origin of coordinates.

According to some embodiments described herein, the first cyclic shift m may be₀And a second cyclic shift m₁Making a determination such that the first cyclic shift m₀Greater than a second cyclic shift m₁I.e. m₀＞m₁That is to say there are only positions available above the diagonal through the origin of coordinates.

According to some embodiments described herein, examplesAs shown in fig. 9, 11, 13, the first cyclic shift may be m₀And a second cyclic shift m₁Making a determination such that the first cyclic shift m₀Less than a second cyclic shift m₁I.e. m₀＜m₁I.e. there are only positions available below the diagonal through the origin of coordinates.

According to some embodiments described herein, the first cyclic shift m may be shifted as shown, for example, in fig. 8, 9, 10 and 11₀And a second cyclic shift m₁Making a determination such that two cyclic shift pairs (m)₀，m₁) And (m'₀，m′₁) M 'is satisfied'₀＝m₀+1 and m'₁＝m₁At most one of +1, i.e. there is always an unused position between the available positions in the diagonal direction.

According to some embodiments described herein, the first cyclic shift m may be₀And a second cyclic shift m₁Making a determination such that two cyclic shift pairs (m)₀，m₁) And (m'₀，m′₁) M 'is satisfied'₀＝m₀+1 and m'₁＝m₁At most one of +1, and a first cyclic shift m₀Greater than a second cyclic shift m₁I.e. m₀＞m₁That is, there is always an unused position between available positions in the diagonal direction through the origin of coordinates, and there is only an available position above the diagonal.

According to some embodiments described herein, the first cyclic shift m may be shifted as shown in fig. 9 and 11, for example₀And a second cyclic shift m₁Making a determination such that two cyclic shift pairs (m)₀，m₁) And (m'₀，m′₁) M 'is satisfied'₀＝m₀+1 and m'₁＝m₁At most one of +1, and a first cyclic shift m₀Less than a second cyclic shift m₁I.e. m₀＜m₁That is, there is always an unused position between available positions in the diagonal direction through the origin of coordinates, and there is only available positions below the diagonalThe position is used.

According to some embodiments described herein, for example, as shown in fig. 12 and 13, a first cyclic shift m0 and a second cyclic shift m may be shifted₁Are determined so that all satisfy m'₀＝m₀+1 and m'₁＝m₁+1 two cyclically shifted pairs (m)₀，m₁) And (m'₀，m′₁) Sequence index of primary synchronization signal PSS different from that of primary synchronization signal PSSAnd (4) associating.

According to some embodiments described herein, the first cyclic shift m may be₀And a second cyclic shift m₁Are determined so that all satisfy m'₀＝m₀+1 and m'₁＝m₁+1 two cyclically shifted pairs (m)₀，m₁) And (m'₀，m′₁) With different primary synchronization signal PSS indicesAssociated, and a first cyclic shift m₀Greater than a second cyclic shift m₁I.e. m₀＞m₁That is, there is only a position available above the diagonal through the origin of coordinates.

According to some embodiments described herein, the first cyclic shift may be m, as shown in fig. 13₀And a second cyclic shift m₁Are determined so that all satisfy m'₀＝m₀+1 and m'₁＝m₁+1 two cyclically shifted pairs (m)₀，m₁) And (m'₀，m′₁) Sequence indexing with different Primary Synchronization Signals (PSS)Associated, and a first cyclic shift m₀Less than a second cyclic shift m₁I.e. m₀＜m₁I.e. there is only a position available below the diagonal through the origin of coordinates.

Finally, it is to be understood that the invention is not limited to the embodiments described above, but relates to and encompasses all embodiments within the scope of the following independent claims.