阅读说明：本技术 定时恢复的定时锁定识别方法与信号接收电路 (Timing lock identification method for timing recovery and signal receiving circuit ) 是由 李荣芸 于 2018-06-14 设计创作，主要内容包括：本发明的实施例提供一种定时恢复的定时锁定识别方法。此方法包括：由定时恢复电路产生第一相位调整脉波与第二相位调整脉波,其中所述第一相位调整脉波用以增加震荡器的输出信号的相位,且所述第二相位调整脉波用以减少所述输出信号的所述相位；以及获得检测窗内所述第一相位调整脉波与所述第二相位调整脉波的数量差,并根据所述数量差判断所述定时恢复电路是否达到定时恢复的锁定状态。此外,本发明的实施例也提供相应的信号接收电路。(The embodiment of the invention provides a timing lock identification method for timing recovery. The method comprises the following steps: generating, by a timing recovery circuit, a first phase adjustment pulse to increase a phase of an output signal of an oscillator and a second phase adjustment pulse to decrease the phase of the output signal; and obtaining the quantity difference of the first phase adjustment pulse wave and the second phase adjustment pulse wave in the detection window, and judging whether the timing recovery circuit reaches a locking state of timing recovery or not according to the quantity difference. In addition, the embodiment of the invention also provides a corresponding signal receiving circuit.)

1. A timing lock identification method for timing recovery comprises the following steps:

generating a first phase adjustment pulse and a second phase adjustment pulse by a timing recovery circuit according to an input signal, wherein the first phase adjustment pulse is used for increasing the phase of an output signal of an oscillator, and the second phase adjustment pulse is used for decreasing the phase of the output signal; and

and acquiring the quantity difference of the first phase adjustment pulse wave and the second phase adjustment pulse wave in the detection window, and judging whether the timing recovery circuit reaches a timing recovery locking state or not according to the quantity difference.

2. The phase lock identification method of claim 1, wherein the step of determining whether the timing recovery circuit reaches the lock state for timing recovery based on the number difference comprises:

if the quantity difference is not greater than a threshold value, the timing recovery circuit is judged to reach the locking state of the timing recovery; and

if the number difference is greater than the threshold value, it is determined that the timing recovery circuit has not reached the locked state for timing recovery.

3. The phase lock identification method of claim 1, wherein the step of determining whether the timing recovery circuit reaches the lock state for timing recovery based on the number difference comprises:

and if P first phase adjustment pulses are continuously detected in the detection window or Q second phase adjustment pulses are continuously detected in the detection window, determining that the timing recovery circuit does not reach the locking state of the timing recovery, wherein P and Q are integers larger than 1.

4. A phase lock identification method according to claim 1 wherein the step of determining whether the timing recovery circuit has reached the locked state of the timing recovery based on the magnitude difference comprises:

obtaining a first number difference between the first phase adjustment pulse wave and the second phase adjustment pulse wave in a first detection window;

if the first quantity difference is not greater than a first threshold value, updating a second quantity difference corresponding to a second detection window according to the first quantity difference, wherein the first detection window is included in the second detection window; and

and judging whether the timing recovery circuit reaches the locking state of the timing recovery according to the second quantity difference.

5. The method of claim 4, wherein the step of determining whether the timing recovery circuit reaches the locked state of the timing recovery according to the magnitude difference further comprises:

if the first quantity difference is larger than the first threshold value or the second quantity difference is larger than a second threshold value, resetting the second quantity difference and updating the detection range of the second detection window; and

and moving the first detection window according to the updated detection range of the second detection window.

6. The method of claim 4, wherein the step of determining whether the timing recovery circuit reaches the locked state of the timing recovery according to the magnitude difference further comprises:

if the first quantity difference is not larger than the first threshold value, the detection range of the first detection window is moved from the first detection range in the second detection window to the second detection range in the second detection window.

7. The method of claim 4, wherein the step of determining whether the timing recovery circuit reaches the locked state of the timing recovery according to the second number difference comprises:

if the detection range of the first detection window already covers the complete detection range of the second detection window and the second quantity difference is not greater than the second threshold value, the timing recovery circuit is judged to reach the locking state of the timing recovery.

8. The method of claim 4, wherein the step of determining whether the timing recovery circuit reaches the locked state of the timing recovery according to the magnitude difference further comprises:

resetting the second quantity difference and updating the detection range of the second detection window if P first phase adjustment pulses are continuously detected in the first detection window or Q second phase adjustment pulses are continuously detected in the first detection window, wherein P and Q are integers larger than 1; and

and moving the first detection window according to the updated detection range of the second detection window.

9. A signal receiving circuit, comprising:

a receiving circuit that receives an input signal;

a timing recovery circuit connected to the receiving circuit and generating a first phase adjustment pulse and a second phase adjustment pulse according to the input signal; and

an oscillator coupled to the receiving circuit and the timing recovery circuit, generating an output signal and increasing a phase of the output signal according to the first phase adjustment pulse or decreasing the phase of the output signal according to the second phase adjustment pulse,

the timing recovery circuit judges whether a locking state of timing recovery is achieved based on the number difference of the first phase adjustment pulse wave and the second phase adjustment pulse wave in the detection window.

10. The signal receiving circuit of claim 9, wherein the operation of the timing recovery circuit determining whether the locked state of the timing recovery is achieved based on the difference in the number of the first phase adjustment pulse and the second phase adjustment pulse within the detection window comprises:

if the quantity difference is not greater than a threshold value, determining that the locking state of the timing recovery is reached; and

if the number difference is greater than the threshold value, the locking state of the timing recovery is not reached.

11. The signal receiving circuit of claim 9, wherein the operation of the timing recovery circuit determining whether the locked state of the timing recovery is achieved based on the difference in the number of the first phase adjustment pulse and the second phase adjustment pulse within the detection window comprises:

if P first phase adjustment pulses are continuously detected in the detection window or Q second phase adjustment pulses are continuously detected in the detection window, the locking state of the timing recovery is not reached, wherein P and Q are integers larger than 1.

12. The signal receiving circuit of claim 9, wherein the operation of the timing recovery circuit determining whether the locked state of the timing recovery is achieved based on the difference in the number of the first phase adjustment pulse and the second phase adjustment pulse within the detection window comprises:

obtaining a first number difference between the first phase adjustment pulse wave and the second phase adjustment pulse wave in a first detection window;

if the first quantity difference is not greater than a first threshold value, updating a second quantity difference corresponding to a second detection window according to the first quantity difference, wherein the first detection window is included in the second detection window; and

and judging whether the locking state of the timing recovery is reached or not according to the second number difference.

13. The signal receiving circuit of claim 12, wherein the operation of the timing recovery circuit determining whether the locked state of the timing recovery is achieved based on the difference in the number of the first phase adjustment pulse and the second phase adjustment pulse within the detection window further comprises:

if the first quantity difference is larger than the first threshold value or the second quantity difference is larger than a second threshold value, resetting the second quantity difference and updating the detection range of the second detection window; and

and moving the first detection window according to the updated detection range of the second detection window.

14. The signal receiving circuit of claim 12, wherein the operation of the timing recovery circuit to determine whether the timing recovery circuit has reached the locked state for the timing recovery based on the difference in the number of the first phase adjustment pulse and the second phase adjustment pulse within the detection window further comprises:

if the first quantity difference is not larger than the first threshold value, the detection range of the first detection window is moved from the first detection range in the second detection window to the second detection range in the second detection window.

15. The signal receiving circuit of claim 12, wherein the operation of the timing recovery circuit to determine whether the timing recovery circuit has reached the locked state for timing recovery based on the second number difference comprises:

if the detection range of the first detection window already covers the complete detection range of the second detection window and the second quantity difference is not greater than the second threshold value, the locking state of the timing recovery is determined to be reached.

16. The signal receiving circuit of claim 12, wherein the operation of the timing recovery circuit determining whether the locked state of the timing recovery is achieved based on the difference in the number of the first phase adjustment pulse and the second phase adjustment pulse within the detection window further comprises:

resetting the second quantity difference and updating the detection range of the second detection window if P first phase adjustment pulses are continuously detected in the first detection window or Q second phase adjustment pulses are continuously detected in the first detection window, wherein P and Q are integers larger than 1; and

and moving the first detection window according to the updated detection range of the second detection window.

Technical Field

The present invention relates to timing recovery (timing recovery) technology, and more particularly, to a timing lock identification method for timing recovery and a signal receiving circuit.

Background

After the signal is transmitted from the transmitting end, the signal may be attenuated and interfered by noise. Therefore, a timing recovery circuit is usually required to be disposed in the signal receiving apparatus at the receiving end to perform timing recovery operations such as channel compensation, noise filtering, and timing error elimination on the received signal. Generally, after the timing recovery operation of the timing recovery circuit is started, the decision can be made by Mean Square Error (MSE) or phase Error phase detection (also called S-curve). However, the mean square error is affected by the setting of the threshold, so that the decision result has an error. In addition, S-curve has a non-linear interval, resulting in a false lock (false-lock) condition in the decision result. In other words, the decision robustness (robustness) cannot be guaranteed by using both of the above two approaches.

Disclosure of Invention

In view of the above, the present invention provides a timing lock identification method for timing recovery and a signal receiving circuit, which can improve the identification efficiency of timing lock.

The embodiment of the invention provides a timing lock identification method for timing recovery, which comprises the following steps: generating, by a timing recovery circuit, a first phase adjustment pulse to increase a phase of an output signal of an oscillator and a second phase adjustment pulse to decrease the phase of the output signal; and obtaining the quantity difference of the first phase adjustment pulse wave and the second phase adjustment pulse wave in the detection window, and judging whether the timing recovery circuit reaches a locking state of timing recovery or not according to the quantity difference.

The embodiment of the invention also provides a signal receiving circuit, which comprises a receiving circuit, a timing recovery circuit and an oscillator. The receiving circuit receives an input signal and generates an output signal. The timing recovery circuit is connected to the receiving circuit and generates a first phase adjustment pulse and a second phase adjustment pulse. The oscillator is coupled to the receiving circuit and the timing recovery circuit and increases a phase of the output signal according to the first phase adjustment pulse or decreases the phase of the output signal according to the second phase adjustment pulse. The timing recovery circuit determines whether or not a locked state of timing recovery is achieved based on a difference in the number of the first phase adjustment pulse waves and the second phase adjustment pulse waves in a detection window.

Based on the above, after the timing recovery circuit generates the first phase adjustment pulse and the second phase adjustment pulse, the difference between the first phase adjustment pulse and the second phase adjustment pulse in the detection window can be obtained. Based on the difference in the number, whether the timing recovery circuit reaches a locked state for timing recovery can be determined. Therefore, the identification efficiency of the locking state of the timing recovery can be effectively improved.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 is a schematic diagram of a signal receiving circuit according to an embodiment of the invention.

Fig. 2 is a flowchart illustrating a timing lock identification method for timing recovery according to an embodiment of the invention.

Fig. 3 is a schematic diagram illustrating detection of a first phase adjustment pulse and a second phase adjustment pulse according to an embodiment of the invention.

Fig. 4 is a flowchart illustrating a timing lock identification method for timing recovery according to an embodiment of the invention.

Fig. 5A to 5D are schematic diagrams illustrating detection of the first phase adjustment pulse and the second phase adjustment pulse according to an embodiment of the invention.

Fig. 6 is a schematic diagram illustrating detection of the first phase adjustment pulse and the second phase adjustment pulse according to an embodiment of the invention.

Description of the reference numerals

10: signal receiving circuit

101: receiving circuit

102: timing recovery circuit

103: oscillator

S201, S202, S401 to S408: step (ii) of

301. 501 and 502: detection window

Detailed Description

Fig. 1 is a schematic diagram of a signal receiving circuit according to an embodiment of the invention. Fig. 2 is a flowchart illustrating a timing lock identification method for timing recovery according to an embodiment of the invention.

Referring to fig. 1 and 2, the signal receiving circuit 10 receives a signal S1 (also referred to as an input signal) and performs operations related to signal reception and adjustment, such as channel compensation, noise filtering, and timing error elimination, on the signal S1 to output a signal S2. The signal S1 can be, for example, Ethernet (Ethernet) signal, and the signal receiving circuit 10 can be disposed in a wired or wireless network interface card or other networking device.

The signal receiving circuit 10 includes a receiving circuit 101, a timing recovery (timing recovery) circuit 102, and an oscillator 103. The receiving circuit 101 is used for receiving the signal S1 and performing channel compensation, noise filtering, and sampling operations on the signal S1. For example, the receiving circuit 101 may include an Analog-to-Digital Converter (ADC) and an equalizer (or an adaptive equalizer). The adc performs adc conversion on the signal S1, and the equalizer performs channel compensation and noise filtering on the converted signal S1 to output a signal S2. It should be noted that the present invention is not limited to the specific circuit composition of the receiving circuit 101 as long as the aforementioned functions can be provided.

The timing recovery circuit 102 is connected to the receiving circuit 101 and the oscillator 103. The timing recovery circuit 102 is configured to analyze the signal S2 and perform a timing recovery operation. For example, the timing recovery circuit 102 may include a digital signal processor and at least one counter. In the timing recovery operation, the timing recovery circuit 102 may generate a pulse ADV (also referred to as a first phase adjustment pulse) and a pulse RET (also referred to as a second phase adjustment pulse) according to the execution state of the timing recovery operation (step S201). The pulse ADV is used to increase the phase of the output signal of the oscillator 103 (i.e., the signal S3), and the pulse RET is used to decrease the phase of the signal S3.

In the present embodiment, the oscillator 103 is a Voltage Controlled Oscillator (VCO) as an example, but the invention is not limited to the type of the oscillator 103. The oscillator 103 receives the pulses ADV and RET and outputs a signal S3. When the oscillator 103 receives the pulse ADV, the oscillator 103 increases the phase of the signal S3. When the oscillator 103 receives the pulse RET, the oscillator 103 decreases the phase of the signal S3. Alternatively, from another perspective, the signal S3 is a clock signal. The oscillator 103 decreases the delay of the signal S3 according to the ADV pulse and increases the delay of the signal S3 according to the RET pulse. The receiving circuit 101 may sample the signal S1 according to the signal S3. By the pulses ADV and RET, the timing of the signal S3 can be gradually adjusted to be synchronous with the timing of the signal S1, thereby increasing the sampling accuracy for the signal S1.

In the process of performing the timing recovery operation, the timing recovery circuit 102 can obtain the difference between the numbers of the pulse wave ADV and the pulse wave RET in a detection window. For example, the timing recovery circuit 102 may count the number of pulses ADV and the number of pulses RET in the detection window by a counter and calculate the difference between the two numbers. The timing recovery circuit 102 can determine whether a lock state (also referred to as a lock state for timing recovery) is reached based on the difference (step S202). It should be noted that the timing recovery circuit 102 reaches the locked state, which means that the timing of the signal S3 has been adjusted to be synchronous (or nearly synchronous) with the timing of the signal S1. In one embodiment, the timing recovery circuit 102 may be considered to be in the locked state when the timing (or clock frequency) of the signal S3 is in the steady state (or converged state).

If the timing recovery circuit 102 is determined not to have reached the locked state, the timing recovery circuit 102 may be in a capture phase. During the capture phase, the timing recovery circuit 102 may adjust the clock frequency of the signal S3 using a larger adjustment magnitude (or step size) to cause the timing of the signal S3 to be adjusted to be synchronized with the timing of the signal S1 as soon as possible. However, if it is determined that the timing recovery circuit 102 has reached the locked state, the timing recovery circuit 102 may enter the tracking phase. In the tracking phase, the timing recovery circuit 102 may adjust the clock frequency of the signal S3 using a smaller adjustment amplitude (also referred to as a second adjustment amplitude) to more accurately adjust the timing of the signal S3 to be synchronized with the timing of the signal S1. Viewed from another perspective, if the timing recovery circuit 102 is determined not to have reached the locked state, the timing recovery circuit 102 may adjust the clock frequency of the signal S3 using a certain adjustment amplitude (also referred to as a first adjustment amplitude). If it is determined that the timing recovery circuit 102 has reached the locked state, the timing recovery circuit 102 may adjust the clock frequency of the signal S3 using another adjustment magnitude (also referred to as a second adjustment magnitude). Wherein the first adjustment amplitude is larger than the second adjustment amplitude.

In one embodiment, one detection window covers one time range (or time interval). Within this time range (i.e., within the detection window), the timing recovery circuit 102 can count the number of pulses ADV and the number of pulses RET. If the difference between the numbers of ADV and RET pulses in the detection window is not greater than a threshold, the timing recovery circuit 102 can determine that the timing recovery lock state is reached. However, if the difference between the numbers of the pulses ADV and the pulses RET in the detection window is larger than the threshold value, the timing recovery circuit 102 determines that the locked state of the timing recovery has not been reached.

Fig. 3 is a schematic diagram illustrating detection of a first phase adjustment pulse and a second phase adjustment pulse according to an embodiment of the invention. It should be noted that fig. 3 shows the pulses ADV, RET and their quantities received at different points in time.

Referring to fig. 3, for convenience of illustration, in this embodiment, the threshold value is set to 2. Within the time range covered by the detection window 301 (i.e., the time range from the time point T31 to the time point T32), 6 pulses ADV and 4 pulses RET are generated. Therefore, in the detection window 301, the number of pulses ADV that can be detected is 6, the number of pulses RET is 4, and the difference between the numbers of pulses ADV and RET is 2. In this embodiment, since the difference (i.e., 2) between the numbers of the pulses ADV and RET is not greater than the threshold (i.e., 2), it can be determined that the lock state for timing recovery has been reached.

In one embodiment, the timing recovery circuit 102 may also determine whether P pulses ADV are detected continuously within a set detection window or Q pulses RET are detected continuously within the detection window. Wherein, P and Q are positive integers, and P and Q can be the same or different. It should be noted that the continuous detection of P pulses ADV means that no pulse RET is detected within the time range of the continuous detection of P pulses ADV. Similarly, the continuous detection of Q pulses RET means that no pulse ADV is detected within the time range of the continuous detection of Q pulses RET.

If P pulses ADV are detected continuously within the set detection window or Q pulses RET are detected continuously within the detection window, the timing recovery circuit 102 can determine that the timing recovery locked state has not been reached. Taking fig. 3 as an example, if P is 4, it can be directly determined that the locked state of timing recovery has not been reached when 4 pulses ADV are continuously detected in the detection window 301. Alternatively, if Q is 2, it can be directly determined that the locked state of timing recovery has not been reached when 2 pulses RET are continuously detected in the detection window 301.

In one embodiment, the two operations of determining whether to achieve the timing recovery lock state according to the difference between the numbers of the pulses ADV and RET and determining whether to achieve the timing recovery lock state according to whether the pulses ADV or RET are continuously detected can be simultaneously adopted. For example, in the embodiment of fig. 3, even if the difference (i.e., 2) between the numbers of ADV and RET in the detection window 301 is not greater than the threshold (i.e., 2), it can be determined that the timing recovery lock state has not been reached because P (e.g., 4) consecutive pulses ADV have been detected.

It should be noted that the present invention does not limit the time length of the actual coverage of the detection window. For example, in one embodiment of fig. 3, once P successive pulses ADV or Q successive pulses RET are detected within the detection window 301, the detection window 301 may be closed. Alternatively, in one embodiment, if a combination of R pulses ADV and RET that are staggered is detected, it may be determined that the timing recovery lock state has been reached, and the detection window 301 may be closed. Wherein R can be any positive integer, depending on the practical requirements. For example, if 1 pulse ADV, 1 pulse RET, 1 pulse ADV, and 1 pulse RET are detected sequentially within a certain time range (i.e., 2 sets (R ═ 2) of interleaved pulses ADV and RET), it can be determined that the lock state for timing recovery has been reached. In addition, in another embodiment, a plurality of detection windows with different time ranges may be used together to increase the decision efficiency.

Fig. 4 is a flowchart illustrating a timing lock identification method for timing recovery according to an embodiment of the invention.

Referring to fig. 4, in step S401, a detection window (also referred to as a first detection window) is set and a difference between the numbers of the pulses ADV and RET in the first detection window (also referred to as a first number difference) is obtained. In step S402, it is determined whether the first magnitude difference is not greater than a threshold (also referred to as a first threshold). If the first magnitude difference is not greater than the first threshold, in step S403, a magnitude difference (also referred to as a second magnitude difference) corresponding to another detection window (also referred to as a second detection window) is updated according to the first magnitude difference, and the first detection window is included in the second detection window. For example, updating the second quantity difference based on the first quantity difference may include adding the current second quantity difference to the currently obtained first quantity difference.

In step S404, it is determined whether the second number difference is not greater than the second threshold. If the second quantity difference is not greater than the second threshold, in step S405, it is determined whether the detection range of the first detection window already covers the complete detection range of the second detection window. If the detection range of the first detection window already covers the complete detection range of the second detection window, in step S406, it is determined that the timing recovery circuit reaches the locked state of timing recovery. However, in step S405, if it is determined that the detection range of the first detection window does not cover the complete detection range of the second detection window, the process proceeds to step S407. In step S407, the detection range of the first detection window is moved from the current detection range (also referred to as the first detection range) within the second detection window to the next detection range (also referred to as the second detection range) within the second detection window, and then step S401 is repeated. The following description will be made of the implementation details of fig. 4 by taking fig. 5A to 5D and fig. 6 as examples.

Fig. 5A to 5D are schematic diagrams illustrating detection of the first phase adjustment pulse and the second phase adjustment pulse according to an embodiment of the invention.

Referring to fig. 4 and 5A, first, the inspection window 501 (i.e., the first inspection window) is set to include the time range between the time points T51 and T52, and the inspection window 502 (i.e., the second inspection window) is set to include the time range between the time points T51 and T55. In the present embodiment, it is assumed that the first threshold is 2, the second threshold is 8, and the initial value of the second number difference is 0. However, in another embodiment, the first threshold and the second threshold can be set to other values.

According to step S401 of fig. 4, within the detection window 501, the number of the first phase adjustment pulses ADV is 5, the number of the second phase adjustment pulses RET is 3, and the first number difference is 2(5-3 ═ 2). Therefore, it may be determined in step S402 that the first number difference (i.e., 2) is not greater than the first threshold value (i.e., 2). Next, in step S403, the second quantity difference (i.e., 0) may be updated to 2 (i.e., 0+2 to 2) according to the first quantity difference (i.e., 2). Then, since step S404 determines that the second quantity difference (i.e. 0) is not greater than the second threshold (i.e. 8) and step S405 determines that the time range of the detection window 501 does not cover the complete detection range of the detection window 502, step S407 moves the detection window 501 to the time range between time points T52 and T53, as shown in fig. 5B.

Referring to fig. 5B, after moving the detection window 501 to a time range between time points T52 and T53, step S401 can be repeatedly performed. According to step S401, in the shifted detection window 501, the number of the first phase adjustment pulses ADV is 4, the number of the second phase adjustment pulses RET is 3, and the first number difference is 1(4-3 equals 1). Therefore, it may be determined in step S402 that the first number difference (i.e., 1) is not greater than the first threshold value (i.e., 2). Next, in step S403, the second number difference (i.e., 2) may be updated to 3 (i.e., 2+1 to 3) according to the first number difference (i.e., 1). Then, since step S404 determines that the second quantity difference (i.e. 3) is not greater than the second threshold (i.e. 8) and step S405 determines that the time range of the detection window 501 does not cover the complete detection range of the detection window 502, step S407 moves the detection window 501 to the time range between time points T53 and T54, as shown in fig. 5C.

Referring to fig. 5C, after the detection window 501 is moved to a time range between time points T53 and T54, step S401 can be repeatedly performed. According to step S401, in the shifted detection window 501, the number of the first phase adjustment pulses ADV is 5, the number of the second phase adjustment pulses RET is 3, and the first number difference is 2(5-3 ═ 2). Therefore, it may be determined in step S402 that the first number difference (i.e., 2) is not greater than the first threshold value (i.e., 2). Next, in step S403, the second quantity difference (i.e., 3) may be updated to 5 (i.e., 3+2 to 5) according to the first quantity difference (i.e., 2). Then, since step S404 determines that the second quantity difference (i.e. 5) is not greater than the second threshold (i.e. 8) and step S405 determines that the time range of the detection window 501 does not cover the complete detection range of the detection window 502, step S407 moves the detection window 501 to the time range between time points T54 and T55, as shown in fig. 5D.

Referring to fig. 5D, after the detection window 501 is moved to the time range between time points T54 and T55, step S401 can be repeatedly performed. According to step S401, within the shifted detection window 501, the number of first phase adjustment pulses ADV is 2, the number of second phase adjustment pulses RET is 4, and the first number difference is 2(4-2 is 2). Therefore, it may be determined in step S402 that the first number difference (i.e., 2) is not greater than the first threshold value (i.e., 2). Next, in step S403, the second number difference (i.e., 5) may be updated to 7 (i.e., 5+2 to 7) according to the first number difference (i.e., 2). At this time, since the step S404 determines that the second quantity difference (i.e. 7) is not greater than the second threshold (i.e. 8), and the step S405 determines that the time range of the detection window 501 already covers the complete detection range of the detection window 502, it can be determined in step S406 that the timing recovery circuit has reached the timing recovery locked state.

Referring back to fig. 4, if the first quantity difference is greater than the first threshold in step S402 or the second quantity difference is greater than the second threshold in step S404, the process proceeds to step S408. In step S408, the second number difference is reset (e.g., to an initial value), the detection range of the second detection window is updated, and the first detection window is moved into the updated second detection window. Then, execution continues with step S401.

Fig. 6 is a schematic diagram illustrating detection of the first phase adjustment pulse and the second phase adjustment pulse according to an embodiment of the invention.

Please refer to fig. 4 and fig. 6, wherein fig. 6 can be continued from any of the embodiments of fig. 5A to fig. 5D. If it is determined in step S402 that the first magnitude difference is greater than the first threshold and/or the second magnitude difference is greater than the second threshold in step S404, the second magnitude difference is reset to the initial value (i.e., 0), the detection window 502 may be updated to cover the time range between time points T52 and T56, and the detection window 501 may be moved to cover the time range between time points T52 and T53. Then, the detection window 501 can be sequentially moved within the time range covered by the detection window 502 according to the flowchart of fig. 4 and the related counting operation is performed to determine whether the timing recovery circuit has reached the timing recovery locked state. For details of related operations, reference may be made to the embodiments of fig. 5A to 5D, which are not described herein again.

It should be noted that, in the embodiments of fig. 5A to 5D and fig. 6, the time lengths between time points T51 and T52, between time points T52 and T53, between time points T53 and T54, and between time points T54 and T55 are all the same, and the time length between time points T51 and T55 is 4 times the time length between time points T51 and T52. However, in another embodiment, the time length between the time points T51 and T55 may be 2 times or 3 times the time length between the time points T51 and T52, and the time lengths of any two adjacent time ranges may be different (e.g., the time length between the time points T51 and T52 may be different from the time length between the time points T52 and T53).

It should be noted that, in any of the embodiments of fig. 5A to 5D, it can also be determined whether P pulses ADV are continuously detected or Q pulses RET are continuously detected in the detection window 501. If P pulses ADV are detected continuously or Q pulses RET are detected continuously in the detection window 501, it can be directly determined that the lock state of timing recovery has not been reached. Alternatively, in any of the embodiments of fig. 5A to 5D, if P pulses ADV are continuously detected or Q pulses RET are continuously detected in the detection window 501, step S408 of fig. 4 may be executed, as shown in the embodiment of fig. 6. In addition, the steps of fig. 2 and 4 may be performed by the timing recovery circuit 102 of fig. 1.

In summary, in the process of performing the timing recovery operation on the input signal, based on the difference between the first phase adjustment pulse and the second phase adjustment pulse generated by the timing recovery circuit, whether the timing recovery circuit reaches the lock state of the timing recovery can be determined, so that the efficiency of identifying the lock state of the timing recovery can be effectively improved.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.