阅读说明：本技术 光源优化方法、光源优化装置、光刻系统及光刻方法 (Light source optimization method, light source optimization device, photoetching system and photoetching method ) 是由 刘娟 刘建忠 于世瑞 于 2019-09-20 设计创作，主要内容包括：本发明提供了一种光源优化方法,包括以下步骤：利用光刻机上不同的光源生成相应的PW OPC模型,所述PW OPC模型是建立在目标工艺窗口条件下能仿真出晶圆上光阻关键尺寸大小的模型；采用所述PW OPC模型对所述晶圆的目标版图进行模拟仿真,并输出多个评判参数；根据所有的所述评判参数筛选出对所述目标版图最友好的光源。所述光源优化方法与现有技术中采用不同的光源在硅片上收集数据的方式相比,不需要收集海量的焦点曝光矩阵(FEM)数据,节省大量的开发时间、人力以及机台资源,即能高效快捷地实现光源的筛选优化,提高光源筛选效率,而且更能直观地反映出不同光源之间的差别。本发明还提供了一种光源优化装置、光刻系统及光刻方法。(The invention provides a light source optimization method, which comprises the following steps: generating corresponding PW OPC models by utilizing different light sources on a photoetching machine, wherein the PW OPC models are models which can simulate the critical dimension of the optical resistance on the wafer under the condition of a target process window; performing analog simulation on the target layout of the wafer by adopting the PW OPC model, and outputting a plurality of judgment parameters; and screening out the most friendly light source to the target layout according to all the evaluation parameters. Compared with the mode of collecting data on a silicon chip by adopting different light sources in the prior art, the light source optimization method does not need to collect massive Focus Exposure Matrix (FEM) data, saves a great deal of development time, manpower and machine resources, can efficiently and quickly realize the screening optimization of the light sources, improves the screening efficiency of the light sources, and can more intuitively reflect the difference between different light sources. The invention also provides a light source optimization device, a photoetching system and a photoetching method.)

1. A method for optimizing a light source, comprising the steps of:

generating corresponding PW OPC models by utilizing different light sources on a photoetching machine, wherein the PW OPC models are models which can simulate the critical dimension of the optical resistance on the wafer under the condition of a target process window;

performing analog simulation on the target layout of the wafer by adopting the PW OPC model, and outputting a plurality of judgment parameters;

and screening out the most friendly light source to the target layout according to all the evaluation parameters.

2. The light source optimization method of claim 1, wherein the evaluation parameters comprise a process fluctuation bandwidth value, a reticle error enhancement factor, an aerial image normalized log slope, and a single point depth of focus.

3. The light source optimization method of claim 1, wherein the light source comprises a two-pole limit light source, a four-hole light source, and a six-hole light source.

4. The light source optimization method according to claim 1, wherein the target layout includes a one-dimensional figure or a two-dimensional figure; or the image comprises a one-dimensional array center position graph, a one-dimensional array edge position graph or a two-dimensional graph corner position graph.

5. The light source optimization method according to claim 2, wherein the step of selecting the most friendly light source to the target layout according to all the evaluation parameters comprises:

judging the friendliness degree of each light source on the photoetching machine to the target layout by using each judgment parameter, and generating a judgment result after one judgment parameter judges one light source;

and selecting the light source which is judged to be the most friendly by the most number of the judging parameters from all judging results, and taking the light source as the most friendly light source for the target layout.

6. A light source optimization device, comprising:

a PW OPC model generation module configured to generate corresponding PW OPC models using different light sources on the lithography machine, wherein the PW OPC models are models that can simulate the critical dimension of the optical resistance on the wafer under the condition of a target process window;

the simulation module is configured to perform simulation on the target layout of the wafer by adopting the PW OPC model and output a plurality of judgment parameters;

and the judging module is configured to screen out the most friendly light source to the target layout according to all the judging parameters.

7. The light source optimization apparatus of claim 6, wherein the evaluation parameters output by the simulation module comprise a process fluctuation bandwidth value, a reticle error enhancement factor, an aerial image normalized logarithmic slope, and a single point depth of focus.

8. The light source optimization device according to claim 6, wherein the step of selecting the most friendly light source to the target layout by the evaluation module according to all the evaluation parameters comprises:

judging the friendliness degree of each light source on the photoetching machine to the target layout by using each judgment parameter, wherein one judgment parameter judges one light source to generate a judgment result;

and selecting the light source which is judged to be the most friendly by the most number of the judging parameters from all judging results, and taking the light source as the most friendly light source for the target layout.

9. A lithography system, comprising a lithography machine with at least two light sources, a mask plate and the light source optimization device of any one of claims 6 to 8, wherein the light source optimization device is configured to select the most friendly light source to a target layout from all light sources on the lithography machine, the lithography machine is configured to expose a wafer by using the mask plate as a mask and using the most friendly light source selected by the light source optimization device to form a lithography pattern on the wafer.

10. A lithographic method, comprising:

selecting the most friendly light source to the target layout from all light sources on a photoetching machine by adopting the light source optimization method of any one of claims 1 to 5 or the light source optimization device of any one of claims 6 to 8;

and providing a mask plate for manufacturing the target layout, and exposing a wafer by using the mask plate as a mask and adopting the most friendly light source so as to form a photoetching pattern on the wafer.

Technical Field

The invention relates to the field of semiconductor manufacturing, in particular to a light source optimization method, a light source optimization device, a photoetching system and a photoetching method.

Background

With the reduction of the technology nodes, when the size of the graph is close to the limit of the photoetching capacity, the process window becomes smaller and smaller, and it is important to select a good light source in a short time in the development stage.

Generally, the industry method of screening light sources comprises the steps of: firstly, selecting a design layout and test patterns with different periods near a design rule; secondly, determining anchor points and optimal photoetching conditions under different light sources in the test pattern; then, under the optimal photoetching condition, respectively collecting Focal Energy Matrix (FEM) data of the layout under different light sources, and inputting parameters such as Depth of Focus (DOF) and Energy tolerance (EL); and finally, judging the process windows of the layouts under different light sources through parameters such as depth of focus (DOF), energy tolerance (EL) and the like. It can be found that the method for screening the light source merely screens the light source by collecting the focal length energy matrix (FEM) data under different light sources on the silicon wafer, since the data volume of the focal length energy matrix (FEM) is very large, it needs to consume a lot of time, manpower and machine resources,

the invention provides a light source optimization method which is used for solving the problem of light source optimization under small technical nodes and a single graph.

Disclosure of Invention

The invention aims to provide a light source optimization method to improve the light source screening efficiency.

In order to solve the technical problem, the invention provides a light source optimization method, which comprises the following steps:

generating corresponding PW OPC models by utilizing different light sources on a photoetching machine, wherein the PW OPC models are models which can simulate the critical dimension of the optical resistance on the wafer under the condition of a target process window;

performing analog simulation on the target layout of the wafer by adopting the PW OPC model, and outputting a plurality of judgment parameters;

and screening out the most friendly light source to the target layout according to all the evaluation parameters.

Optionally, in the light source optimization method, the evaluation parameter includes a process fluctuation bandwidth value, a mask error enhancement factor, an aerial image normalized logarithmic slope, and a single-point focal depth.

Optionally, in the light source optimization method, the light source includes a two-pole light source, a four-hole light source, and a six-hole light source.

Optionally, in the light source optimization method, the target layout includes a one-dimensional graph or a two-dimensional graph; or the image comprises a one-dimensional array center position graph, a one-dimensional array edge position graph or a two-dimensional graph corner position graph.

Optionally, in the light source optimization method, the step of screening out the most friendly light source to the target layout according to all the evaluation parameters includes:

judging the friendliness degree of each light source on the photoetching machine to the target layout by using each judgment parameter, and generating a judgment result after one judgment parameter judges one light source;

and selecting the light source which is judged to be the most friendly by the most number of the judging parameters from all judging results, and taking the light source as the most friendly light source for the target layout.

To achieve the above and other related objects, the present invention also provides a light source optimization apparatus, including:

a PW OPC model generation module configured to generate corresponding PW OPC models using different light sources on the lithography machine, wherein the PW OPC models are models that can simulate the critical dimension of the optical resistance on the wafer under the condition of a target process window;

the simulation module is configured to perform simulation on the target layout of the wafer by adopting the PW OPC model and output a plurality of judgment parameters;

and the judging module is configured to screen out the most friendly light source to the target layout according to all the judging parameters.

Optionally, in the light source optimization apparatus, the evaluation parameter output by the analog simulation module includes a process fluctuation bandwidth value, a mask error enhancement factor, an aerial image normalized logarithmic slope, and a single-point focal depth.

Optionally, in the light source optimization apparatus, the step of screening, by the judgment module, a light source that is most friendly to the target layout according to all the judgment parameters includes:

judging the friendliness degree of each light source on the photoetching machine to the target layout by using each judgment parameter, wherein one judgment parameter judges one light source to generate a judgment result;

and selecting the light source which is judged to be the most friendly by the most number of the judging parameters from all judging results, and taking the light source as the most friendly light source for the target layout.

In order to achieve the above objects and other related objects, the present invention further provides a lithography system, including a lithography machine having at least two light sources, a mask plate and the light source optimization device, wherein the light source optimization device is configured to select a light source that is most friendly to a target layout from all light sources on the lithography machine, and the lithography machine is configured to expose a wafer by using the mask plate as a mask and using the most friendly light source selected by the light source optimization device to form a lithography pattern on the wafer.

To achieve the above and other related objects, the present invention also provides a photolithography method including:

selecting the most friendly light source to the target layout from all light sources on a photoetching machine by adopting the light source optimization method or the light source optimization device;

and providing a mask plate for manufacturing the target layout, and exposing a wafer by using the mask plate as a mask and adopting the most friendly light source so as to form a photoetching pattern on the wafer.

In summary, the present invention provides a light source optimization method, including: firstly, different light sources are utilized to generate corresponding Process Window (PW) Optical Proximity Correction (OPC) models, secondly, the models are adopted to carry out analog simulation on a target layout, and judgment parameters are output, and finally, the light sources are screened according to the judgment parameters. Compared with the mode of collecting data on a silicon chip by adopting different light sources in the prior art, the light source optimization method does not need to collect massive Focus Exposure Matrix (FEM) data, saves development time and a large amount of manpower and machine resources, can efficiently and quickly realize the screening optimization of the light sources, improves the screening efficiency of the light sources, and can more intuitively reflect the difference between different light sources.

In addition, the invention also provides a light source optimization device, a photoetching system and a photoetching method. The light source optimization device comprises a PW OPC model generation module, an analog simulation module and a judgment module, and can screen out the most friendly light source to the target layout. The photoetching system comprises a photoetching machine with at least two light sources, a mask plate and the light source optimization device, wherein the mask plate can be used as a mask, and the light source which is most friendly to a target layout and is screened from all the light sources on the photoetching machine by the light source optimization device is adopted to expose a wafer so as to form a photoetching pattern on the wafer. The photoetching method comprises the following steps: and providing a mask plate for manufacturing the target layout, and exposing a wafer by using the mask plate as a mask and adopting a most friendly light source so as to form a photoetching pattern on the wafer. The most friendly light source is the light source which is most friendly to the target layout and is screened from all light sources on a photoetching machine by adopting the light source optimization method or the light source optimization device.

Drawings

FIG. 1 is a flow chart of a method for optimizing a light source.

Fig. 2 is a flowchart of a light source optimization method according to an embodiment of the invention.

Detailed Description

With the reduction of the technology nodes, when the size of the graph is close to the limit of the photoetching capacity, the process window becomes smaller and smaller, and it is important to select a good light source in a short time in the development stage. If the light sources are simply screened by collecting the focal length energy matrix (FEM) data under different light sources on the silicon wafer, a lot of time, manpower and machine resources are consumed.

Referring to fig. 1, a light source optimization procedure commonly employed in the industry includes: firstly, selecting a design layout and test patterns with different periods near a design rule; secondly, determining anchor points and optimal photoetching conditions under different light sources in the test pattern; then, under the optimal photoetching condition, respectively collecting focal length energy matrix (FEM) data of the layout under different light sources, and outputting judgment parameters according to the focal length energy matrix (FEM), wherein the judgment parameters can comprise depth of focus (DOF), energy tolerance (EL), photoresist morphology (PRprofile) and the like; and finally, judging the process windows of the target layouts under different light sources through depth of focus (DOF), energy tolerance (EL) and the like, thereby screening out the most friendly light source to the target layouts. The depth of focus (DOF) refers to a distance that a focal plane (focus) is allowed to move along an optical axis of a lens on the premise that an image is kept to be clear, and the larger the depth of focus (DOF) is, the larger the process window is. The tolerance of Energy (EL), also called exposure latitude (exposure), refers to the maximum deviation allowed by the exposure energy over the range of allowable variations of the line width, the greater the tolerance of Energy (EL) value, the larger the process window. If the photoresist profile (PRProfile) is in an inverted trapezoid shape, the photoresist may collapse, which reduces the exposure quality and the photolithography process quality.

The optimization method of the light source only screens the light source by collecting the data of the focal length energy matrix (FEM) under different light sources on the silicon chip, and the data volume of the focal length energy matrix (FEM) is very huge, so that the screening of the most friendly light source to the target layout needs to consume a large amount of time, manpower and machine resources.

Based on the discovery, the invention provides a light source optimization method, which screens out the most friendly light source to a layout by a method of generating a Process Window (PW) Optical Proximity Correction (OPC) model, so that massive Focus Exposure Matrix (FEM) data does not need to be collected, the screening and optimization of the light source can be efficiently and quickly realized, and the difference between different light sources can be more intuitively reflected.

To make the objects, advantages and features of the present invention more clear, the light source optimization method proposed by the embodiment of the present invention is further described in detail below with reference to fig. 2. It is to be noted that the drawings are only for the purpose of facilitating and clearly aiding the description of the embodiments of the present invention.

Based on the above research, the present embodiment provides a light source optimization method, referring to fig. 2. The light source optimization method comprises the following steps: generating corresponding PW OPC models by utilizing different light sources on a photoetching machine, wherein the PW OPC models are models which can simulate the critical dimension of the optical resistance on the wafer under the condition of a target process window; performing analog simulation on the target layout of the wafer by adopting the PW OPC model, and outputting a plurality of judgment parameters; and screening out the most friendly light source to the target layout according to all the evaluation parameters.

First, a PW OPC model is generated using different light sources on the lithography machine, where the light sources can be any lithography machine-usable light source, preferably a dipolar (Dipole) limit light source, a four-hole light source, and a six-hole light source. Because there are a large number of small-pitch one-dimensional patterns close to the photolithography limit in the layout design, in order to resolve these patterns and have a strong resolution, a corresponding dipolar (Dipole) limit light source is required, which requires the direction of the light source to be perpendicular to the direction of the one-dimensional pattern and the polarization direction of the light source to be parallel to the direction of the pattern. However, the resolution of the Dipole (Dipole) limit light source to the two-dimensional pattern is poor. In order to balance the resolutions of one-dimensional and two-dimensional patterns, the light sources need to be further adjusted and optimized, that is, four-hole light sources and six-hole light sources can be added in the light sources, and then the most friendly light sources to the target layout are screened out through a Process Window (PW) OPC model. The four-hole light source and the six-hole light source are independent four-hole or six-hole light sources which are usable by a photoetching machine formed by light source-mask optimization simulation and OPC program through changing a mask plate and a pattern type and are completely different from a dipolar (Dipole) limit light source.

And generating corresponding PW OPC models by using different light sources, and determining simulation positions of different types of graphs in the target layout. The PW OPC model is a model which is established under a target process window condition and can simulate the size of a photoresist CD on a wafer, wherein the target process window condition comprises energy information and focal depth information, the energy is preferably optimal energy of-4% to + 4%, and the focal depth is preferably: the optimal focal depth is-45 nm to +45nm, and the optimal energy and the optimal focal depth need to be determined according to the process requirements. The target layout comprises a one-dimensional graph or a two-dimensional graph, and further, the target layout can be all kinds of graphs such as a one-dimensional array center position (array center) graph, a one-dimensional array edge position (array edge) graph or a two-dimensional graph Corner position (Corner) graph.

And then, performing analog simulation on the target layout by adopting the PW OPC model, and outputting judgment parameters. The evaluation parameters include a process variation band (PV-band), a Mask Error Enhancement Factor (MEEF), a Normalized Image Log Slope (NILS), a single point Depth of focus (IDOF), and the like.

And finally, screening out the most friendly light source to the target layout according to all the judgment parameters. The method comprises the following specific steps: judging the friendliness degree of each light source on the photoetching machine to the target layout by using each judgment parameter, and generating a judgment result after one judgment parameter judges one light source; and selecting the light source which is judged to be the most friendly by the most number of the judging parameters from all judging results, and taking the light source as the most friendly light source for the target layout. The process fluctuation bandwidth value (PV-band) refers to the size variation range of the obtained graph under the condition of the target process window, and the smaller the value is, the larger the actual process window is; the Mask Error Enhancement Factor (MEEF) refers to the range of the line width change of the wafer to be exposed along with the line width change of the mask under the condition of the target process window, and the smaller the value of the MEEF is, the larger the actual process window is. The normalized logarithmic slope of aerial image (NILS) refers to the contrast of the obtained photoresist aerial image under the condition of the target process window, and the larger the value of the contrast is, the larger the actual process window is. The single point depth of focus (IDOF) refers to the depth of focus at the optimum energy condition, the larger the value, the larger the actual process window. And in the process of screening the light sources according to the evaluation parameters, for different light sources, the evaluation parameters are mutually independent. And finally, screening out the most friendly light source to the target layout by integrating the judging parameters, and realizing the optimization of the light source by the mode.

According to the method, the corresponding Process Window (PW) OPC models are generated by utilizing different light sources on the photoetching machine, then the models are adopted to carry out analog simulation on the target layout, the judgment parameters are output, and finally the light sources are screened according to all the judgment parameters.

The present embodiment further provides a light source optimization apparatus, including: a PW OPC model generation module configured to generate corresponding PW OPC models using different light sources on the lithography machine, wherein the PW OPC models are models that can simulate the critical dimension of the optical resistance on the wafer under the condition of a target process window; the simulation module is configured to perform simulation on the target layout of the wafer by adopting the PWOPC model and output a plurality of judgment parameters; and the judging module is configured to screen out the most friendly light source to the target layout according to all the judging parameters.

The light source is preferably a two-pole limit light source, a four-hole light source and a six-hole light source, and the target layout comprises a one-dimensional graph or a two-dimensional graph; or, the target process window condition includes energy information and focal depth information, the energy is preferably the optimal energy of-4% to + 4%, and the focal depth is preferably: the optimal focal depth is-45 nm to +45nm, the optimal energy and the optimal focal depth need to be specifically determined according to the process requirements, and the evaluation parameters output by the analog simulation module comprise a process fluctuation bandwidth value, a mask error enhancement factor, an aerial image normalized logarithmic slope and a single-point focal depth. The step that the judging module screens out the most friendly light source to the target layout according to all the judging parameters comprises the following steps: judging the friendliness degree of each light source on the photoetching machine to the target layout by using each judgment parameter, and generating a judgment result after one judgment parameter judges one light source; and selecting the light source which is judged to be the most friendly by the most number of the judging parameters from all judging results, and taking the light source as the most friendly light source for the target layout.

The embodiment also provides a lithography system, which comprises a lithography machine with at least two light sources, a mask plate and the light source optimization device, wherein the light source optimization device is configured to be the most friendly light source to a target layout screened from all light sources on the lithography machine, the lithography machine is configured to use the mask plate as a mask, and the most friendly light source screened by the light source optimization device is adopted to expose a wafer so as to form a lithography pattern on the wafer.

The embodiment also provides a lithography method, including: selecting the most friendly light source to the target layout from all light sources on a photoetching machine by adopting the light source optimization method or the light source optimization device; and providing a mask plate for manufacturing the target layout, and exposing a wafer by using the mask plate as a mask and adopting the most friendly light source so as to form a photoetching pattern on the wafer.

It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the invention. As used herein, the singular is intended to include the plural unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Finally, it should be noted that the above-mentioned embodiments are only preferred embodiments of the present invention, and are not intended to limit the scope of the present invention. That is, all equivalent changes and modifications made according to the content of the claims of the present invention should be within the technical scope of the present invention.