阅读说明：本技术 一种基于有限状态机的逻辑看门狗实现方法 (Logic watchdog implementation method based on finite-state machine ) 是由 唐启翔 于 2018-06-20 设计创作，主要内容包括：本发明公开了一种基于有限状态机的逻辑看门狗实现方法,包括以下步骤：单板最后一级电源1.0V上电成功,状态机由初始态转到启动态,同时启动计时器开始计数；当CPLD检测到处理器输出的WDI,且启动时间大于等于45s时,状态机由启动态转到运行态；如果启动时间达到65s还没有检测到WDI信号,则状态机由启动态转到掉电态,这时CPLD输出2s的掉电信号控制其它部分掉电,然后状态机回到初始态。本发明使用有限状态机将系统运行划分为初始态、启动态、运行态、掉电态四个阶段,可以在系统启动阶段挂死或运行阶段挂死的情况下,通过重新上下电来恢复系统运行。(The invention discloses a logic watchdog implementation method based on a finite-state machine, which comprises the following steps: the last stage of the power supply of the single board is successfully electrified at 1.0V, the state machine is switched from the initial state to the starting state, and meanwhile, a timer is started to start counting; when the CPLD detects the WDI output by the processor and the starting time is more than or equal to 45s, the state machine is switched from a starting state to a running state; if the starting time reaches 65s and no WDI signal is detected, the state machine is switched from the starting state to the power-down state, the CPLD outputs 2s of power-down signals to control other parts to be powered down, and then the state machine returns to the initial state. The invention uses the finite state machine to divide the system operation into four stages of initial state, starting state, operating state and power failure state, and can recover the system operation by powering on and powering off again under the condition that the system is hung up in the starting stage or the operating stage.)

1. A logic watchdog realizing method based on a finite state machine is characterized in that: the method comprises the following steps:

s101, a last stage power supply of a single board is powered on successfully at 1.0V, a state machine is switched from an initial state to a starting state, and a timer is started to start counting;

s102, when the CPLD detects the WDI output by the processor and the starting time is more than or equal to 45S, the state machine is switched from a starting state to a running state; if the starting time reaches 65s and no WDI signal is detected, the state machine is switched from the starting state to the power-down state, the CPLD outputs 2s power-down signals to control the power-down of other parts, and then the state machine returns to the initial state;

s103, if the loss or other abnormity of the WDI signal is detected in the running state, the state machine is switched from the running state to the power-down state; similarly, if a 1.0V power supply anomaly is detected in the run state, the state machine will transition from the run state to the initial state.

2. The logic watchdog implementation method based on the finite-state machine according to claim 1, wherein: the method for detecting WDI output by the processor comprises the following steps: setting a high-level width register counter _ width _ H and a low-level width register counter _ width _ L, resetting the high-level width register counter _ width _ H when the WDI signal is at a low level, and adding 1 to the high-level width register counter _ width _ H when the WDI signal is at a high level; similarly, when the WDI signal is at the high level, the low level width register counter _ width _ L is cleared, and when the WDI signal is at the low level, the low level width register counter _ width _ L is incremented by 1; when any one of the high-level width register counter _ width _ H and the low-level width register counter _ width _ L is equal to 580, WDI _ dec _ result = 0 is output, and WDI _ dec _ result = 1 is output otherwise.

3. The logic watchdog implementation method based on the finite-state machine according to claim 1, wherein: the CPLD is an electromechanical management module which is independently powered and is used for acquiring and controlling the state of other parts of the single board.

Technical Field

The invention relates to the relevant technical field of embedded systems, in particular to a logic watchdog implementation method based on a finite-state machine.

Background

The embedded system works in a complex environment, and a condition that a program is hung up or flown due to external interference exists, so that a 'watchdog' for monitoring the running state of the program is a necessary function of a product. The watchdog function has the following implementation modes: firstly, an external watchdog chip is adopted, such as a Meixin MAX 706; secondly, a watchdog timer integrated in the embedded processor is adopted; thirdly, a watchdog function circuit is built through a hardware description language by using an FPGA or a CPLD. Under the condition that a product has a logic chip, the third scheme can improve the system integration level and reduce the hardware cost.

As shown in fig. 1, taking a MAX706RESA chip as an example, the 8 th pin of the chip is WDI, that is, a feeding dog signal is input, as long as the pin changes in high and low levels within 1.6S, the internal watchdog timer of the chip will be cleared, and if the level change interval of the WDI pin exceeds 1.6S, the 8 th pin/WDO of the chip will output low levels until the WDI pin changes in level again. Therefore, when the GPIO of the processor is used for outputting the WDI dog feeding signal, if the program is hung up, the dog feeding signal can not be overturned according to the rule or even stopped, and at the moment, the/WDO outputs low level to trigger the processor to reset.

Disclosure of Invention

The present invention aims to provide a logic watchdog implementation method based on a finite-state machine, so as to solve the problems proposed in the above background art.

In order to achieve the purpose, the invention provides the following technical scheme:

a logic watchdog realizing method based on a finite-state machine comprises the following steps:

s101, a last stage power supply of a single board is powered on successfully at 1.0V, a state machine is switched from an initial state to a starting state, and a timer is started to start counting;

s102, when the CPLD detects the WDI output by the processor and the starting time is more than or equal to 45S, the state machine is switched from a starting state to a running state; if the starting time reaches 65s and no WDI signal is detected, the state machine is switched from the starting state to the power-down state, the CPLD outputs 2s power-down signals to control the power-down of other parts, and then the state machine returns to the initial state;

s103, if the loss or other abnormity of the WDI signal is detected in the running state, the state machine is switched from the running state to the power-down state; similarly, if a 1.0V power supply anomaly is detected in the run state, the state machine will transition from the run state to the initial state.

As a further scheme of the invention: the method for detecting the WDI signal output by the processor comprises the following steps: setting a high-level width register counter _ width _ H and a low-level width register counter _ width _ L, resetting the high-level width register counter _ width _ H when the WDI signal is at a low level, and adding 1 to the high-level width register counter _ width _ H when the WDI signal is at a high level; similarly, when the WDI signal is at the high level, the low level width register counter _ width _ L is cleared, and when the WDI signal is at the low level, the low level width register counter _ width _ L is incremented by 1; when any one of the high-level width register counter _ width _ H and the low-level width register counter _ width _ L is equal to 580, WDI _ dec _ result = 0 is output, and WDI _ dec _ result = 1 is output otherwise.

As a further scheme of the invention: the CPLD is an electromechanical management module which is independently powered and is used for acquiring and controlling the state of other parts of the single board.

Compared with the prior art, the invention has the beneficial effects that: the invention uses the finite state machine to divide the system operation into four stages of initial state, starting state, operating state and power failure state, and can recover the system operation by powering on and powering off again under the condition that the system is hung up in the starting stage or the operating stage is hung up; the method for realizing the watchdog function by utilizing the state machine is simple, the logic is clear, the state conversion time can be adjusted according to the loading time of an actual system, the pulse width detection criterion of the dog feeding signal and the output time of the reset signal can be programmed, and the application is more flexible than that of a hardware watchdog chip.

Drawings

FIG. 1 is a timing diagram of a conventional chip watchdog overflow logic.

FIG. 2 is a flow chart of the present invention.

FIG. 3 is a logic diagram of the state machine of the present invention.

Fig. 4 is a simulation result diagram according to the first embodiment of the present invention.

Fig. 5 is a simulation result diagram of the second embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 2 and 3, a logic watchdog implementation method based on a finite-state machine includes the following steps:

s101, a last stage power supply of a single board is successfully electrified at 1.0V, a state machine is switched from an initial state (Idle) to a Start state (Start), and a timer is started to Start counting;

s102, when the CPLD detects the WDI output by the processor and the starting time is more than or equal to 45S, the state machine is changed from a starting state (Start) to a running state (Run); if the starting time reaches 65S and no WDI signal is detected, the state machine is switched from a starting state (Start) to a power-down state (off), the CPLD outputs a power-down signal of 2S to control the power-down of other parts, and then the state machine returns to an initial state (Idle);

s103, if WDI signal loss or other abnormity is detected in the running state (Run), the state machine is switched from the running state (Run) to a power-down state (off); similarly, if a 1.0V power supply anomaly is detected in the Run state (Run), the state machine will transition from the Run state (Run) to the initial state (Idle).

Through the setting of the state machine, the system operation can be recovered by powering on and powering off again under the condition that the system is dead in the starting stage or dead in the operating stage.

The method for detecting the WDI signal output by the processor comprises the following steps: setting a high-level width register counter _ width _ H and a low-level width register counter _ width _ L, resetting the high-level width register counter _ width _ H when the WDI signal is at a low level, and adding 1 to the counter _ width _ H when the WDI signal is at a high level; similarly, when the WDI signal is at a high level, the counter _ width _ L is cleared, and when the WDI signal is at a low level, the counter _ width _ L is added with 1; WDI detection result WDI _ dec _ result = 0 is output when either counter _ width _ H or counter _ width _ L is equal to 580, i.e., high or low level width reaches 580ms, instead of convention 500ms, and WDI _ dec _ result = 1 is output otherwise.