阅读说明：本技术 用于延长电源转换器的保护期间的控制器及其操作方法 (Controller for extending protection period of power converter and operation method thereof ) 是由 邹明璋 叶之朴 卢宏儒 于 2019-04-10 设计创作，主要内容包括：本发明公开了一种用于延长电源转换器的保护期间的控制器及其操作方法。所述控制器包含一延迟电路。所述延迟电路耦接于所述控制器的一供电电压引脚,其中当所述电源转换器进入一保护模式时,所述延迟电路启用,通过所述供电电压引脚接收一供电电压,且根据所述供电电压延长对应所述保护模式的保护期间。因此,因为本发明可延长所述保护期间,所以相较于现有技术,本发明可使所述电源转换器的功率开关在对应所述保护模式的恢复期间所产生的热有效散去。另外,因为所述控制器是直接通过一供电电压引脚控制所述供电电压,所以所述控制器不须额外的引脚。(The invention discloses a controller for prolonging the protection period of a power converter and an operation method thereof. The controller includes a delay circuit. The delay circuit is coupled to a supply voltage pin of the controller, wherein when the power converter enters a protection mode, the delay circuit is enabled, receives a supply voltage through the supply voltage pin, and extends a protection period corresponding to the protection mode according to the supply voltage. Therefore, the invention can prolong the protection period, so compared with the prior art, the invention can effectively dissipate the heat generated by the power switch of the power converter during the recovery period corresponding to the protection mode. In addition, because the controller controls the supply voltage directly through a supply voltage pin, the controller does not require additional pins.)

1. A controller for extending a protection period of a power converter, comprising:

the delay circuit is enabled when the power converter enters a protection mode, receives a supply voltage through the supply voltage pin, and extends a protection period corresponding to the protection mode according to the supply voltage.

2. The controller of claim 1, wherein said delay circuit comprises:

a first current source coupled to the supply voltage pin for generating a first discharge current according to a protection signal corresponding to the protection mode and the supply voltage when the power converter enters the protection mode;

a delay unit for generating a delay enable signal according to the protection signal and a detection voltage related to a primary side of the power converter, wherein the delay enable signal corresponds to a predetermined delay time; and

a second current source coupled to the delay and the supply voltage pin for generating a second discharge current according to the delay enable signal;

the power supply voltage is determined by the first discharge current, a capacitance of the primary side of the power converter, and a charge current related to an input terminal of the primary side of the power converter, or by the first discharge current, the second discharge current, the capacitance, and the charge current.

3. The controller of claim 2, wherein: the controller turns off the delay circuit when the supply voltage is below a low-voltage lockout turn-off voltage.

4. The controller of claim 3, wherein: when the delay circuit is turned off and the supply voltage is greater than a low-voltage lock-on voltage, the controller generates a gate control signal to the power switch on the primary side of the power converter again.

5. The controller of claim 1, wherein said delay circuit comprises:

a current source, which is used for being started according to a protection signal corresponding to the protection mode, generating a first discharge current when the power supply voltage is smaller than a lower limit value, and generating a second discharge current when the power supply voltage is larger than an upper limit value; and

the counter is used for counting the times that the power supply voltage is smaller than the lower limit value;

wherein the supply voltage is determined by the first discharge current, a capacitance of the primary side of the power converter, a charging current related to an input terminal of the primary side of the power converter, or the second discharge current, the capacitance, and the charging current

When the number of times is equal to a preset number of times, the counter enables the current source to generate the second discharging current, the first discharging current is smaller than the charging current, and the second discharging current is larger than the charging current.

6. The controller of claim 5, wherein: the controller turns off the delay circuit when the supply voltage is below a low-voltage lockout turn-off voltage.

7. The controller of claim 6, wherein: when the delay circuit is turned off and the supply voltage is greater than a low-voltage lock-on voltage, the controller generates a gate control signal to the power switch on the primary side of the power converter again.

8. The controller according to claim 2 or 5, wherein: the second discharge current is adjusted according to an output voltage of a secondary side of the power converter.

9. The controller of claim 1, wherein: the protection mode corresponds to an output short-circuit protection or an over-current protection.

10. The controller of claim 1, wherein: the protection mode corresponds to an over-voltage protection, an over-load protection, an over-temperature protection, or an under-voltage protection.

11. The controller of claim 1, wherein: the power converter is a flyback power converter.

12. A method of operating a controller for extending a protection period of a power converter, wherein the controller includes a delay circuit and the delay circuit includes a first current source, a delay and a second current source, comprising:

the power converter enters a protection mode;

the first current source generates a first discharge current according to a protection signal corresponding to the protection mode and a supply voltage, and the first discharge current, a capacitance on a primary side of the power converter, and a charging current related to an input terminal on the primary side of the power converter determine the supply voltage;

the delayer generates a delay enable signal according to the protection signal and a detection voltage related to a primary side of the power converter, wherein the delay enable signal corresponds to a preset delay time; and

the second current source generates a second discharging current according to the delay enable signal, and the second discharging current and the first discharging current, the capacitor, and the charging current determine the supply voltage.

13. The method of claim 12, further comprising:

the controller turns off the delay circuit when the supply voltage is below a low-voltage lockout turn-off voltage; and

when the delay circuit is turned off and the supply voltage is greater than a low-voltage lock-on voltage, the controller generates a gate control signal to the power switch on the primary side of the power converter again.

14. The method of operation of claim 12, wherein: the second discharge current is adjusted according to an output voltage of a secondary side of the power converter.

15. A method of operating a controller for extending a protection period of a power converter, wherein the controller includes a delay circuit and the delay circuit includes a current source and a counter, comprising:

the power converter enters a protection mode;

the current source is enabled according to a protection signal corresponding to the protection mode;

when a supply voltage is smaller than a lower limit value, the current source generates a first discharge current, and the first discharge current, a capacitor on the primary side of the power converter and a charging current related to an input end on the primary side of the power converter determine the supply voltage;

when the power supply voltage is greater than an upper limit value, the current source generates a second discharge current, and the second discharge current, the capacitor and the charging current determine the power supply voltage; and

when the number of times that the power supply voltage is smaller than the lower limit value is counted by the counter is equal to a preset number of times, the counter enables the current source to generate the second discharge current;

wherein the first discharge current is less than the charge current and the second discharge current is greater than the charge current.

16. The method of claim 15, further comprising:

the controller turns off the delay circuit when the supply voltage is below a low-voltage lockout turn-off voltage; and

when the delay circuit is turned off and the supply voltage is greater than a low-voltage lock-on voltage, the controller generates a gate control signal to the power switch on the primary side of the power converter again.

17. The method of operation of claim 15, wherein: the second discharge current is adjusted according to an output voltage of a secondary side of the power converter.

Technical Field

The present invention relates to a controller applied to a power converter and an operating method thereof, and more particularly, to a controller for extending a protection period of a power converter and an operating method thereof.

Background

In the prior art, when a power converter is applied to a television and enters a protection mode (where the protection mode corresponds to an output short-circuit protection (OSCP) or an over-current protection (OCP)), since the television cannot be shut down arbitrarily, a gate signal generation circuit applied in a controller of the power converter generates a burst mode (burst mode) -like gate control signal to a power switch on a primary side of the power converter, that is, during an enabling period of the gate control signal (corresponding to a recovery period of the protection mode), the operation of the power switch still generates heat. If the heat generated by the power switch during the recovery period cannot be effectively dissipated during the off period of the gate control signal (corresponding to the protection period of the protection mode), the heat generated by the power switch during the recovery period may damage components in the television. Therefore, how to effectively dissipate the heat generated by the power switch during the recovery period becomes an important issue.

Disclosure of Invention

An embodiment of the invention discloses a controller for prolonging a protection period of a power converter. The controller includes a delay circuit. The delay circuit is coupled to a supply voltage pin of the controller, wherein when the power converter enters a protection mode, the delay circuit is enabled, receives a supply voltage through the supply voltage pin, and extends a protection period corresponding to the protection mode according to the supply voltage.

Another embodiment of the present invention discloses an operation method of a controller for extending a protection period of a power converter, wherein the controller includes a delay circuit and the delay circuit includes a first current source, a delay and a second current source. The operation method comprises the steps that the power converter enters a protection mode; the first current source generates a first discharge current according to a protection signal corresponding to the protection mode and a supply voltage, and the first discharge current, a capacitance on a primary side of the power converter, and a charging current related to an input terminal on the primary side of the power converter determine the supply voltage; the delayer generates a delay enable signal according to the protection signal and a detection voltage related to a primary side of the power converter, wherein the delay enable signal corresponds to a preset delay time; and the second current source generates a second discharging current according to the delay enable signal, and the second discharging current and the first discharging current, the capacitor and the charging current determine the power supply voltage.

Another embodiment of the present invention discloses an operation method of a controller for extending a protection period of a power converter, wherein the controller includes a delay circuit and the delay circuit includes a current source and a counter. The operation method comprises the steps that the power converter enters a protection mode; the current source is enabled according to a protection signal corresponding to the protection mode; when a supply voltage is smaller than a lower limit value, the current source generates a first discharge current, and the first discharge current, a capacitor on the primary side of the power converter and a charging current related to an input end on the primary side of the power converter determine the supply voltage; when the power supply voltage is greater than an upper limit value, the current source generates a second discharge current, and the second discharge current, the capacitor and the charging current determine the power supply voltage; when the number of times that the power supply voltage is smaller than the lower limit value is counted by the counter is equal to a preset number of times, the counter enables the current source to generate the second discharging current; wherein the first discharge current is less than the charge current and the second discharge current is greater than the charge current.

The invention discloses a controller for prolonging the protection period of a power converter and an operation method thereof. The controller and the operation method are that after the power converter enters a protection mode, a delay circuit is used for prolonging a protection period corresponding to the protection mode according to a power supply voltage. Therefore, the invention can prolong the protection period, so compared with the prior art, the invention can effectively dissipate the heat generated by the power switch of the power converter during the recovery period corresponding to the protection mode. In addition, because the controller controls the supply voltage directly through a supply voltage pin, the controller does not require additional pins.

Drawings

Fig. 1 is a schematic diagram of a controller for extending a protection period of a power converter according to a first embodiment of the present invention.

Fig. 2 is a timing diagram illustrating the supply voltage of the controller and the gate control signal generated by the controller after the power converter enters the protection mode.

Fig. 3 is a diagram illustrating the coupling relationship of the first current source, the delay and the second current source.

Fig. 4 is a schematic diagram illustrating the operation timing of the delayer.

Fig. 5 is a schematic diagram of a controller for extending the protection period of a power converter according to a second embodiment of the present invention.

Fig. 6 is a timing diagram illustrating the supply voltage of the controller and the gate control signal generated by the controller after the power converter enters the protection mode.

Fig. 7 is a flowchart of an operation method of a controller for extending the protection period of a power converter according to a third embodiment of the present invention.

Fig. 8 is a flowchart of an operation method of the controller for extending the protection period of the power converter according to the fourth embodiment of the present invention.

Wherein the reference numerals are as follows:

100 power converter

102 power switch

103 resistance

104 capacitor

200. 500 controller

202 delay circuit

204 supply voltage pin

206. 208, 210 pins

2022 first current source

2024 delay device

2026 second current source

20242 comparator

20244 OR gate

20246 NAND gate

20248 pulse generator

502 delay circuit

5022 Current Source

5024 counter

CLK clock signal

D0-DN +1, DF flip-flop

DES delayed enable signal

EN reset signal

GND ground terminal

GCS Gate control Signal

IC charging current

IPRI primary side current

IOUT output current

IDIS1 first discharge current

IDIS2 second discharge current

Lower limit of LLI

OCP protection signal

PRI Primary side

PUL pulse signal

R reset pin

SEC Secondary side

T1-T7, T41, T42, T43 time

TR recovery period

TP guard period

UVLOON low voltage lock-on voltage

UVLOOFF low voltage lockout turn-off voltage

Upper limit of ULI

VCS detection voltage

VCC supply voltage

VREF reference voltage

VCOMP comparison signal

700, 712, 800, 818 steps

Detailed Description

Referring to fig. 1, fig. 1 is a schematic diagram of a controller 200 for extending a protection period of a power converter 100 according to a first embodiment of the present invention, wherein the power converter 100 is a flyback power converter (flyback converter), and in order to simplify fig. 1, only components of the power converter 100 and the controller 200 related to the present invention are shown in fig. 1. As shown in fig. 1, the controller 200 includes a delay circuit 202, and the delay circuit 202 includes a first current source 2022, a delay 2024 and a second current source 2026, wherein the first current source 2022 is coupled to a supply voltage pin 204, the second current source 2026 is coupled to the delay 2024 and the supply voltage pin 204, and the controller 200 receives a supply voltage VCC through the supply voltage pin 204. As shown in fig. 1, a protection circuit (not shown in the controller 200 of fig. 1) in the controller 200 may determine whether to enable the power converter 100 to enter a protection mode according to the output current IOUT of the secondary side SEC of the power converter 100, where the protection mode corresponds to an output short-circuit protection or an over-current protection. In addition, the method for the protection circuit to determine whether to enter the protection mode according to the output current IOUT is well known to those skilled in the art of the present invention, and is not described herein again.

Referring to fig. 2, fig. 2 is a timing diagram illustrating the supply voltage VCC of the controller 200 and a gate control signal GCS generated by the controller 200 after the power converter 100 enters the protection mode. As shown in fig. 2, at a time T1, the supply voltage VCC is greater than a low voltage lock out ("undervoltage lock out") turn-on voltage UVLOON, so a gate signal generating circuit (not shown in the controller 200 of fig. 1) in the controller 200 generates a gate control signal GCS to the power switch 102 of the primary side PRI of the power converter 100 between a time T2 and a time T3, wherein the gate control signal GCS is a pulse width modulation ("PWM") signal, the gate control signal GCS is transmitted to the power switch 102 through a pin 206 of the controller 200, and a time interval between the time T2 and the time T3 is a recovery period TR of the power converter 100 corresponding to the protection mode. As shown in fig. 2, at time T3, the gate signal generating circuit stops generating the gate control signal GCS to the power switch 102 according to the detection voltage VCS (shown in fig. 1) of the primary PRI of the power converter 100 and a reference voltage VREF, and the protection circuit generates a protection signal OCP to the first current source 2022 and the delay 2024, wherein the detection voltage VCS is determined by the primary current IPRI flowing through the primary PRI of the power converter 100 and a resistor 103, and the controller 200 receives the detection voltage VCS through a pin 208. Therefore, because the protection circuit generates the protection signal OCP to the first current source 2022, the first current source 2022 is enabled and starts to generate a first discharging current IDIS1 to discharge a capacitor 104 (as shown in fig. 1) according to the supply voltage VCC, wherein the first discharging current IDIS1 varies with the variation of the supply voltage VCC, and the first discharging current IDIS1 flows to a ground GND through the pin 210 of the controller 200. As shown in fig. 1 and 2, during the recovery period TR, since only one charging current IC charges the capacitor 104, the supply voltage VCC is determined by the charging current IC and the capacitor 104, so that the supply voltage VCC maintains a first stable state. After the time T3, the first discharging current IDIS1 starts to discharge the capacitor 104, so the power supply voltage VCC is determined by the first discharging current IDIS1, the charging current IC and the capacitor 104, wherein in an embodiment of the present invention, the first discharging current IDIS1 is greater than the charging current IC at the time T3, so the power supply voltage VCC starts to gradually decrease until a time T4 (since the first discharging current IDIS1 changes with the change of the power supply voltage VCC, at the time T4, the first discharging current IDIS1 is equal to the charging current IC, so the power supply voltage VCC maintains a second stable state after the time T4 until a time T5).

As shown in fig. 2, at time T5, the delay 2024 generates a delay enable signal DES to the second current source 2026 according to the protection signal OCP and the detection voltage VCS, so that the second current source 2026 is enabled and starts to generate a second discharging current IDIS2 to discharge the capacitor 104, wherein the delay enable signal DES corresponds to a predetermined delay time, a time interval between time T3 and time T5 is a protection period TP of the power converter 100 corresponding to the protection mode, and the second discharging current IDIS2 flows to the ground GND through the pin 210 of the controller 200. As shown in fig. 2, after time T5, the second discharging current IDIS2 starts to discharge the capacitor 104 (wherein the first discharging current IDIS1 still continues to discharge the capacitor 104, so the supply voltage VCC is determined by the first discharging current IDIS1, the second discharging current IDIS2, the charging current IC and the capacitor 104, resulting in the supply voltage VCC decreasing from the second stable state until less than a low voltage locking off voltage UVLOOFF (time T6 shown in fig. 2) after time T5. as shown in fig. 2, at time T6, because the supply voltage VCC is lower than the low voltage locking off voltage UVLOOFF, the controller 200 turns off the delay circuit 2024, resulting in the supply voltage VCC gradually increasing until greater than the low voltage locking on voltage UVLOON (time T7 shown in fig. 2.) as shown in fig. 2, after time T7, the controller 200 will repeat the above-mentioned operation principle for time T1-time T7 until the power converter 100 leaves the protection mode, in another embodiment of the present invention, the second discharge current IDIS2 can be adjusted according to the output voltage of the secondary side SEC of the power converter 100 (wherein the output voltage is not shown in fig. 1), for example, when the output voltage is high, the second discharge current IDIS2 is low, and when the output voltage is low, the second discharge current IDIS2 is high.

Referring to fig. 3 and 4, fig. 3 is a schematic diagram illustrating a coupling relationship among the first current source 2022, the delay device 2024 and the second current source 2026, and fig. 4 is a schematic diagram illustrating an operation timing of the delay device 2024. As shown in fig. 3, the delay 2024 includes a comparator 20242, an or gate 20244, a nand gate 20246, a pulse generator 20248, and flip-flops D0-DN +1, DF. As shown in fig. 2 and 4, between a time T41 (corresponding to the time T2 in fig. 2) and a time T42 (corresponding to the time T3 in fig. 2), since the gate signal generating circuit generates the gate control signal GCS to the power switch 102, the detection voltage VCS gradually increases from zero until it is equal to the reference voltage VREF at the time T3. Therefore, the comparison signal VCOMP generated by the comparator 20242 is high between time T41 and time T42. In addition, between time T41 and time T42, the protection circuit has not yet generated the protection signal OCP, so the protection signal OCP is low. In addition, as shown in fig. 4, after the time T42, the comparison signal VCOMP, the protection signal OCP, and the pulse signal PUL generated by the pulse generator 20248 make the reset pin R of the flip-flop D0-DN +1 low, so the delay 2024 can delay a clock signal CLK by using the flip-flop D0-DN +1 and generate the delay enable signal DES to the second current source 2026 at a time T43 (corresponding to the time T5 in fig. 2), which causes the second current source 2026 to be enabled and start generating the second discharge current IDIS2 to discharge the capacitor 104, wherein as shown in fig. 4, the series connection of the flip-flops D0-DN +1 is used to determine the predetermined delay time, that is, the delay 2024 can use the flip-flop D0-DN +1 to change the length of the predetermined delay time. The pulse generator 20248 generates the pulse signal PUL according to the rising edge of the protection signal OCP. As shown in fig. 4, after time T42, the reset signal EN of the flip-flop DF is set low to maintain the protection signal OCP at high level.

In an embodiment of the present invention, when the power converter 100 is applied to a television and enters the protection mode, the controller 200 operates according to the timing sequence of fig. 2 because the television cannot be arbitrarily turned off. Although the gate signal generating circuit still generates the gate control signal GCS to the power switch 102 during the recovery period TR as shown in fig. 2, the controller 200 can effectively dissipate the heat generated by the power switch 102 of the power converter 100 during the recovery period TR to protect the components in the television because the delay 2024 can extend the predetermined delay time (i.e., extend the protection period TP during which the gate signal generating circuit stops generating the gate control signal GCS to the power switch 102) by using the flip-flop D0-DN + 1. In addition, because the controller 200 utilizes the delay circuit 202 to directly control the supply voltage VCC via the supply voltage pin 204, the controller 200 is also a 6-pin integrated circuit, i.e., the present invention can eliminate the need for additional pins for the controller 200.

Referring to fig. 5 and 6, fig. 5 is a schematic diagram of a controller 500 for extending a protection period of a power converter 100 according to a second embodiment of the present invention, and fig. 6 is a timing diagram illustrating a supply voltage VCC of the controller 500 and a gate control signal GCS generated by the controller 500 after the power converter 100 enters the protection mode, wherein in order to simplify fig. 5, only components of the power converter 100 and the controller 500 related to the present invention are shown in fig. 5. As shown in fig. 5, the difference between the controller 500 and the controller 200 is that the controller 500 includes a delay circuit 502, and the delay circuit 502 includes a current source 5022 and a counter 5024, wherein the current source 5022 is coupled to the supply voltage pin 204, the counter 5024 is coupled to the current source 5022, and the controller 500 receives the supply voltage VCC through the supply voltage pin 204. In addition, as shown in fig. 6, the difference between the supply voltage VCC of the controller 500 and the supply voltage VCC of the controller 200 is in the operation principle corresponding to the protection time TP, which is described in detail as follows.

As shown in fig. 6, after the power converter 100 enters the protection mode, at time T3, the gate signal generating circuit (not shown in the controller 500 of fig. 5) in the controller 500 may stop generating the gate control signal GCS to the power switch 102 according to the detection voltage VCS (shown in fig. 5) of the primary PRI of the power converter 100 and the reference voltage VREF, and the protection circuit (not shown in the controller 500 of fig. 5) in the controller 500 generates the protection signal OCP to the current source 5022. Accordingly, because the protection circuit generates the protection signal OCP to the current source 5022, the current source 5022 is enabled and begins to generate a second discharge current IDIS2 to discharge the capacitor 104 (shown in fig. 5). After the time T3, the supply voltage VCC is determined by the second discharging current IDIS2, the charging current IC and the capacitor 104 because the second discharging current IDIS2 starts to discharge the capacitor 104, but in an embodiment of the present invention, the second discharging current IDIS2 is greater than the charging current IC, so the supply voltage VCC starts to gradually decrease until the supply voltage VCC is less than a lower limit LLI (time T4 shown in fig. 6). As shown in fig. 6, at time T4, since the supply voltage VCC is less than the lower limit LLI, the current source 5022 generates a first discharging current IDIS 1. At this time, the supply voltage VCC is determined by the first discharging current IDIS1, the charging current IC and the capacitor 104, but in an embodiment of the present invention, the first discharging current IDIS1 is smaller than the charging current IC, so the supply voltage VCC starts to gradually increase until the supply voltage VCC is greater than an upper limit ULI (time T5 shown in fig. 6). Thus, the delay circuit 502 can repeat the operation principle from the time T4 to the time T5 until the counter 5024 counts the number of times that the supply voltage VCC is smaller than the lower limit LLI (in another embodiment of the present invention, the counter 5024 counts the number of times that the supply voltage VCC is greater than the upper limit ULI) is equal to a predetermined number of times (corresponding to the time T6 shown in fig. 6). At time T6, because the number of times is equal to the predetermined number of times, the current source 5022 will only generate the second discharge current IDIS2, which causes the supply voltage VCC to start to decrease after time T6 until it is less than the low-voltage lockout voltage UVLOOFF (time T7 shown in fig. 6). Therefore, although the gate signal generating circuit still generates the gate control signal GCS to the power switch 102 during the recovery period TR as shown in fig. 6, the controller 500 can effectively dissipate the heat generated by the power switch 102 of the power converter 100 during the recovery period TR to protect the components in the television because the delay circuit 502 can extend the predetermined delay time (i.e., extend the protection period TP) by using the operation principle as shown in fig. 6. In addition, the remaining operation principle of the controller 500 is the same as that of the controller 200, and is not described in detail herein.

Referring to fig. 1, 2 and 7, fig. 7 is a flowchart illustrating a method for extending a protection period of a power converter according to a third embodiment of the present invention. The operation method of fig. 7 is explained by using the power converter 100 and the synchronous rectifier 200 of fig. 1, and the detailed steps are as follows:

step 700: starting;

step 702: the power converter 100 enters the protection mode;

step 704: the first current source 2022 generates a first discharging current IDIS1 according to the corresponding protection signal OCP and the supply voltage VCC;

step 706: the delayer 2024 generates a delay enable signal DES according to the protection signal OCP and the detection voltage VCS;

step 708: the second current source 2026 generates a second discharge current IDIS2 according to the delay enable signal DES;

step 710: when the supply voltage VCC is lower than the low-voltage lockout off voltage uvloff, the controller 200 turns off the delay circuit 202;

step 712: when the delay circuit 202 is turned off and the supply voltage VCC is greater than the low-voltage lock-on voltage uvlon, the controller 200 generates the gate control signal GCS again to the power switch 102 of the primary-side PRI of the power converter 100, and then jumps back to step 704.

In step 702, as shown in fig. 1, a protection circuit (not shown in the controller 200 of fig. 1) in the controller 200 may determine whether to enable the power converter 100 to enter the protection mode according to the output current IOUT of the secondary side SEC of the power converter 100. After the power converter 100 enters the protection mode, at time T1, the supply voltage VCC is greater than the low-voltage lock-on voltage uvlon, so the gate signal generating circuit in the controller 200 generates the gate control signal GCS to the power switch 102 between time T2 and time T3, wherein the time interval between time T2 and time T3 is the recovery period TR of the power converter 100 corresponding to the protection mode. As shown in fig. 1 and 2, during the recovery period TR, the supply voltage VCC maintains the first stable state because only the charging current IC charges the capacitor 104. In step 704, as shown in fig. 2, at time T3, the gate signal generating circuit may stop generating the gate control signal GCS to the power switch 102 according to the detection voltage VCS (shown in fig. 1) of the primary side PRI of the power converter 100 and the reference voltage VREF, and the protection circuit generates the protection signal OCP to the first current source 2022 and the delay 2024. Therefore, the first current source 2022 is enabled and starts to generate the first discharging current IDIS1 to discharge the capacitor 104 according to the supply voltage VCC, wherein the first discharging current IDIS1 varies with the variation of the supply voltage VCC. After time T3, the first discharging current IDIS1 starts to discharge the capacitor 104, so the power supply voltage VCC is determined by the first discharging current IDIS1, the charging current IC and the capacitor 104, wherein because the first discharging current IDIS1 is greater than the charging current IC at time T3, the power supply voltage VCC starts to gradually decrease until time T4 (because the first discharging current IDIS1 changes with the change of the power supply voltage VCC, at time T4, the first discharging current IDIS1 is equal to the charging current IC, which causes the power supply voltage VCC to maintain the second stable state after time T4 until time T5). In step 706, as shown in fig. 2, at time T5, the delay 2024 may generate a delay enable signal DES to the second current source 2026 according to the protection signal OCP and the detection voltage VCS, so that the second current source 2026 is enabled and starts to generate a second discharging current IDIS2 to discharge the capacitor 104, wherein the delay enable signal DES corresponds to the predetermined delay time, and a time interval between time T3 and time T5 is a protection period TP of the power converter 100 corresponding to the protection mode. In step 708, as shown in fig. 2, after time T5, second discharge current IDIS2 begins to discharge capacitor 104 (where first discharge current IDIS1 also continues to discharge capacitor 104, so supply voltage VCC is determined by first discharge current IDIS1, second discharge current IDIS2, charging current IC and capacitor 104, resulting in supply voltage VCC decreasing from the second stable state until less than low voltage lock off voltage UVLOOFF after time T5 (time T6 shown in fig. 2.) in step 710, as shown in fig. 2, at time T6, because supply voltage VCC is less than low voltage lock off voltage UVLOOFF, controller 200 turns off delay circuit 2024, resulting in supply voltage VCC gradually increasing until greater than low voltage lock on voltage uvolon (time T7 shown in fig. 2.) in step 712, as shown in fig. 2, at time T7, supply voltage VCC is greater than low voltage lock on voltage uvolon, the gate signal generating circuit (not shown in the controller 200 of fig. 1) in the controller 200 generates the gate control signal GCS again to the power switch 102 of the primary side PRI of the power converter 100.

Referring to fig. 1, 5, 6 and 8, fig. 8 is a flowchart illustrating a method for extending a protection period of a power converter according to a fourth embodiment of the present invention. The method of operation of fig. 8 is illustrated using the power converter 100 and the synchronous rectifier 500 of fig. 5, with the detailed steps as follows:

step 800: starting;

step 802: the power converter 100 enters the protection mode;

step 804: the current source 5022 is enabled according to the protection signal OCP corresponding to the protection mode;

step 806: whether the supply voltage VCC is less than the lower limit value LLI; if so, go to step 808; if not, go to step 806 again;

step 808: the current source 5022 generates a first discharging current IDIS1, and the counter 5024 counts the number of times that the supply voltage VCC is less than the lower limit value LLI;

step 810: whether the supply voltage VCC is greater than the upper limit ULI; if so, go to step 812; if not, go to step 810 again;

step 812: current source 5022 generates a second discharge current IDIS 2;

step 814: the counter 5024 counts whether the number of times that the power supply voltage VCC is smaller than the lower limit LLI is equal to the preset number of times; if so, go to step 816; if not, go to step 806;

step 816: when the supply voltage VCC is lower than the low-voltage lockout turn-off voltage uvloff, the controller 500 turns off the delay circuit 502;

step 818: when the delay circuit 502 is turned off and the supply voltage VCC is greater than the low-voltage lock-on voltage uvlon, the controller 500 generates the gate control signal GCS again to the power switch 102 of the primary-side PRI of the power converter 100, and the process goes back to step 804.

The difference between the fourth embodiment of fig. 8 and the third embodiment of fig. 7 is that in step 806, at time T3, the current source 5022 is enabled and starts to generate the second discharging current IDIS2 to discharge the capacitor 104 (as shown in fig. 5), so the supply voltage VCC starts to gradually decrease until the supply voltage VCC is lower than the lower limit value LLI (as shown at time T4 in fig. 6); in step 808, as shown in fig. 6, at time T4, since the current source 5022 generates the first discharging current IDIS1, the supply voltage VCC will start to gradually increase until the supply voltage VCC is greater than the upper limit ULI (time T5 shown in fig. 6); in step 812, since the current source 5022 generates the second discharging current IDIS2, the supply voltage VCC will start to gradually decrease until the supply voltage VCC is less than the lower limit LLI; in step 814, the delay circuit 502 may repeat the operation principle from time T4 to time T5 until the number of times when the counter 5024 counts the number of times that the supply voltage VCC is smaller than the lower limit value LLI (in another embodiment of the present invention, the number of times that the counter 5024 counts the number of times that the supply voltage VCC is greater than the upper limit value ULI) is equal to the predetermined number of times (corresponding to time T6 shown in fig. 6); at time T6, because the number of times is equal to the predetermined number of times, the current source 5022 will only generate the second discharge current IDIS2, which causes the supply voltage VCC to start to decrease after time T6 until it is less than the low-voltage lockout voltage UVLOOFF (time T7 shown in fig. 6). In addition, the remaining operation principle of the fourth embodiment of fig. 8 is the same as that of the third embodiment of fig. 7, and is not described again here.

In summary, in the controller and the operation method disclosed in the present invention, after the power converter enters the protection mode, the delay circuit is used to extend the protection period corresponding to the protection mode according to the supply voltage. In addition, the content of the above embodiments of the present invention is exemplified by the protection signal applied to the overcurrent protection and the output short-circuit protection. In fact, the protection signal of the present invention can also be applied to various aspects of protection mechanisms or protection modes, such as Over Voltage Protection (OVP), Over Load Protection (OLP), Over Temperature Protection (OTP), under voltage protection (Brown out protection), and so on. Therefore, the invention can prolong the protection period, so compared with the prior art, the invention can effectively dissipate the heat generated by the power switch of the power converter during the recovery period corresponding to the protection mode. In addition, because the controller controls the supply voltage directly through the supply voltage pin, the controller does not require an additional pin.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.