阅读说明：本技术 与经调节的di/dt和/或dv/dt组合地驱动功率开关的系统和方法 (System and method for driving a power switch in combination with a regulated DI/DT and/or DV/DT ) 是由 K.诺尔林 J.格勒格 A.施赖贝尔 B.维希特 于 2019-06-18 设计创作，主要内容包括：公开了与经调节的DI/DT和/或DV/DT组合地驱动功率开关的系统和方法。根据实施例,一种驱动开关晶体管的方法包括：利用栅极驱动信号驱动开关晶体管；测量开关晶体管的负载路径电压的导数和开关晶体管的负载路径电流的导数中的至少一个；测量栅极驱动信号的导数；基于参考信号、所测量的栅极驱动信号的导数、以及所测量的开关晶体管的负载路径电压的导数或所测量的开关晶体管的负载路径电流的导数中的至少一个来形成误差信号；以及形成栅极驱动信号,其中形成栅极驱动信号包括使用动态控制器处理误差信号。(Systems and methods of driving a power switch in combination with a regulated DI/DT and/or DV/DT are disclosed. According to an embodiment, a method of driving a switching transistor includes: driving a switching transistor with a gate drive signal; measuring at least one of a derivative of a load path voltage of the switching transistor and a derivative of a load path current of the switching transistor; measuring a derivative of the gate drive signal; forming an error signal based on the reference signal, the measured derivative of the gate drive signal, and at least one of the measured derivative of the load path voltage of the switching transistor or the measured derivative of the load path current of the switching transistor; and forming a gate drive signal, wherein forming the gate drive signal includes processing the error signal using a dynamic controller.)

1. A gate drive circuit for controlling a gate controlled component, the gate drive circuit comprising:

a dynamic controller configured to receive an input reference signal and to control a gate voltage of a gate controlled component via an output terminal of the gate drive circuit;

at least one component feedback circuit for a dynamic controller, the at least one component feedback circuit configured to provide feedback to the dynamic controller from at least one of: a time derivative of a load path voltage of the gate controlled component or a time derivative of a load path current of the gate controlled component; and

a gate drive feedback circuit for a dynamic controller, the gate drive feedback circuit configured to provide feedback from a time derivative of a voltage at an output terminal of the gate drive circuit.

2. The gate drive circuit of claim 1, further comprising a buffer circuit having an input coupled to the output of the dynamic controller and an output coupled to the output terminal of the gate drive circuit.

3. The gate drive circuit of claim 2, wherein the buffer circuit and the dynamic controller are disposed on a single semiconductor substrate.

4. The gate drive circuit of claim 1, wherein the dynamic controller comprises a proportional-integral (PI) controller.

5. The gate drive circuit of claim 1, wherein:

when the gate drive circuit switches on the gate controlled component, the gate drive feedback circuit has a first gain of a first polarity; and

the gate drive feedback circuit has a second gain of a second polarity when the gate driver circuit turns off the gate controlled component, wherein the first polarity and the second polarity are configured to provide negative feedback.

6. The gate drive circuit of claim 5, wherein the gate drive feedback circuit is further configured to rectify feedback from a time derivative of the voltage at the output terminal of the gate drive circuit.

7. The gate drive circuit of claim 5, wherein:

the gate drive feedback circuit is configured to limit a positive slew rate of a voltage at an output terminal of the gate drive circuit when the gate drive circuit turns on the gate controlled component; and

the gate drive feedback circuit is configured to limit a negative slew rate of a voltage at the output terminal of the gate drive circuit when the gate drive circuit turns off the gate controlled component.

8. A circuit, comprising:

a gate driver circuit having an output coupled to a gate drive terminal configured to be coupled to a gate of the switching transistor;

a dynamic controller having an output coupled to an input of the gate driver circuit;

a summing circuit having an output coupled to an input of the dynamic controller and a first input configured to receive a reference signal;

at least one feedback circuit coupled between the voltage measurement terminal and a second input of the summing circuit, the at least one feedback circuit configured to provide a signal to the second input of the summing circuit that is proportional to at least one of a derivative of a load path voltage of the switching transistor and a derivative of a load path current of the switching transistor; and

an anti-windup circuit coupled between the output of the gate driver circuit and a third input of the summing circuit, the anti-windup circuit configured to provide a signal to the third input of the summing circuit that is proportional to a derivative of the output voltage of the gate driver circuit.

9. The circuit of claim 8, further comprising a switching transistor.

10. The circuit of claim 8, wherein the at least one feedback circuit comprises:

a first feedback circuit configured to provide a first signal proportional to a derivative of the load path voltage to a second input of the summing circuit; and

a second feedback circuit configured to provide a second signal proportional to a derivative of the load path current of the switching transistor to a fourth input of the summing circuit.

11. The circuit of claim 10, further comprising a clipping circuit coupled between the output of the second feedback circuit and the fourth input of the summing circuit.

12. The circuit of claim 8, wherein the anti-windup circuit is configured to:

applying a first gain to a signal proportional to a derivative of an output voltage of the gate driver circuit when the gate driver circuit turns on the switching transistor; and

when the gate driver circuit turns off the switching transistor, a second gain is applied to a signal proportional to a derivative of an output voltage of the gate driver circuit.

13. The circuit of claim 12, wherein the anti-windup circuit comprises:

a first current mirror having an output coupled to a third input of the summing circuit; and

a first capacitor coupled between the output of the gate driver circuit and the input of the first current mirror.

14. The circuit of claim 13, wherein the anti-windup circuit further comprises:

a second current mirror having an output coupled to a third input of the summing circuit; and

a second capacitor coupled between the output of the gate driver circuit and the input of the second current mirror.

15. The circuit of claim 14, wherein the first current mirror has a different mirror ratio than the second current mirror.

16. The circuit of claim 12, wherein the first gain comprises a first polarity and the second gain comprises a second polarity opposite the first polarity, wherein the first polarity and the second polarity are configured to provide negative feedback.

17. The circuit of claim 8, further comprising an external booster stage having an input coupled to the gate drive terminal and an output configured to be coupled to the gate of the switching transistor.

18. A method of driving a switching transistor, the method comprising:

driving a switching transistor with a gate drive signal;

measuring at least one of a derivative of a load path voltage of the switching transistor and a derivative of a load path current of the switching transistor;

measuring a derivative of the gate drive signal;

forming an error signal based on the reference signal, the measured derivative of the gate drive signal, and at least one of the measured derivative of the load path voltage of the switching transistor or the measured derivative of the load path current of the switching transistor; and

forming the gate drive signal, wherein forming the gate drive signal includes processing the error signal using a dynamic controller.

19. The method of claim 18, wherein forming a gate drive signal further comprises:

generating a control signal using a dynamic controller;

driving an input of a gate driving circuit with a control signal; and

a gate drive signal is generated using a gate drive circuit.

20. The method of claim 18, wherein driving the switching transistor with the gate drive signal comprises driving a booster stage with the gate drive signal, wherein an output of the booster stage is coupled to a gate of the switching transistor.

21. The method of claim 18, wherein the dynamic controller is a proportional-integral (PI) controller.

22. The method of claim 18, further comprising:

applying a first gain to a derivative of the measured gate drive signal before forming an error signal when the switching transistor is turned on; and

a second gain is applied to the derivative of the measured gate drive signal before forming an error signal when the switching transistor is turned off.

23. The method of claim 22, further comprising:

providing only a derivative of the measured gate drive signal of a first polarity before forming the error signal when the switching transistor is turned on; and

only the derivative of the measured gate drive signal of a second polarity, which is opposite to the first polarity, is provided before the error signal is formed when the switching transistor is switched off.

24. The method of claim 23, wherein:

the first polarity represents a positive slew rate of the gate drive signal; and

the second polarity represents a negative slew rate of the gate drive signal.

25. The method of claim 22, wherein the first gain comprises a first polarity and the second gain comprises a second polarity opposite the first polarity.

26. The method of claim 18, further comprising receiving a switch control signal and generating a reference signal based on the received switch control signal.

27. The method of claim 26, wherein the switch control signal comprises a pulse width modulated signal.

Technical Field

The present invention relates generally to systems and methods for driving power switches in combination with regulated di/dt and/or dv/dt.

Background

General driver circuits for power semiconductors such as Insulated Gate Bipolar Transistors (IGBTs), Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), junction gate field effect transistors (JFETs) and High Electron Mobility Transistors (HEMTs) may be adapted to control the switching slope of the power semiconductors. The switching slope is at least one of: a voltage change over time (dv/dt) which occurs when the voltage on the load path of the power semiconductor rises or falls; and a current high change (di/dt) over time that occurs when the current through the load path of the power semiconductor rises or falls. In general, the slope is not adjusted to a particular value or range but is only limited, which may be sufficient for many applications. However, limiting the slope may mean, for example, limiting dv/dt to a maximum voltage change value or limiting di/dt to a maximum current change value. Limiting di/dt is particularly important in the case of a decreasing current, since an excessive (negative) di/dt with respect to parasitic inductances may generate the following voltages: this voltage may exceed the maximum voltage rating of the respective power semiconductor.

In the case where the signal for driving the power semiconductor is under closed loop control, further problems arise with regard to overshoot that may occur when the drive voltage of the power semiconductor is below the turn-on threshold of the semiconductor. In this operating region, the feedback path including the output of the respective semiconductor device is essentially disabled, and at least part of the control loop for regulating the drive voltage of the power semiconductor may operate in an open loop state. Such open loop behavior may cause voltage errors and overshoot that are corrected by the loop once it is fully closed.

Disclosure of Invention

According to an embodiment, a gate driving circuit for controlling a gate controlled component includes: a dynamic controller configured to receive an input reference signal and to control a gate voltage of the gate controlled component via an output terminal of the gate drive circuit; at least one component feedback circuit for a dynamic controller, the at least one component feedback circuit configured to provide feedback to the dynamic controller from at least one of: a time derivative of a load path voltage of the gate controlled component or a time derivative of a load path current of the gate controlled component; and a gate drive feedback circuit for the dynamic controller, the gate drive feedback circuit configured to provide feedback from a time derivative of the voltage at the output terminal of the gate drive circuit.

According to another embodiment, a circuit includes: a gate driver circuit having an output coupled to a gate drive terminal configured to be coupled to a gate of the switching transistor; a dynamic controller having an output coupled to an input of the gate driver circuit; a summing circuit having an output coupled to an input of the dynamic controller and a first input configured to receive a reference signal; at least one feedback circuit coupled between the voltage measurement terminal and a second input of the summing circuit, the at least one feedback circuit configured to provide a signal to the second input of the summing circuit that is proportional to at least one of a derivative of a load path voltage of the switching transistor and a derivative of a load path current of the switching transistor; and an anti-windup circuit coupled between an output of the gate driver circuit and a third input of the summing circuit, the anti-windup circuit configured to provide a signal to the third input of the summing circuit that is proportional to a derivative of an output voltage of the gate driver circuit.

According to a further embodiment, a method of driving a switching transistor includes: driving a switching transistor with a gate drive signal; measuring at least one of a derivative of a load path voltage of the switching transistor and a derivative of a load path current of the switching transistor; measuring a derivative of the gate drive signal; forming an error signal based on the reference signal, the measured derivative of the gate drive signal, and at least one of the measured derivative of the load path voltage of the switching transistor or the measured derivative of the load path current of the switching transistor; and forming a gate drive signal, wherein forming the gate drive signal includes processing the error signal using a dynamic controller.

Drawings

For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a schematic diagram illustrating an exemplary driver circuit without an external output boost circuit and with an integrated circuit having analog and digital dv/dt feedback paths;

FIG. 2 is a schematic diagram illustrating an exemplary driver circuit having an external output boost circuit and having an integrated circuit with analog and digital dv/dt feedback paths;

FIG. 3 is a schematic diagram illustrating an exemplary driver circuit without an external output boost circuit and with an integrated circuit having analog and digital dv/dt and di/dt feedback paths;

FIG. 4 is a schematic diagram illustrating an exemplary driver circuit having an external output boost circuit and having an integrated circuit with analog and digital dv/dt and di/dt feedback paths;

FIG. 5 is a schematic diagram illustrating an exemplary driver circuit with analog and digital feedback paths;

FIG. 6 is a schematic diagram illustrating an exemplary driver circuit with modified analog and digital feedback paths;

FIG. 7 is a schematic diagram illustrating an exemplary drive circuit with further modified analog and digital feedback paths;

8A-8E illustrate line and waveform diagrams depicting the performance of an embodiment gate drive system that provides closed loop slew rate control of the output voltage of a gate driver circuit;

FIGS. 9A and 9B illustrate schematic diagrams of an embodiment gate drive circuit;

fig. 10A to 10C illustrate waveform diagrams showing the performance of the gate driving circuit of the embodiment;

11A and 11B illustrate feedback circuits that may be used to implement an embodiment gate driver circuit; and

fig. 12A and 12B illustrate an embodiment gate driver integrated circuit.

Detailed Description

Fig. 1 to 7 generally describe the regulation of changes in voltage (dv/dt regulation) and changes in current (di/dt regulation) of a power switch as described in german patent application DE 102016111449.9 filed on 6.22.2016. A detailed description of an embodiment of the present invention is made with reference to fig. 8A to 12B. In an embodiment of the invention, the power switch driver circuit is configured to adjust a derivative (dI) of the load path current using a feedback control circuit_cDt), derivative of load path voltage (dV)_CEDt) and derivative of the gate drive voltage (dV)_out，DriverDt). In some embodiments, three feedback paths are used to couple dI_c/dt、dV_CEDt and dV_out，DriverThe/dt feedback is provided to a single dynamic controller, such as a proportional-integral (PI) controller. By removing dI_cDt and dV_CEProviding d in addition to/dt_{Vout，Driver}/dt, overshoot of the gate drive voltage may be reduced and/or eliminated. This overshoot may also be referred to as a "windup" effect. These embodiments are described with respect to fig. 8A to 8E, 9A to 9B, 10A to 10C, 11A to 11B, and 12A to 12B.

In simple general driver circuits, which mainly limit the voltage overshoot during turn-off, the feedback signal is applied directly to the control terminals of the semiconductor devices, e.g. their gates. This direct feedback configuration is undesirable because the feedback signal requires a certain amount of current to generate an effective voltage change at the gate when acting against a low gate resistor (less than 1 ohm to a few ohms). In other common driver circuits, the feedback currents are low because they act on the input of the power amplifier stage which directly drives the gate of the semiconductor device. The input impedance at the input of the power amplifier stage, where the feedback current has to generate a voltage, reaches several orders of magnitude higher than the impedance at the control terminal (e.g. gate resistor) of the semiconductor device. Such driver circuits typically use discrete transistors connected as current amplifiers, for example in an emitter follower type configuration. For high current amplification, two or three amplifier stages may be required, for example in a darlington configuration. In order to evaluate the voltage change dv/dt and/or the current change di/dt over time, standard passive discrete components are usually used.

Fig. 1 shows an exemplary driver circuit for driving a controllable semiconductor device 106, such as an Insulated Gate Bipolar Transistor (IGBT) or any other suitable semiconductor device. The emitter of the semiconductor device 106 may be connected to ground 108 via a parasitic inductance 107 and its collector connected to a load (not shown). The semiconductor device 106 may also be referred to as a gate controlled component or a switching transistor. The load path of the semiconductor device 106 is the path between its emitter and collector and may include a parasitic inductance 107. The driver circuit receives an external control signal, such as a control input signal 100, and comprises a signal pre-processing stage 101 and a subsequent signal post-processing stage 102, such as an internal output stage. At least the signal pre-processing stage 101 and the post-processing stage 102 may be integrated in an integrated circuit device 103. Integrated circuit device 103 may receive control input signal 100 and at least two feedback signals from, for example: an analog feedback signal 104 from an external analog dv/dt monitoring stage 105; and a digital feedback signal 114 from the external analog-to-digital converter 112, the external analog-to-digital converter 112 converting the voltage into a binary word forming the digital feedback signal 114. The analog-to-digital converter 112 is connected upstream of an internal dv/dt monitoring stage 115, the internal dv/dt monitoring stage 115 being arranged in the integrated circuit device 103.

The feedback signal 104 (e.g., a voltage and/or a current) may be combined (e.g., summed) in the integrated circuit device 103 with an internal control signal 111 (e.g., a voltage and/or a current), the internal control signal 111 coming from the internal pre-processing stage 101 at an input of the post-processing stage 102. The monitoring stage 105 performs a simulated calculation of the voltage change by time dv/dt from the voltage on the load path of the semiconductor device 106, e.g. the voltage at the collector of the semiconductor device 106. The monitoring stage 115 performs a digital calculation of the voltage change by time dv/dt from the digital feedback signal 114, the digital feedback signal 114 being representative of the voltage over the load path of the semiconductor device 106. The monitoring stage 115 controls the pre-processing stage 101, the pre-processing stage 101 outputting an analog signal (e.g. a voltage and/or a current) dependent on the input signal 100 and the digital feedback signal 114.

Further, the external dv/dt monitoring stage 105 and the internal dv/dt monitoring stage 115 evaluate voltage changes over time of the voltage on the load path of the semiconductor device 106 to be controlled. The voltage evaluation may include at least one of: monitoring voltage changes, gating feedback signals, detecting a rise and fall of a voltage, amplifying or attenuating at least one feedback signal, and the like. The output stage 102 provides a control output signal 116 to regulate the voltage change dv/dt at the control path (gate) of the semiconductor device 106, the control output signal 116 being, for example, a controlled voltage and/or current dependent on the control input signal 100 and the feedback signals 104 and 114.

Alternatively, the integrated circuit device 103 may be connected to the gate of the semiconductor device 106 via a resistor 109. Still alternatively, the signal pre-processing stage 101 and the post-processing stage 102 may be connected via a resistor 110. The resistor 109 may have as small a resistance as possible, just enough to suppress oscillations in the control path (gate) of the semiconductor device 106 and thus stabilize the entire circuit. The current into the control path (gate) of the semiconductor device 106 is indirectly controlled by feedback into an output stage forming part of the signal post-processing stage 102 of the integrated circuit device 103 in this example. Resistor 110 allows the feedback current (which forms signal 104) to generate a voltage difference in opposition to the voltage provided by pre-processing stage 101, thus adjusting the input of the output stage of signal post-processing stage 102 to provide slope control for semiconductor device 106.

The signal pre-processing stage 101 may perform at least one of level shifting, electrical isolation and signal shaping processing. The signal post-processing stage 102 is in this example a voltage-to-voltage amplifier supplying any current required to achieve the output voltage, but could alternatively be a current-to-voltage amplifier, a current-to-current amplifier, or a voltage-to-current amplifier as shown, with the circuitry upstream and downstream of the respective amplifier being adapted accordingly. Integrated circuit device 103 may be referenced to ground 108, where ground 108 is one end of parasitic inductance 107, such as an outer end of parasitic inductance 107. As can be seen, feedback signals 104 and 114, which are representative of the voltage change dv/dt, act against resistor 110.

Referring to fig. 2, the driver circuit shown in fig. 1 may be modified in that an integrated circuit device 200 is used instead of the integrated circuit device 103, wherein the resistor 110 is replaced by a digitally controllable current source 201. As can be seen, the feedback signal 104 (current) acts against the current source 201, the current source 201 ideally providing an infinite DC resistance. The current source 201 is controlled by a digital dv/dt monitoring stage 208, the digital dv/dt monitoring stage 208 digitally evaluating the voltage change over time of the voltage across the load path of the semiconductor device 106. The analog monitoring stage 207 performs an analog calculation of the voltage change dv/dt over time from the voltage on the load path of the semiconductor device 106. A digital-to-analog converter 112 connected between the analog monitoring stage 207 and the digital dv/dt monitoring stage 208 converts the resulting analog dv/dt signal from the analog monitoring stage 207 into a digital dv/dt signal for the digital dv/dt monitoring stage 208. The current source 201 may further be adjustable to provide a specific current for different semiconductor devices 106.

Further, an external power amplifier 202 may be inserted between the post-processing stage 102 and the resistor 109. In this example, the power amplifier 202 includes one amplifier stage formed of a complementary transistor pair (e.g., with a pnp bipolar transistor 203 and an npn bipolar transistor 204) connected in a complementary emitter-follower configuration between a negative voltage supply line 205 and a positive voltage supply line 206. For example, the post-processing stage 102 may have a current drive capability of up to 1 or 2 amps, and the current amplifier 202 may increase this capability by a factor of 10 to 50, so that the resistor 109 may be reduced in the circuit shown in fig. 2. The post-processing stage 102 and/or the current amplifier 202 may alternatively have a class a or class a/B amplifier configuration in order to increase the speed at which the transition from positive to negative current is performed. Alternatively or additionally, the post-processing stage 102 and/or the power amplifier 202 may have more than one amplifier stage to achieve very low parasitic driver inductance. The internal dv/dt monitoring stage 115 is replaced by a digital monitoring stage 208, the digital monitoring stage 208 digitally processing the digital input signal and providing a digital output signal.

By providing access to the input of the internal output stage of the integrated circuit device, the current provided by the feedback stage may be further reduced (to tens of mA) due to smaller parasitic capacitances and the integrated circuit may provide increased speed and flexibility. At the same time, it may reduce the number of cascaded external output stages required. The output stage may typically supply a maximum current of 0.5A to 2A or in some cases up to 6A. Still further, the feedback path needs to feed less current, requiring a smaller feedback capacitor (small extra capacitance on the high voltage switch node), making the overall circuit more efficient in terms of power consumption and size. Amplifying the current through one or more external stages may provide sufficient current to drive very large IGBT devices, power semiconductor modules, and the like. Instead of driving the input of the internal power stage by means of a controllable voltage source and a resistor, it can be driven by means of a controllable current source capable of supplying a positive current and a negative current. This allows for a dv/dt (and/or di/dt) adjustment that is more linear (if the dv/dt feedback capacitance is linear) and not dependent on the load.

As shown in fig. 3, the driver circuit shown in fig. 2 may be modified in that instead of the integrated circuit device 200 an integrated circuit device 300 is used, wherein the current source 201 is omitted and the feedback processing and superposition stage 301 is connected between the pre-processing stage 101 and the post-processing stage 102. Digital dv/dt monitoring stage 207 digitally processes a digital input signal, e.g., a binary signal representing the voltage across the load path of semiconductor device 106, and provides a digital output signal, e.g., a binary signal representing the derivative of the voltage across the load path of semiconductor device 106. Further, at least one other external feedback stage, such as an external analog di/dt monitoring stage 302 and/or an external digital di/dt monitoring stage 303 is connected to the load path of the semiconductor device 106 via an analog-to-digital converter 304. The feedback processing and superposition stage 301 receives signals from the dv/dt monitoring stages 105 and 207, the signal pre-processing stage 101 and additionally from the analog di/dt monitoring stage 302 and the digital di/dt monitoring stage 303. The digital di/dt monitoring stage 303 digitally processes a digital input signal, such as a binary signal representing the current through the semiconductor device 106 load path, and provides a digital output signal, such as a binary signal representing the derivative of the current through the semiconductor device 106 load path.

The driver circuit shown in fig. 3 may be modified as shown in fig. 4 in that a power amplifier 400 is inserted between the post-processing stage 102 and the resistor 109. In this example, the power amplifier 400 includes one amplifier stage formed of a complementary transistor pair (e.g., with a pnp bipolar transistor 401 and an npn bipolar transistor 402) connected in a complementary emitter-follower configuration between a negative voltage supply line 403 and a positive voltage supply line 404. Alternatively, the power amplifier 400 may have more than one amplifier stage to achieve very low parasitic driver inductance and/or may have a class a or class a/B amplifier structure in order to increase the speed at which the transition from positive to negative current is performed. Further, digital dv/dt monitoring stage 207 is replaced by digital dv/dt monitoring stage 405 and digital di/dt monitoring stage 303 is replaced by digital di/dt monitoring stage 406. The dv/dt monitoring stage 405 and the di/dt monitoring stage 406 digitally process a digital input signal and provide a digital (binary) output signal.

Referring to fig. 5, another exemplary driver circuit includes an integrated circuit device 500 having a low voltage circuit portion and a higher voltage circuit portion electrically isolated from the low voltage circuit portion. The low voltage circuit portion includes an under-voltage lockout (UVLO) block 501 that receives a (positive) supply voltage VCC of the integrated circuit device 500₁And a first ground GND₁The integrated circuit device 500 is connected to the first ground GND₁For reference. Under-voltage lockout block 501 is an electronic circuit block that is used to supply powerVoltage VCC₁The power for the integrated circuit device 500 is disabled and/or turned off if it falls below the operating value. For example, in integrated circuit device 500, undervoltage lockout block 501 may monitor supply voltage VCC₁And if the supply voltage VCC₁Falling below a certain threshold turns off the circuit, thus protecting the integrated circuit device 500 and, if possible, also protecting the semiconductor device and/or the load associated with the integrated circuit device 500. The low-voltage circuit portion of the integrated circuit device 500 may further include a logic block 502 that receives an input (control) signal IN (e.g., for switch control) and an enable signal EN (e.g., for enabling or disabling, for example, the logic block 502, the integrated circuit device 500, or the entire driver circuit).

The logic block 502 may also provide a digital input/output interface for exchanging digital data DIO, such as specific control data, status data, service data, etc., with other units (not shown). Still further, the logic block 502 may be clocked with a clock signal provided by a clock signal generator 503 and may be connected to an electrically isolated bidirectional signal coupler 504, the electrically isolated bidirectional signal coupler 504 may provide isolation on an inductive (as shown), capacitive, optical, or any other suitable basis. Optionally, an additional signal coupler 505 (e.g., a unidirectional coupler) may be coupled in signal but electrically isolated from the low voltage circuit portion and the higher voltage circuit portion.

In the higher voltage circuit part, the signal coupler 504 and the signal coupler 505 (if present) are connected to a control block 506, which control block 506 may be a logic block or a software block implemented with a processor or a combination of both. Control block 506 receives a clock signal from clock signal generator 507 and a signal from undervoltage lockout block 508 for the higher voltage circuit portion. The control block 506 exchanges digital data with a central signal processing block 509, the central signal processing block 509 may provide for load path voltage/current slope post-processing, adjustment and adaptation. For example, the central signal processing block 509 may be adapted or programmed to implement a digital loop controller includingOne is at least: a proportional control mechanism (P); an integral control mechanism (I); a differential control mechanism (D); or a combination thereof such as, for example, a PI or PID control mechanism. Further, the control block 506 sends an on/off signal to the central signal processing block 509 and the memory 510, a sampling control signal to the two analog-to-digital conversion blocks 511 and 512, and another on/off signal and slope configuration data to the level shift block 513. The analog-to-digital conversion blocks 511 and 512 send data to the memory 510. The analog-to-digital conversion block 511 receives the second ground GND₂A voltage sense signal VSD (e.g., voltage or current) for reference, and an analog-to-digital conversion block 512 receives a signal at a second ground GND₂A current sense signal IS (e.g., voltage or current) that IS a reference.

The level shift block 513 sends control data to the adaptive driver block 514, and the adaptive driver block 514 may comprise a series connection of a (negative) supply voltage VEE₂And (positive) supply voltage VCC₂In between two digitally controllable current sources 515 and 516, with a node 517 between the two current sources 515 and 516. Supply voltage VEE₂And VCC₂May be monitored by the under-voltage lock-out block 508. Each of current sources 515 and 516 is controlled by digital data provided by level shift block 513. The driver output stage 518 is connected to a node 517, to a line carrying a voltage sense signal (e.g., voltage or current), and to the output of a transconductance amplifier block 519, the non-inverting input of which 519 is connected to a second ground GND₂And its inverting input IS connected to a line receiving a current sense signal IS (e.g. a voltage on an inductance corresponding to a change in the current to be measured).

The external wiring of integrated circuit device 500 includes two capacitors 520 and 521 that couple the collector line of semiconductor device 106 to the line carrying voltage sense signal VSD and the line carrying voltage sense signal VSA, respectively. Two capacitors 520 and 521 are used to derive dv/dt from the voltage on the load path. Second ground GND₂Is established by the node between the emitter of the semiconductor device 106 and one end of the parasitic inductance 107. The current sensing signal IS IS in the parasitic inductance107 at the other end. The inductance 107 serves to differentiate di/dt from the current obtained through the load path and to convert the current into a corresponding voltage to be measured. The gate of the semiconductor device 106 is connected to the output stage 518 via a resistor 522. Supply voltage VEE₂And VCC₂May be provided by a bipolar voltage source 523, the ground of the bipolar voltage source 523 being connected to the second ground GND₂. Optionally, it can also be supplied with the supply voltage VEE₂And VCC₂Is connected between the output stage 518 and the resistor 522. In the exemplary driver circuit shown in fig. 5, the blocks 501-509, 513 may form a pre-processing stage, the blocks 510-512, 519 form a feedback processing and superposition stage, and the blocks 515-518 form a signal post-processing stage.

By adding external feedback capacitances (e.g., capacitors 520 and 521) and providing a power stage (e.g., output stage 518) that buffers the current source driver (e.g., driver block 514), dv/dt feedback and/or di/dt feedback require much lower peak currents on the current source driver. In this way, the current source driver can be designed with lower power components, allowing the current source to be more accurate and faster in changing its current value. Additionally, the current source driver may be constructed as a current output digital-to-analog converter that can be digitally programmed to vary dv/dt and/or di/dt. Additional external digital period regulation loops may be added to further control dv/dt and/or di/dt, as shown in fig. 5. The programming of dv/dt and di/dt can be independently varied without changing the dv/dt or di/dt analog feedback network. The digital loop can track changes in the load path voltage and load path current to change the digital to analog converter output current at the correct time when a transition occurs between dv/dt and di/dt. In general, the analog feedback path is faster (fewer delays caused by signal processing and/or higher critical frequencies) but provides less accuracy and flexibility. In contrast, the digital feedback path is slower (more delay times due to signal processing and/or lower critical frequencies) but provides greater accuracy and flexibility.

The driver circuit shown in fig. 5 is an example of how an integrated driver with high voltage level offset and analog and digital dv/dt and di/dt feedback paths can be implemented. The di/dt feedback path (e.g., corresponding to signal IS) senses the voltage at the emitter inductance (e.g., parasitic inductance 107), injects/sinks a corresponding (e.g., proportional) current to/from a summing node (e.g., node 517) that originates from the current source pre-driver stage (e.g., transconductance amplifier block 519) and the reference current of the dv/dt analog feedback capacitor (e.g., capacitor 521). The summing node controls the input of a unity gain amplifier (only one internal stage, such as output stage 518, or in combination with an external cascade stage, such as current amplifier 524), which in turn drives the gate voltage of an external semiconductor device (e.g., semiconductor device 106). The dv/dt digital feedback path may be implemented by way of an analog-to-digital converter (e.g., analog-to-digital converter block 511) that samples the current flowing through a dv/dt digital feedback capacitor (e.g., capacitor 520). The di/dt digital feedback path is implemented by way of an analog-to-digital converter (e.g., analog-to-digital converter block 512) that samples voltage changes across the emitter inductance (e.g., parasitic inductance 107) that are indicative of current changes through the emitter inductance.

Fig. 6 shows the driver circuit described above with respect to fig. 5 with some modifications and alternative implementations. The two digitally controllable current sources 515 and 516 are connected to each other by a diode series connection 600 of one or more diodes, e.g. four diodes, thereby forming a node 601 between the current source 515 and one end of the diode series connection 600 and a node 602 between the current source 516 and the other end of the diode series connection 600. Each digitally controllable current source 515, 516 is connected in parallel with a constant current source 603 and 604, respectively. The line carrying the voltage sense signal VSA IS connected to node 601 and the line carrying the current sense signal IS connected to node 602 through resistor 605 and diode 606 (instead of transconductance amplifier block 519).

The output stage 518 shown in FIG. 5 is a class A/B amplifierA class a/B amplifier stage comprising: an n-channel type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) 607 having its gate connected to node 601 and its drain connected to a supply voltage VCC₂(ii) a And comprises a mosfet 608 of the p-channel type, whose gate is connected to the node 602 and whose drain is connected to the supply voltage VEE₂. The sources of the transistors 607 and 608 are connected to each other via another diode series connection circuit 609 having at least one diode (e.g., two diodes). Further, the n-channel type MOSFET 610 is connected to the second ground GND via its gate₂And is connected via its drain to a line carrying the voltage sense signal VSA. The source of transistor 610 IS connected to the line carrying current sense signal IS through linearization resistor 611. Still further, if desired, resistor 612 may be connected between the line carrying voltage sense signal VSD and second ground GND₂And a voltage divider comprising two resistors 613 and 614 connected in series IS connected between the second ground GND2 and the line carrying the current sense signal IS to reduce the voltage swing at the respective analog to digital converter input.

The input of the analog-to-digital converter block 512 IS now connected to the node between the resistors 613 and 614 (rather than directly to the line carrying the current sense signal IS). Alternatively, the external resistor 615 may be connected in parallel to the resistor 612. The current amplifier 524 may be connected in this example by an n-channel type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) 616 having its gate connected to the source of transistor 607 and its drain connected to the supply voltage VCC₂) And a metal oxide semiconductor field effect transistor 617 of the p-channel type (whose gate is connected to the source of the transistor 608 and whose drain is connected to the supply voltage VEE)₂) To be implemented. The sources of transistors 607 and 608 are connected to each other and to resistor 522.

In the driver circuit of fig. 6, the unity gain buffer stage (output stage 518 in fig. 5) is replaced by two cascaded class a/B amplifier stages (transistors 607, 608, 616, 617 and diode series connection 609 in fig. 6) and two bias current sources (constant current sources 603 and 604 in fig. 6). The analog dv/dt feedback path remains unchanged. The analog di/dt feedback path is replaced by two separate feedback paths for turning on (transistor 610 and resistor 611) and turning off (resistor 605 and diode 606 in fig. 6).

In the driver circuit discussed above in relation to fig. 6, the resistor 605 and the diode 606 may be replaced by the n-channel type mosfet 700, the resistor 701, the p-channel type mosfet 702-704 and the current source 705. As shown in FIG. 7, the transistor 700 may be connected via its gate to the line carrying the current sensing signal IS and via its source to the second ground GND through a linearization resistor 701₂Providing voltage to current conversion. The transistor 702 is connected to the supply voltage line VEE via its drain₂Connected via their gates to the drains of transistors 700 and 704 and connected via their sources to the gates of transistors 703 and 704. The current source 705 is connected to the supply voltage line VCC₂And the gates of transistors 703 and 704. The sources of transistors 703 and 704 are also connected to the supply voltage line VCC₂. The drain of transistor 703 is connected to node 602. Transistors 702 to 704 connected to current source 705 form a current mirror circuit that inverts the turn-off di/dt feedback current from transistor 700. The speed of the current mirror with transistors 703 and 704 is increased by adding transistor 702, which transistor 702 acts as a source follower. To boost the current mirror speed in both directions, a current source 705 has been added. Further, a diode 706 is interposed between the line carrying the voltage sense signal VSA and the drain of the transistor 610.

The driver circuit shown in fig. 7 also allows for GND at ground₂And supply voltage VEE₂Not operating simultaneously, so that the gate driver can also be supplied with a bipolar power supply. Still further, turning off the di/dt feedback does not directly feed current to the summing junction by making the feedback load dependent on, for example, the load condition of the semiconductor device 106 and/or its miller platform's resistorIn the dots. For example, if the voltage change dv/dt is fed back directly from the collector of the semiconductor device 106 through the capacitor (capacitor 520) to the summing node, the feedback current through the feedback capacitor (capacitor 520) will depend on the voltage change dv/dt at the collector of the semiconductor device 106 when the gate voltage of the semiconductor device 106 is at the miller plateau. However, if the current change di/dt is fed back directly through a resistor (e.g., resistor 605 in fig. 6), the current change di/dt will become a voltage difference between the di/dt induced voltage that depends on the inductance (parasitic inductance 107) and the actual voltage level of the gate (or input of the buffer stage) of the semiconductor device 106.

In the driver circuit shown in fig. 7, the semiconductor device 106 is driven with a bipolar power supply and a load-independent di/dt feedback. For turning on di/dt, when the summing node (including the gate of transistor 607) is pulled below the second ground GND₂When the simple diode (diode 706) is set to be in reverse bias. The transistor 610, which is connected as a source follower via the resistor 611, automatically produces a transition from positive to negative current regulation. The current summing node (comprising the gate of transistor 607) -with dV/dt through capacitor 521 and di/dt across inductance 107-automatically transitions from dV/dt regulation to di/dt regulation. To make the feedback at turn off independent of the load, the transconductance amplifier may be configured to measure the voltage in a differential manner across the parasitic inductance 107 and then inject a high side current into the summing node 602 that is independent of the summing node voltage. When the semiconductor device 106 is turned off, a similar concept as for the turn-on voltage change di/dt feedback may be implemented to generate a current proportional to the voltage across the parasitic inductance 107. However, the current has the wrong polarity. To obtain the correct polarity of the current, a high side current mirror (transistors 703 and 704) is employed. Transistor 702 and current source 705 are used to achieve the necessary bandwidth in the current mirror. The methods outlined above may also be implemented using discrete devices, but when implemented in an integrated circuit, control of speed and control of parasitic elements may be more advantageous.

In the examples described above in relation to fig. 1 to 7, the analog feedback stage and the digital feedback stage comprise signal delay times due to their respective signal processing. The signal delay time of a digital feedback stage may be greater than the delay time of a corresponding analog feedback stage. However, the accuracy of a digital feedback stage may be greater than the accuracy of a corresponding analog feedback stage. Still further, the digital feedback stage or path may include not only digital circuitry but also analog and digital (mixed) circuitry.

In some cases, the driver circuit of an embodiment may be prone to voltage overshoot when the gate driver is turned on or off, as illustrated in the waveform diagram of fig. 8A. Trace 801 shown in the waveform diagram of fig. 8A represents the output voltage V of the gate driver circuit of an embodiment used to provide a driver voltage for a gate of, for example, semiconductor device 106_out，driver. As shown, when the driver is activated, the output voltage V_out，driverAt a time period t_delay,onFrom Vss to a maximum voltage Vcc during the first portion of (a). Finally, the driver outputs a voltage V_out，driverDropping to the Miller plateau voltage V after the control loop of the driver circuit of an embodiment has had an opportunity to respond_Miller. Output voltage V_out，driverThe reason for the initial overshoot is because the semiconductor device 106 is in the time period t_delay,onIs open during the initial portion of (a). Because the semiconductor device 106 is off, no dV is provided during this time_CEDt and dI_CFeedback of/dt, and driver output voltage V_out，driverEssentially increasing in an unregulated manner until the semiconductor device 106 turns on and dV_CEDt and dI_CThe/dt feedback loop is closed. During the initial delay phase, dV_CEDt and dI_CThe feedback signal of both/dt is zero, while a non-zero reference signal has been applied. The controller is hard to windup to achieve non-zero dI based on a non-zero reference_CAnd/dt. Due to windup, the output of the gate driver may be limited to the driver supply voltage (labeled here as Vcc). When the gate voltage reaches its threshold and the current through the switch begins to rise(achievement of Positive dI_CDt feedback signal), the output of the drive needs to be stabilized from the drive supply to dI_CA steady state value of/dt, which therefore takes a longer delay time. During this time, dI_CThe/dt is not regulated. This voltage overshoot phenomenon is also referred to herein as "windup" or "windup effect".

In some cases, the controller may windup or overshoot as follows: making it difficult or impossible for the controller to stabilize to the driver output voltage V_out，driverAnd/or to provide the required dV_CEDt and dI_CAnd/dt. In extreme cases, the driver outputs a voltage V_out，driverMay remain unstable throughout the switching cycle.

In some conventional systems, the windup effect is mitigated by monitoring and controlling the gate current supplied to the gate of the switching device. In such systems, the gate current is monitored by measuring the voltage across a current sense resistor coupled in series with the gate of the switching device. Such systems may require additional pins to support monitoring of the voltage across the current sense resistor. Furthermore, the gate drive current for such systems may need to be recalibrated for different sized switching devices.

In embodiments of the invention, the slew rate (dV) of the driver output voltage is controlled by controlling the slew rate of the driver output voltage during the switching delay phase of the switching on and/or off_out，DriverDt) to mitigate and/or eliminate windup effects. The effect of this controlled slew rate control is represented by trace 803 in the waveform diagram of FIG. 8A, which represents the driver output voltage V when the slew rate of the output driver is under feedback control_out，Driver. As can be seen in FIG. 8A, the slew rate dV of the driver output voltage_out，driverThe/dt may be controlled in such a way that: driver output voltage V_out，driverSmoothly approaching the miller plateau V without overshoot_Miller. However, it should be understood that the waveform diagram of FIG. 8A is a simple illustration of a single scene. In some embodiments of the present invention, depending on the environment and configuration of a particular system,there may be a slight overshoot. Using the proposed dV_out，DriverThe/dt control, the difference in gate voltage and gate current can be kept small, which reduces the settling time of the gate voltage. Thus dI at switch-on_CDt or dV at turn-off_CEThe/dt can reach its steady state value earlier.