阅读说明：本技术 一种用于数据子帧聚合重传的硬件重传电路及方法 (Hardware retransmission circuit and method for data subframe aggregation retransmission ) 是由 不公告发明人 于 2019-10-09 设计创作，主要内容包括：本发明公开了一种用于数据子帧聚合重传的硬件重传电路,包括：寄存器,寄存器中存储有N个初传子帧对应的N个描述符,N为大于1的正整数；单块确认BA帧分析电路,用于对接收的当前BA帧进行分析,得出与重传子帧关联的第一信息；重传聚合电路,用于根据所述第一信息,对存储在所述寄存器中的所述重传子帧对应的描述符进行更新；系统内存读取模块,用于根据更新后的所述重传子帧对应的描述符,从主存储区中读取所述重传子帧并发送。本发明解决了现有技术BA帧的分析及子帧的聚合重传利用控制层处理,效率较低,对系统整体的吞吐率有较大的影响并且增加了主处理器的负载的缺陷。(The invention discloses a hardware retransmission circuit for data subframe aggregation retransmission, which comprises: the register is used for storing N descriptors corresponding to N initial transmission subframes, and N is a positive integer greater than 1; the single block BA frame confirming analysis circuit is used for analyzing the received current BA frame to obtain first information associated with the retransmission subframe; the retransmission aggregation circuit is used for updating the descriptors corresponding to the retransmission subframes stored in the register according to the first information; and the system memory reading module is used for reading the retransmission subframe from the main storage area and sending the retransmission subframe according to the updated descriptor corresponding to the retransmission subframe. The invention solves the defects that the analysis of the BA frame and the aggregation retransmission of the subframe utilize the control layer for processing, the efficiency is lower, the overall throughput rate of the system is greatly influenced, and the load of a main processor is increased in the prior art.)

1. A hardware retransmission circuit for aggregate retransmission of a-MPDU data frames, comprising:

the register is used for storing N descriptors corresponding to N initial transmission subframes, and N is a positive integer greater than 1;

the single block BA frame analysis circuit is used for analyzing a received current BA frame to obtain first information associated with a retransmission subframe, wherein the current BA frame is used for representing the transmission condition of each subframe in an aggregation frame sent last time, and the initial transmission subframe comprises the retransmission subframe;

the retransmission aggregation circuit is used for updating the descriptors corresponding to the retransmission subframes stored in the register according to the first information;

and the system memory reading module is used for reading the retransmission subframe from the main storage area and sending the retransmission subframe according to the updated descriptor corresponding to the retransmission subframe.

2. The hardware retransmission circuit of claim 1, further comprising a state machine to:

when the current BA frame is received, controlling the BA frame analysis circuit to analyze the current BA frame to obtain first information associated with the retransmission subframe, and controlling the retransmission aggregation circuit to update the descriptor corresponding to the retransmission subframe according to the first information;

after the updating of the descriptor corresponding to the retransmission subframe is completed, controlling the system memory reading module to read and send the retransmission subframe from the main storage area according to the updated descriptor corresponding to the retransmission subframe;

and after the retransmission subframe is completed, controlling the BA frame analysis circuit to wait for receiving the next BA frame.

3. The hardware retransmission circuit of claim 2, wherein the state machine is further to:

when specific descriptor information is received, controlling the system memory reading module to store the N descriptors into the register according to the specific descriptor information;

after the N descriptors are stored, controlling the system memory reading module to acquire the N initial transmission subframes from the main storage area according to the N descriptors and sending the N initial transmission subframes;

and after the N initial transmission subframes are completely sent, controlling the BA frame analysis circuit to wait for receiving the current BA frame.

4. The hardware retransmission circuit according to claim 3, wherein the specific descriptor information is start address information of a start descriptor, the start descriptor is a descriptor with the top address stored in the N descriptors, the descriptor is stored in the main memory area, and a next descriptor start address information is included in a single descriptor;

the system memory reading module is further configured to sequentially read the N descriptors including the start descriptor from the main storage area according to the start address information of the start descriptor and the start address information of the next descriptor, and store the N descriptors in the register.

5. The hardware retransmission circuit according to claim 4, wherein the system memory reading module is specifically configured to, after an ith descriptor is stored, determine whether the ith descriptor is a last subframe descriptor according to first field information of the ith descriptor;

if the ith descriptor is the last subframe descriptor, the storage of the N descriptors is finished;

if the ith descriptor is not the last subframe descriptor, reading the (i + 1) th descriptor according to the starting address information of the next descriptor in the ith descriptor, and sequentially increasing the i until the last subframe descriptor is read and stored, and then completing the storage of the N descriptors, wherein the i is a positive integer less than or equal to N.

6. The hardware retransmission circuit of claim 1, wherein the BA frame analysis circuit comprises:

an error judgment circuit, configured to determine, according to the SSC number of the current BA frame, the start sequence number and the end sequence number of the aggregation frame sent last time, a first sequence number corresponding to the retransmission subframe and a second sequence number corresponding to a subframe for which a transmission condition is not determined; the current BA frame includes the SSC number and bitmap information, the SSC number is a sequence number of a first subframe corresponding to the bitmap information, the starting sequence number is a sequence number of a first subframe in the aggregation frame sent last time, the ending sequence number is a sequence number of a last subframe in the aggregation frame sent last time, the sequence numbers are numbers of the N initial-transmission subframes arranged according to a sending sequence, the sequence numbers are stored in the N descriptors, and a single sequence number corresponds to a single descriptor one by one;

a sorting operation circuit, configured to align a sequence in which the bitmap information is located with a sequence of each subframe of the aggregation frame sent last time according to the SSC number of the current BA frame and the starting sequence number;

and the shift judgment circuit is used for shifting the aligned bitmap information, judging the transmission condition of the subframe of which the transmission condition is not determined, and determining a third sequence number corresponding to the retransmission subframe, wherein the first information comprises the first sequence number and the third sequence number.

7. The hardware retransmission circuit of claim 6, wherein the retransmission frame aggregation circuit is further to:

and updating the descriptor corresponding to the retransmission subframe stored in the register according to the first sequence number and the third sequence number.

8. The hardware retransmission circuit of claim 7, wherein the retransmission frame aggregation circuit is specifically configured to:

and after determining a sequence number corresponding to the jth retransmission subframe, updating a first descriptor corresponding to the jth retransmission subframe, wherein j is a positive integer less than or equal to N.

9. The circuit of claim 8, wherein the retransmission frame aggregation circuit is further specifically configured to:

after determining the sequence number corresponding to the jth retransmission subframe, updating the aggregation frame length information of the first descriptor and the aggregation frame length information of the second descriptor according to the subframe length information in the first descriptor; the second descriptor is a descriptor corresponding to the j-1 th retransmission subframe, the length information of the aggregation frame is used for representing the length information of the aggregation frame to be sent, and the updated length information of the aggregation frame is used for representing the length information of the aggregation frame to be sent.

10. A hardware retransmission method for data subframe aggregation retransmission, applied to the hardware retransmission circuit of any one of claims 1 to 9, comprising:

analyzing the received current BA frame to obtain first information associated with a retransmission subframe, wherein the current BA frame is used for representing the transmission condition of each subframe in the aggregation frame sent last time, and the initial transmission subframe comprises the retransmission subframe;

updating the descriptor corresponding to the retransmission subframe stored in the register according to the first information;

and reading the retransmission subframe from a main storage area and sending the retransmission subframe according to the updated descriptor corresponding to the retransmission subframe.

Technical Field

The present invention relates to the field of wireless communication technologies, and in particular, to a hardware retransmission circuit and method for data subframe aggregation retransmission.

Background

In order to ensure the support of the control layer to the high throughput rate and reduce the control layer overhead caused by the separate transmission of the data packets, in the 802.11n standard, an Aggregation Media protocol data unit (a-MPDU) and single Block Acknowledgement (BA) frame technology is proposed. The technique for aggregating Media layer Protocol Data units (a-MPDUs) and single Block Acknowledgement (BA) frames is that a control layer aggregates a plurality of Media layer Protocol Data units (MPDUs) having the same receiving end address into an aggregate frame to be sent to a PHY, the PHY sends the aggregate frame to the receiving end, the receiving end returns a BA frame carrying a Starting Sequence Control (SSC) number and 64-bit sequence (bitmap) information to indicate whether the receiving end correctly receives the previous Data frame, each bit in the 64-bit bitmap information indicates the receiving condition of an MPDU subframe, the normal condition is "1" and the error condition is "0", the control layer analyzes the BA frame returned by the receiving end, and whether a subframe is transmitted incorrectly. For the subframe with transmission failure, the control layer needs to re-aggregate the subframe and then send the subframe again.

However, the aggregation retransmission of the retransmission subframe has a poor regularity in aggregation processing compared with the normal subframe, and in the existing wireless network transmission, the analysis of the BA frame and the aggregation retransmission of the subframe utilize control layer processing, which has a low efficiency, has a large influence on the overall throughput rate of the system, and increases the load of the main processor.

Disclosure of Invention

The embodiment of the application provides a hardware retransmission circuit and a hardware retransmission method for data subframe aggregation retransmission, solves the problems that in the prior art, analysis of a BA frame and control layer processing of subframe aggregation retransmission are low in efficiency, the overall throughput rate of a system is greatly influenced, and the load of a main processor is increased.

On one hand, the present application provides the following technical solutions through an embodiment of the present application:

a hardware retransmission circuit for data subframe aggregation retransmission, comprising: the register is used for storing N descriptors corresponding to N initial transmission subframes, and N is a positive integer greater than 1; the single block BA frame confirmation analysis circuit is used for analyzing a received current BA frame to obtain first information associated with a retransmission subframe, wherein the current BA frame is used for representing the transmission condition of each subframe in an aggregation frame sent last time, and the initial transmission subframe comprises the retransmission subframe; the retransmission aggregation circuit is used for updating the descriptors corresponding to the retransmission subframes stored in the register according to the first information; and the system memory reading module is used for reading the retransmission subframe from the main storage area and sending the retransmission subframe according to the updated descriptor corresponding to the retransmission subframe.

In an embodiment, the apparatus further includes a state machine, where the state machine is configured to control the BA frame analysis circuit to analyze the current BA frame when the current BA frame is received, obtain first information associated with the retransmission subframe, and control the retransmission aggregation circuit to update the descriptor corresponding to the retransmission subframe according to the first information; after the updating of the descriptor corresponding to the retransmission subframe is completed, controlling the system memory reading module to read and send the retransmission subframe from the main storage area according to the updated descriptor corresponding to the retransmission subframe; and after the retransmission subframe is completed, controlling the BA frame analysis circuit to wait for receiving the next BA frame.

In one embodiment, the state machine is further configured to control the system memory reading module to store the N descriptors into the register according to specific descriptor information when the specific descriptor information is received; after the N descriptors are stored, controlling the system memory reading module to acquire the N initial transmission subframes from the main storage area according to the N descriptors and sending the N initial transmission subframes; and after the N initial transmission subframes are completely sent, controlling the BA frame analysis circuit to wait for receiving the current BA frame.

In one embodiment, the specific descriptor information is start address information of a start descriptor, the start descriptor is a descriptor with the top address stored in the N descriptors, the descriptor is stored in the main memory area, and the next descriptor start address information is included in a single descriptor; the system memory reading module is further configured to sequentially read the N descriptors including the start descriptor from the main storage area according to the start address information of the start descriptor and the start address information of the next descriptor, and store the N descriptors in the register.

In an embodiment, the system memory reading module is specifically configured to, after an ith descriptor is stored, determine whether the ith descriptor is a last subframe descriptor according to first field information of the ith descriptor; if the ith descriptor is the last subframe descriptor, the storage of the N descriptors is finished; if the ith descriptor is not the last subframe descriptor, reading the (i + 1) th descriptor according to the starting address information of the next descriptor in the ith descriptor, and sequentially increasing the i until the last subframe descriptor is read and stored, and then completing the storage of the N descriptors, wherein the i is a positive integer less than or equal to N.

In one embodiment, the BA frame analysis circuitry comprises: an error judgment circuit, configured to determine, according to the SSC number of the current BA frame, the start sequence number and the end sequence number of the aggregation frame sent last time, a first sequence number corresponding to the retransmission subframe and a second sequence number corresponding to a subframe for which a transmission condition is not determined; the current BA frame includes the SSC number and bitmap information, the SSC number is a sequence number of a first subframe corresponding to the bitmap information, the starting sequence number is a sequence number of a first subframe in the aggregation frame sent last time, the ending sequence number is a sequence number of a last subframe in the aggregation frame sent last time, the sequence numbers are numbers of the N initial-transmission subframes arranged according to a sending sequence, the sequence numbers are stored in the N descriptors, and a single sequence number corresponds to a single descriptor one by one; a sorting operation circuit, configured to align a sequence in which the bitmap information is located with a sequence of each subframe of the aggregation frame sent last time according to the SSC number of the current BA frame and the starting sequence number; and the shift judgment circuit is used for shifting the aligned bitmap information, judging the transmission condition of the subframe of which the transmission condition is not determined, and determining a third sequence number corresponding to the retransmission subframe, wherein the first information comprises the first sequence number and the third sequence number.

In one embodiment, the retransmission frame aggregation circuit is further configured to update descriptors corresponding to the retransmission subframes stored in the register according to the first sequence number and the third sequence number.

In an embodiment, the retransmission frame aggregation circuit is specifically configured to update the first descriptor corresponding to the jth retransmission subframe after determining the sequence number corresponding to the jth retransmission subframe, where j is a positive integer less than or equal to N.

In an embodiment, the retransmission frame aggregation circuit is further specifically configured to update, according to the subframe length information in the first descriptor, the aggregation frame length information of the first descriptor and the aggregation frame length information of the second descriptor after determining the sequence number corresponding to the jth retransmission subframe; the second descriptor is a descriptor corresponding to the j-1 th retransmission subframe, the length information of the aggregation frame is used for representing the length information of the aggregation frame to be sent, and the updated length information of the aggregation frame is used for representing the length information of the aggregation frame to be sent.

On the other hand, based on the same inventive concept, the present application provides the following technical solutions through an embodiment of the present application:

a hardware retransmission method for data subframe aggregation retransmission, which is applied to the hardware retransmission circuit in any of the above embodiments, includes: analyzing the received current BA frame to obtain first information associated with a retransmission subframe, wherein the current BA frame is used for representing the transmission condition of each subframe in the aggregation frame sent last time, and the initial transmission subframe comprises the retransmission subframe; updating the descriptor corresponding to the retransmission subframe stored in the register according to the first information; and reading the retransmission subframe from a main storage area and sending the retransmission subframe according to the updated descriptor corresponding to the retransmission subframe.

One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:

the invention realizes the analysis of the current BA frame returned by the receiving end and the sending of the retransmission subframe by the hardware retransmission circuit consisting of the system memory reading module, the register, the BA frame analysis circuit and the retransmission aggregation circuit, replaces the retransmission analysis work completed by upper-layer software in the prior art by the hardware retransmission circuit, compared with software processing, the processing speed of the scheme is higher, the extra time overhead of the system caused by the aggregation retransmission is reduced, the transmission throughput rate is improved, and the load of a main processor of the system is greatly reduced. In addition, the N descriptors corresponding to the N initial transmission subframes are stored through the register, the descriptors corresponding to the retransmission subframes are updated through the retransmission aggregation circuit, when the retransmission subframes are read from the main storage area subsequently, the descriptors corresponding to the updated retransmission subframes only need to be read, and the descriptors of the retransmission subframes do not need to be read from the main storage area again, so that the processing speed is further increased.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.

Fig. 1 is a circuit diagram of a hardware retransmission circuit for data subframe aggregation retransmission according to a preferred embodiment of the present application;

fig. 2 is a flowchart of a hardware retransmission method for data subframe aggregation retransmission according to a preferred embodiment of the present application.

Detailed Description

The embodiment of the application provides a hardware retransmission circuit and a hardware retransmission method for data subframe aggregation retransmission, solves the problems that in the prior art, analysis of a BA frame and control layer processing of subframe aggregation retransmission are low in efficiency, the overall throughput rate of a system is greatly influenced, and the load of a main processor is increased.

In order to solve the technical problems, the general idea of the embodiment of the application is as follows:

a hardware retransmission circuit for data subframe aggregation retransmission, comprising: the register is used for storing N descriptors corresponding to N initial transmission subframes, and N is a positive integer greater than 1; the single block BA frame analysis circuit is used for analyzing a received current BA frame to obtain first information associated with a retransmission subframe, wherein the current BA frame is used for representing the transmission condition of each subframe in an aggregation frame sent last time, and the initial transmission subframe comprises the retransmission subframe; the retransmission aggregation circuit is used for updating the descriptors corresponding to the retransmission subframes stored in the register according to the first information; and the system memory reading module is used for reading the retransmission subframe from the main storage area and sending the retransmission subframe according to the updated descriptor corresponding to the retransmission subframe. The invention realizes the analysis of the current BA frame returned by the receiving end and the sending of the retransmission subframe by the hardware retransmission circuit consisting of the system memory reading module, the register, the BA frame analysis circuit and the retransmission aggregation circuit, replaces the retransmission analysis work completed by upper-layer software in the prior art by the hardware retransmission circuit, compared with software processing, the processing speed of the scheme is higher, the extra time overhead of the system caused by the aggregation retransmission is reduced, the transmission throughput rate is improved, and the load of a main processor of the system is greatly reduced. In addition, the N descriptors corresponding to the N initial transmission subframes are stored through the register, the descriptors corresponding to the retransmission subframes are updated through the retransmission aggregation circuit, when the retransmission subframes are read from the main storage area subsequently, the descriptors corresponding to the updated retransmission subframes only need to be read, and the descriptors of the retransmission subframes do not need to be read from the main storage area again, so that the processing speed is further increased.

In order to better understand the technical solution, the technical solution will be described in detail with reference to the drawings and the specific embodiments.