阅读说明：本技术 栅极驱动器以及功率模块 (Gate driver and power module ) 是由 富泽淳 西泽昭则 于 2018-01-19 设计创作，主要内容包括：可编程解码器(201)包括按每个时钟使计数值增加的计数器(204A)、将计数值转换为地址的地址解码器(205A)、存储确定了与转换后的地址相应的数据的表格的存储部(251A)、以及对从存储部(251A)输出的与表格内的地址相应的数据进行锁存的锁存部(207)。可变驱动驱动器(202)包括多个MOS晶体管(208)、(209)、(210)。锁存部(207A)的输出与多个MOS晶体管(208)、(209)、(210)的控制电极连接。表格内的多个数据被确定为：伴随计数值的增加,可变驱动驱动器(202)的驱动力增加。计数器(20A)在臂控制信号被激活的期间更新计数值。(A programmable decoder (201) is provided with a counter (204A) for incrementing a count value for each clock, an address decoder (205A) for converting the count value into an address, a storage unit (251A) for storing a table in which data corresponding to the converted address is specified, and a latch unit (207) for latching data corresponding to the address in the table output from the storage unit (251A). The variable drive driver (202) includes a plurality of MOS transistors (208), (209), (210). The output of the latch unit (207A) is connected to the control electrodes of the MOS transistors (208), (209), and (210). A plurality of data within the table is determined as: the driving force of the variable drive driver (202) is increased along with the increase of the count value. A counter (20A) updates a count value during the period when the arm control signal is activated.)

1. A gate driver for driving an arm circuit including a power element, comprising:

a programmable decoder; and

a variable drive driver that drives the arm circuit,

the programmable decoder includes:

a counter that increments a count value every clock;

an address decoder that converts the count value into an address;

a storage unit that stores a table in which data corresponding to the address after the conversion is specified; and

a latch unit that latches data corresponding to the address in the table output from the storage unit,

the variable drive driver comprises a plurality of MOS transistors,

an output of the latch unit is connected to control electrodes of the plurality of MOS transistors, 1 st electrodes of the plurality of MOS transistors are commonly connected and connected to a control electrode of the power element, 2 nd electrodes of the plurality of MOS transistors are commonly connected to a power supply,

a plurality of data within the table is determined as: with the increase of the count value, the driving force of the variable drive driver is increased,

the counter updates the count value during activation of the arm control signal.

2. The gate driver according to claim 1, wherein the plurality of data set in the table is determined as: in the 1 st range where the count value is small, the ratio of the increase amount of the driving force of the variable drive driver to the increase amount of the count value is small, as compared with the 2 nd range where the count value is large.

3. The gate driver according to claim 1, wherein the plurality of data set in the table is determined as: in the 1 st range where the count value is small, the ratio of the increase amount of the driving force of the variable drive driver to the increase amount of the count value is large as compared with the 2 nd range where the count value is large.

4. The gate driver of claim 1,

the variable drive driver includes N MOS transistors of 1 st to Nth,

the gate width of the ith MOS transistor is greater than that of the (i-1) th MOS transistor, wherein i is more than or equal to 2,

the storage section outputs the data of N bits specified in the table,

the latch unit outputs an ith gate control signal for controlling on/off of the ith MOS transistor, based on an ith bit value of the N-bit data output from the storage unit.

5. The gate driver of claim 4, wherein the gate width of the ith MOS transistor is 2 of the gate width of the 1 st MOS transistor^(i-1)Multiple, wherein i is more than or equal to 2.

6. The gate driver of claim 4, wherein the gate width of the ith MOS transistor is Kx (i-1) times the gate width of the 1 st MOS transistor, where K is a number greater than 1 and i ≧ 2.

7. The gate driver of claim 1, wherein the table is determined as: and increasing the number of MOS transistors which are turned on among the plurality of MOS transistors according to the increase of the count value.

8. The gate driver of claim 1,

the storage section stores a plurality of tables as the tables,

the power element includes a control electrode, a1 st electrode and a2 nd electrode,

the gate driver includes: a voltage detection circuit that detects a voltage between the 1 st electrode and the 2 nd electrode of the power element,

and a controller that selects one table from the plurality of tables according to the detected magnitude of the voltage,

the storage unit outputs data corresponding to the address from the address decoder in the selected table.

9. The gate driver of claim 8,

the storage section stores a1 st table and a2 nd table as a plurality of the tables,

the controller selects one of the 1 st table and the 2 nd table according to the detected magnitude of the voltage.

10. The gate driver of claim 9,

the plurality of data set in the 1 st table are determined as: in a1 st range in which the count value is small, a ratio of an increase amount of the driving force of the variable drive driver to an increase amount of the count value is small as compared with a2 nd range in which the count value is large,

the plurality of data set in the 2 nd table are determined as: a ratio of an increase amount of the driving force of the variable drive driver to an increase amount of the count value is large in a1 st range in which the count value is small as compared with a2 nd range in which the count value is large,

the controller selects the 1 st table when the detected voltage is equal to or higher than a reference voltage, and selects the 2 nd table when the detected voltage is lower than the reference voltage.

11. The gate driver according to claim 8, comprising:

a constant current source; and

a diode having a cathode connected to the 1 st electrode of the power element,

the output of the constant current source and the anode terminal of the diode are connected to a node,

the voltage detection circuit detects a voltage between the 1 st electrode and the 2 nd electrode of the power element by detecting a voltage of the node.

12. The gate driver of claim 1,

the storage section stores a plurality of the tables,

the power element includes a control electrode, a1 st electrode and a2 nd electrode,

the gate driver includes: a current detection circuit that detects a current flowing between the 1 st electrode and the 2 nd electrode of the power element; and

a controller that selects one table from the plurality of tables according to the detected magnitude of the voltage,

the storage unit outputs data corresponding to the address from the address decoder in the selected table.

13. The gate driver of claim 12, wherein,

the table includes a1 st table and a2 nd table as a plurality of the tables,

the controller selects one of the 1 st table and the 2 nd table according to the detected magnitude of the current.

14. The gate driver of claim 13, wherein,

the plurality of data set in the 1 st table are determined as: in a1 st range in which the count value is small, a ratio of an increase amount of the driving force of the variable drive driver to an increase amount of the count value is small as compared with a2 nd range in which the count value is large,

the plurality of data set in the 2 nd table are determined as: a ratio of an increase amount of the driving force of the variable drive driver to an increase amount of the count value is large in a1 st range in which the count value is small as compared with a2 nd range in which the count value is large,

the controller selects the 1 st table when the detected current is equal to or greater than a reference current, and selects the 2 nd table when the detected current is less than the reference current.

15. The gate driver of claim 12, wherein,

the power element is an IGBT with a sense emitter,

the current detection circuit detects a current flowing between the 1 st electrode and the 2 nd electrode of the power element by detecting a current flowing at the sense emitter.

16. A gate driver for driving an arm circuit including a power element, comprising:

a programmable decoder; and

a variable drive driver that drives the arm circuit,

the programmable decoder includes:

a1 st counter that increments a1 st count value every 1 st clock;

a1 st storage unit that stores a1 st table in which data corresponding to the 1 st count value is specified;

a1 st latch unit that latches data corresponding to the 1 st count value in the 1 st table output from the 1 st storage unit;

a2 nd counter that increments a2 nd count value every 2 nd clock;

a2 nd storage unit that stores a2 nd table in which data corresponding to the 2 nd count value is specified;

a2 nd latch unit that latches data corresponding to the 2 nd count value in the 2 nd table output from the 2 nd storage unit,

the variable drive driver includes a plurality of PMOS transistors and a plurality of NMOS transistors,

an output of the 1 st latch unit is connected to control electrodes of the plurality of PMOS transistors, 1 st electrodes of the plurality of PMOS transistors are commonly connected and connected to a control electrode of the power element, 2 nd electrodes of the plurality of PMOS transistors are commonly connected to a1 st power supply,

an output of the 2 nd latch unit is connected to control electrodes of the plurality of NMOS transistors, 1 st electrodes of the plurality of NMOS transistors are commonly connected and connected to a control electrode of the power element, 2 nd electrodes of the plurality of NMOS transistors are commonly connected to a2 nd power supply,

a plurality of data within the 1 st table is determined as: the driving force of the variable drive driver is increased with an increase in the 1 st count value, and a plurality of data in the 2 nd table is determined as: the driving force of the variable drive driver is increased in accordance with the increase of the 2 nd count value.

17. A gate driver for driving an arm circuit including a power element, comprising:

a programmable decoder; and

a variable drive driver that drives the arm circuit,

the programmable decoder includes:

a counter that increases a count value for each clock in a period in which the arm 1 control signal is activated, and decreases the count value for each clock in a period in which the arm 2 control signal is activated;

an address decoder that converts the count value into an address;

a storage unit that stores a1 st table and a2 nd table in which data corresponding to the address after the conversion is specified, the storage unit outputting data corresponding to the address in the 1 st table during an active period of the 1 st arm control signal, and outputting data corresponding to the address in the 2 nd table during an active period of the 2 nd arm control signal: and

a latch section that latches data output from the storage section,

the variable drive driver comprises a plurality of MOS transistors,

an output of the latch unit is connected to control electrodes of the plurality of MOS transistors, 1 st electrodes of the plurality of MOS transistors are commonly connected and connected to a control electrode of the power element, 2 nd electrodes of the plurality of MOS transistors are commonly connected to a power supply,

the plurality of data in the 1 st table changes the driving force of the variable drive driver in accordance with an increase in the count value, and the plurality of data in the 2 nd table changes the driving force of the variable drive driver in accordance with a decrease in the count value.

18. The gate driver of claim 17,

the plurality of data in the 1 st table increases the driving force of the variable driving driver in accordance with an increase in the count value,

in addition to the decrease in the count value from the 1 st value to the 2 nd value, the plurality of data in the 2 nd table decrease the driving force of the variable drive driver in accordance with the decrease in the count value, and increase the driving force of the variable drive driver in accordance with the decrease in the count value from the 1 st value to the 2 nd value.

19. A power module is provided with:

an upper arm circuit including a1 st power element;

a lower arm circuit comprising a2 nd power element;

a1 st gate driver for driving the upper arm circuit; and

a2 nd gate driver for driving the lower arm circuit,

the 1 st gate driver and the 2 nd gate driver are the gate driver of claim 1,

the 1 st power element of the upper arm circuit and the 2 nd power element of the lower arm circuit are connected in series between a1 st power source and a2 nd power source.

Technical Field

The invention relates to a gate driver and a power module.

Background

A device is known that can reduce noise generated in an IGBT (Insulated Gate Bipolar Transistor) by relaxing the switching of the IGBT.

For example, patent document 1 describes a gate drive circuit capable of externally adjusting the switching characteristics of a voltage-driven semiconductor device constituting a power conversion device. The gate drive circuit includes an insulating circuit, a command selection circuit, a plurality of transistors, a plurality of on-gate resistors, a plurality of off-gate resistors, and a gate power supply. A selection signal and a command signal which are commanded from outside are input to a command selection circuit via an insulation circuit, any one of the plurality of on-gate resistors and the plurality of off-gate resistors is selected, and the transistors corresponding to the selected on-gate resistor and off-gate resistor are alternately turned on and off based on the command signal.

Disclosure of Invention

Problems to be solved by the invention

In patent document 1, since a user of a power conversion apparatus such as an inverter can select characteristics (for example, a high efficiency type or a low noise type) of the inverter and operate the inverter, 1 inverter can provide an inverter according to a wide range of operation specifications.

However, in the device described in patent document 1, the gate current cannot be changed in a transient manner in a programmable manner.

Therefore, an object of the present invention is to provide a gate driver and a power module capable of transitionally changing a gate current programmably.

Means for solving the problems

In order to solve the above problem, the present invention is a gate driver for driving an arm circuit including a power element. The gate driver includes a programmable decoder and a variable drive driver for driving the arm circuit. The programmable decoder includes a counter for incrementing a count value for each clock, an address decoder for converting the count value into an address, a storage unit for storing a table in which data corresponding to the converted address is specified, and a latch unit for latching data corresponding to the address in the table output from the storage unit. The variable drive driver includes a plurality of MOS transistors. The output of the latch unit is connected to control electrodes of the plurality of MOS transistors, 1 st electrodes of the plurality of MOS transistors are connected in common and to a control electrode of the power element, and 2 nd electrodes of the plurality of MOS transistors are connected in common to a power supply. A plurality of data within the table is determined as: the driving force of the variable drive driver increases with an increase in the count value. The counter updates the count value during the time that the arm control signal is activated.

ADVANTAGEOUS EFFECTS OF INVENTION

According to the present invention, since the driving force of the variable drive driver is determined by the table, the gate current can be changed in a transient programmable manner.

Drawings

Fig. 1 is a diagram showing a configuration of a power module 200 according to embodiment 1.

Fig. 2 is a diagram showing an example of conversion of the count value CA to the address ADD _ a.

Fig. 3 is a diagram showing an example of table a in table RWM 206A.

Fig. 4 is a diagram showing the gate voltage of the power element 214 in the case of using the conversion of the count value CA to the address ADD _ a in fig. 2 and the table a in fig. 3.

Fig. 5 is a diagram showing the configuration of a power module 300 according to embodiment 2.

FIG. 6 is a diagram showing an example of Table A1 in Table RWM 306A.

Fig. 7 is a diagram showing the gate voltage of the power element 214 in the case of using the conversion of the count value CA to the address ADD _ a in fig. 2 and the table a1 in fig. 6.

FIG. 8 shows an example of Table A2 in Table RWM 306B.

Fig. 9 is a diagram showing the gate voltage of the power element 214 in the case of using the conversion of the count value CA to the address ADD _ a in fig. 2 and the table a2 in fig. 8.

Fig. 10 is a diagram showing a configuration of a power module 400 according to embodiment 3.

Fig. 11 is a diagram showing a configuration of a power module 500 according to embodiment 4.

Fig. 12 is a diagram showing a configuration of a power module 600 according to embodiment 5.

Fig. 13 is a diagram showing an example of table a1 in table RWM 606A.

Fig. 14 shows an example of table B1 in table RWM 606C.

Fig. 15 shows an example of table a2 in table RWM 606B.

Fig. 16 is a diagram showing an example of table B2 in table RWM 606D.

Fig. 17 is a diagram showing simulation results when the count values CA and CB are decreased.

Detailed Description

Hereinafter, embodiments of the present invention will be described with reference to the drawings.