阅读说明：本技术 快瞬态响应ldo及其电路 (Fast transient response LDO and circuit thereof ) 是由 刘兴 胡毅 马永旺 李振国 刘浩 冯曦 冯文楠 唐晓柯 邵炜平 于 2019-10-25 设计创作，主要内容包括：本发明公开了一种快瞬态响应LDO及其电路,该电路包含一个快通路和一个慢通路,快通路由负载晶体管、第七晶体管以及第六晶体管组成。慢通路由负载晶体管、第一晶体管、第五晶体管以及第七晶体管组成。快通路用来增大环路带宽,慢通路用来增加DC精度。电路中的第二电容和第三电容能够感知负载变化,通过电容耦合的方式相应的增大或减小流过第十四晶体管和第三晶体管的电流,通过增加对负载晶体管栅极电容充放电速度从而加快环路响应速度,减小输出电压的过冲值。(The invention discloses a fast transient response LDO (low dropout regulator) and a circuit thereof. The slow path is composed of a load transistor, a first transistor, a fifth transistor, and a seventh transistor. The fast path is used to increase the loop bandwidth and the slow path is used to increase the DC accuracy. The second capacitor and the third capacitor in the circuit can sense load change, currents flowing through the fourteenth transistor and the third transistor are correspondingly increased or decreased in a capacitive coupling mode, the loop response speed is increased by increasing the charging and discharging speed of the gate capacitor of the load transistor, and the overshoot value of the output voltage is reduced.)

1. A fast transient response LDO circuit, comprising:

a first transistor;

one end of the first resistor is connected with the source electrode of the first transistor, and the other end of the first resistor is connected with an input voltage;

a second resistor having one end connected to the input voltage;

a source electrode of the fourth transistor is connected with the other end of the second resistor, and a grid electrode of the fourth transistor is connected with a drain electrode of the fourth transistor and a grid electrode of the first transistor;

a load transistor, a source of which is connected to the input voltage, a gate of which is connected to a drain of the fourth transistor, and a drain of which is used as a voltage output terminal of the fast transient response LDO circuit;

a fifth transistor, a source of which is connected to a control voltage, a drain of which is connected to the drain of the first transistor, and a gate of which is connected to the drain of the fifth transistor;

a sixth transistor, a gate of which is connected to the source of the fifth transistor, and a drain of which is connected to the gate of the fourth transistor;

a seventh transistor, a source of which is connected to the drain of the load transistor, a gate of which is connected to the gate of the fifth transistor, and a drain of which is connected to the source of the sixth transistor.

2. The fast transient response LDO circuit of claim 1, wherein the fast transient response LDO circuit further comprises:

a source of the second transistor is connected with the other end of the first resistor, and a grid of the second transistor is connected with a drain of the second transistor;

a third transistor, a gate of which is connected to the gate of the second transistor, a source of the third transistor is connected to a gate of the fourth transistor, a source of the second transistor, and one end of the second resistor, and a drain of the third transistor is connected to a gate of the first transistor and a drain of the sixth transistor;

an eighth transistor, a source of which is connected to a drain of the fifth transistor, and a gate of which is connected to a first bias voltage;

a ninth transistor, a drain of which is connected to a source of the eighth transistor, and a gate of which is connected to a second bias voltage;

a tenth transistor, a source of which is connected to the drain of the ninth transistor, and a drain of which is connected to the drain of the second transistor;

a second capacitor, one end of which is connected to the gate of the tenth transistor, and the other end of which is connected to the drain of the load transistor;

an eleventh transistor having a source connected to the source of the tenth transistor and a gate connected to the gate of the tenth transistor;

the output end of the current source is connected with the drain electrode of the eleventh transistor and the grid electrode of the eleventh transistor;

a twelfth transistor, a drain of which is connected to both the source of the sixth transistor and the drain of the seventh transistor, and a gate of which is connected to a third bias voltage;

a thirteenth transistor, a drain of which is connected to the source of the twelfth transistor, a source of which is connected to the source of the eleventh transistor, and a gate of which is connected to a fourth bias voltage;

a third capacitor having one end connected to the drain of the load transistor;

a fourteenth transistor, a drain of which is connected to both a drain of the twelfth transistor and a drain of the seventh transistor, a source of the fourteenth transistor is connected to the other end of the third capacitor, and a gate of the fourteenth transistor is connected to a fifth bias voltage;

a fifteenth transistor having a drain connected to the drain of the fourteenth transistor, a source connected to the source of the thirteenth transistor, and a gate connected to a sixth bias voltage.

3. The fast transient response LDO circuit of claim 2, wherein the fast transient response LDO circuit further comprises:

and one end of the first capacitor is connected with the grid electrode of the fifth transistor, and the other end of the first capacitor is connected with the source electrode of the ninth transistor.

4. The fast transient response LDO circuit of claim 1, wherein the fifth transistor and the sixth transistor are a pair of mirrored current mirrors.

5. The fast transient response LDO circuit of claim 1, wherein a ratio of a width to length ratio of the fifth transistor and the sixth transistor is equal to a current ratio of the fifth transistor and the sixth transistor.

6. The fast transient response LDO circuit of claim 1, wherein the sixth transistor is an NMOS transistor.

7. The fast transient response (LDO) circuit of claim 2, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the seventh transistor, and the load transistor are all PMOS transistors, and wherein the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, and the fifteenth transistor are all NMOS transistors.

8. A fast transient response LDO, comprising the fast transient response LDO circuit as claimed in any one of claims 1 to 7.

Technical Field

The present invention relates to the field of circuit design, and more particularly, to a fast transient response LDO and a circuit thereof.

Background

The low dropout regulator (LDO) is a common power management chip, has the advantages of simple structure, low cost, low noise, low power consumption, simple peripheral circuit and the like, and is widely applied to a plurality of fields such as medical treatment, computers, industrial basic equipment, portable products and the like. The traditional LDO with an off-chip capacitor structure needs a large capacitor with microfarad magnitude externally hung on a chip, so that on one hand, an output pole can be easily made to be a dominant pole, and frequency compensation is facilitated; on the other hand, although the external large capacitor can reduce the loop bandwidth, when the load of the LDO changes rapidly, the charge and discharge energy of the capacitor is used for achieving stable output before the circuit responds to the change of the load, and similarly, the LDO with the off-chip capacitor also has good power supply rejection characteristic. However, the external capacitor is large and requires a specific range of resistance of the equivalent series resistor, and occupies an extra pin of the chip and a large area of the printed circuit board, which is not favorable for chip integration and limits the application.

In recent years, LDO without off-chip capacitor is more and more favored, the design difficulty is mainly stability and transient response speed, and the stability needs to be improved by internal pole compensation without large off-chip capacitor, which undoubtedly increases the complexity and design difficulty of the circuit, often at the expense of power consumption and precision. In addition, when the load current suddenly changes, the output voltage thereof generates a large overshoot due to the loop response speed.

The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.

Disclosure of Invention

The invention aims to provide a fast transient response LDO and a circuit thereof, which can improve the response speed of a loop and reduce the overshoot of an output voltage when a load changes.

To achieve the above object, the present invention provides a fast transient response LDO circuit, which includes: : the transistor comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a load transistor, a first resistor, a second resistor, a first capacitor, a second capacitor, a third capacitor and a current source.

One end of the first resistor is connected with the source electrode of the first transistor; the source electrode of the second transistor is connected with the other end of the first resistor, and the grid electrode of the second transistor is connected with the drain electrode of the second transistor; the grid electrode of a third transistor is connected with the grid electrode of the second transistor, the source electrode of the third transistor is connected with the source electrode of the second transistor, and the drain electrode of the third transistor is connected with the grid electrode of the first transistor; one end of the second resistor is connected with the source electrode of the third transistor and the input voltage; the source electrode of the fourth transistor is connected with the other end of the second resistor, and the grid electrode of the fourth transistor is connected with the drain electrode of the third transistor and the drain electrode of the fourth transistor; the source electrode of the load transistor is connected with the input voltage, and the grid electrode of the load transistor is connected with the drain electrode of the fourth transistor; a source electrode of the fifth transistor is connected with a control voltage, a drain electrode of the fifth transistor is connected with a drain electrode of the first transistor, and a grid electrode of the fifth transistor is connected with a drain electrode of the fifth transistor; the grid electrode of the sixth transistor is connected with the source electrode of the fifth transistor, and the drain electrode of the sixth transistor is connected with the drain electrode of the third crystal; a source of a seventh transistor is connected to the drain of the load transistor, a gate of the seventh transistor is connected to the gate of the fifth transistor, and a drain of the seventh transistor is connected to the source of the sixth transistor; the source electrode of the eighth transistor is connected with the drain electrode of the fifth transistor, and the grid electrode of the eighth transistor is connected with the first bias voltage; the drain electrode of the ninth transistor is connected with the source electrode of the eighth transistor, and the grid electrode of the ninth transistor is connected with the second bias voltage; one end of a first capacitor is connected with the grid electrode of the fifth transistor, and the other end of the first capacitor is connected with the source electrode of the ninth transistor; a source of the tenth transistor is connected to a drain of the ninth transistor, and a drain of the tenth transistor is connected to a drain of the second transistor; one end of a second capacitor is connected with the grid electrode of the tenth transistor, and the other end of the second capacitor is connected with the drain electrode of the load transistor; a source of the eleventh transistor is connected to a source of the tenth transistor, and a gate of the eleventh transistor is connected to a gate of the tenth transistor; the output end of the current source is connected with the drain electrode of the eleventh transistor and the grid electrode of the eleventh transistor; the drain electrode of the twelfth transistor is connected with the source electrode of the sixth transistor and the drain electrode of the seventh transistor, and the grid electrode of the twelfth transistor is connected with a third bias voltage; a drain of a thirteenth transistor is connected with a source of the twelfth transistor, a source of the thirteenth transistor is connected with a source of the eleventh transistor, and a gate of the thirteenth transistor is connected with a fourth bias voltage; one end of the third capacitor is connected with the drain electrode of the load transistor; a drain electrode of the fourteenth transistor is connected with a drain electrode of the twelfth transistor and a drain electrode of the seventh transistor, a source electrode of the fourteenth transistor is connected with the other end of the third capacitor, and a gate electrode of the fourteenth transistor is connected with a fifth bias voltage; a drain of the fifteenth transistor is connected to a drain of the fourteenth transistor, a source of the fifteenth transistor is connected to a source of the thirteenth transistor, and a gate of the fifteenth transistor is connected to a sixth bias voltage.

In one embodiment of the present invention, the fifth transistor and the sixth transistor are a current mirror in a mirror image relationship, and a ratio of a width-to-length ratio of the fifth transistor and the sixth transistor is equal to a current ratio of the fifth transistor and the sixth transistor.

In one embodiment of the present invention, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the seventh transistor, and the load transistor are all PMOS transistors, and the sixth transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, and the fifteenth transistor are all NMOS transistors.

Compared with the prior art, the fast transient response LDO circuit comprises a fast path (consisting of the load transistor, the seventh transistor and the sixth transistor) and a slow path (consisting of the load transistor, the first transistor, the fifth transistor and the seventh transistor), wherein the fast path is used for increasing the loop bandwidth, and the slow path is used for increasing the DC precision. The second capacitor and the third capacitor can sense load change, currents flowing through the fourteenth transistor and the third transistor are correspondingly increased or decreased in a capacitive coupling mode, the loop response speed is increased by increasing the charging and discharging speed of the gate capacitor of the load transistor, and the overshoot value of the output voltage is reduced. The first capacitor and the fifth transistor form RC filtering, and the influence of a slow path on the stability of a fast path is further reduced. Therefore, the fast transient response LDO circuit provided by the invention realizes large bandwidth, ensures DC precision, improves load regulation rate, and reduces the influence of process, voltage and temperature on output voltage.

Drawings

FIG. 1 is a fast transient response LDO circuit according to an embodiment of the invention.

Detailed Description

The following detailed description of the present invention is provided in conjunction with the accompanying drawings, but it should be understood that the scope of the present invention is not limited to the specific embodiments.

Throughout the specification and claims, unless explicitly stated otherwise, the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.

As shown in fig. 1, in one embodiment, the fast transient response LDO circuit 10 includes: the circuit comprises a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a load transistor Mpass, a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, a third capacitor C3 and a current source I.

One end of the first resistor R1 is connected to the source of the first transistor M1; the source of the second transistor M2 is connected to the other end of the first resistor R1, and the gate of the second transistor M2 is connected to the drain of the second transistor M2; the gate of the third transistor M3 is connected to the gate of the second transistor M2, the source of the third transistor M3 is connected to the source of the second transistor M2, and the drain of the third transistor M3 is connected to the gate of the first transistor M1; one end of the second resistor R2 is connected to the source of the third transistor M3 and the input voltage; the source of the fourth transistor M4 is connected to the other end of the second resistor R2, and the gate of the fourth transistor M4 is connected to the drain of the third transistor M3 and the drain of the fourth transistor M4; source and input voltage V of load transistor Mpass_INThe grid electrode of the load transistor Mpass is connected with the drain electrode of the fourth transistor M4; the source of the fifth transistor M5 and the control voltage V_ctrlConnected to the drain of the fifth transistor M5A pole of the fifth transistor M5 is connected with the drain of the first transistor M1, and a gate of the fifth transistor M5 is connected with the drain of the fifth transistor M5; the gate of the sixth transistor M6 is connected to the source of the fifth transistor M5, and the drain of the sixth transistor M6 is connected to the drain of the third transistor; the source of the seventh transistor M7 is connected to the drain of the load transistor Mpass, the gate of the seventh transistor M7 is connected to the gate of the fifth transistor M5, and the drain of the seventh transistor M7 is connected to the source of the sixth transistor M6; a source of the eighth transistor M8 is connected to a drain of the fifth transistor M5, a gate of the eighth transistor M8 is connected to the first bias voltage V_bn1Connecting; a drain of the ninth transistor M9 is connected to a source of the eighth transistor M8, a gate of the ninth transistor M9 is connected to the second bias voltage V_bn2Connecting; one end of the first capacitor C1 is connected to the gate of the fifth transistor M5, and the other end of the first capacitor C1 is connected to the source of the ninth transistor M9; a source of the tenth transistor M10 is connected to the drain of the ninth transistor M9, and a drain of the tenth transistor M10 is connected to the drain of the second transistor M2; one end of the second capacitor C2 is connected with the gate of the tenth transistor M10, and the other end of the second capacitor C2 is connected with the drain of the load transistor Mpass; a source of the eleventh transistor M11 is connected to a source of the tenth transistor M10, and a gate of the eleventh transistor M11 is connected to a gate of the tenth transistor M10; the output end of the current source I is connected with the drain electrode of the eleventh transistor M11 and the gate electrode of the eleventh transistor M11; a drain of the twelfth transistor M12 is connected to a source of the sixth transistor M6 and a drain of the seventh transistor M7, and a gate of the twelfth transistor M12 is connected to the third bias voltage V_bn3Connecting; a drain of the thirteenth transistor M13 is connected to a source of the twelfth transistor M12, a source of the thirteenth transistor M13 is connected to a source of the eleventh transistor M11, a gate of the thirteenth transistor M13 is connected to the fourth bias voltage V_bn4Connecting; one end of the third capacitor M3 is connected with the drain electrode of the load transistor Mpass; a drain of the fourteenth transistor M14 is connected to both the drain of the twelfth transistor M12 and the drain of the seventh transistor M7, a source of the fourteenth transistor M14 is connected to the other end of the third capacitor M3, a gate of the fourteenth transistor M14 is connected to the fifth bias voltage V_bn5Connecting; fifteenth transistor M15 is connected to the drain of the fourteenth transistor M14, the source of the fifteenth transistor M15 is connected to the source of the thirteenth transistor M13, the gate of the fifteenth transistor M15 is connected to the sixth bias voltage V_bn6Are connected.

In the present embodiment, the control voltage V_ctrlGenerated by a bandgap reference circuit 11 and a control voltage generator 12. The respective bias voltages are generated by a bandgap reference circuit 11. The first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the seventh transistor M7, and the load transistor Mpass are all PMOS transistors, and the sixth transistor M6, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15 are all NMOS transistors.

Specifically, the fast transient response LDO circuit comprises a fast path composed of transistors Mpass, M7 and M6 and a slow path composed of Mpass, M1, M5 and M7, wherein the fast path is used for increasing the loop bandwidth, and the slow path is used for increasing the DC precision. The design of the fast path and the slow path improves the load regulation rate, and reduces the process, the voltage and the temperature to the output voltage V_LDOThe influence of (c). Transistors M3, M8, M9, M12, M13, M14, M15 serve as current sources to provide bias current to the circuit. The capacitors C2 and C3 can sense load changes, accordingly increase or decrease the current flowing through the M14 and M3 tubes in a capacitive coupling mode, and the overshoot value of the output voltage is reduced by increasing the charging and discharging speed of the gate capacitor of the load transistor Mpass. The capacitor C1 and the diode-connected M5 form an RC filter, further reducing the effect of the slow path on the fast path stability.

The fast path includes three poles in total, V_A、V_GAnd an output pole V_LDO，V_AIs a high frequency node, V_GThe node becomes a low-resistance node due to the connection of M4 in the form of a diode, and V_GThe capacitance of the node is mainly from the gate capacitance of the transistor Mpass and is far smaller than the output pole V_LDOThus the output pole V_LDOBecomes the dominant pole and V_GIs the secondary dominant pole. At V_GAnother effect of the M4 in the form of a pole-connected diode is to reduce the loop gain of the fast path, since even if the output pole is the dominant pole, which is still at a higher frequency due to the impedance seen by the source of transistor M7 being about 1/gm, the dominant and secondary poles are not spaced far apart, and reducing the loop gain helps to improve the phase margin. The fast path has large-3 dB bandwidth and gain bandwidth product GBW, which is the key for realizing fast response of the loop, and V in the circuit structure_GAnd V_AConnected between them is an NMOS (transistor M6), V_GAnd V_AThe voltage difference between them need only be greater than one overdrive voltage. Thus, V can be reduced_AThe node is sensitive to load current and supply voltage, so the circuit can be suitable for wide supply voltage range applications.

When the load current is increased or reduced, the capacitors C2 and C3 can sense the load change, and the slew rate of charging and discharging the gate capacitor of the Mpass tube is correspondingly increased in an RC coupling mode. Slew rate current of gate capacitance discharge is represented by current I of M3_n1And I_n4The difference is provided by the charging slew rate current_n3(I_n3＝I_n2) Provided is a method. When the load current is increased to cause the output voltage to generate downward overshoot, a transient increased current is superposed on the M14 tube after the load current is coupled through the capacitor C3, the current provided by the transistor M3 after the load current is coupled through the capacitor C2 has a transient decrease, and the discharged slew rate current is equal to I_n1-I_n4+ΔI_M14+ΔI_M3(ii) a Similarly, when the load current is reduced to cause the output voltage to generate upward overshoot, the slew rate current charged after the capacitive coupling is I_n3+ΔI_M14+ΔI_M3. Wherein, I_n1Is the current of transistor M15, I_n3Is the current of transistor M3, I_n4Is the current of the resistor R2, Δ I_M14The current change value of the transistor M14 when the load current changes. Delta I_M3The current change value of the transistor M3 when the load current changes.

In this embodiment, M5 and M7 are current mirrors in a mirror image relationship, and the ratio of the width to length ratio of the two transistors to the powerEqual current ratio and output voltage V_LDOAnd V_CTRLThe value of M4 is equal, and a part of I is occupied by the diode formed by M4_n1The current, flowing through M7, is no longer a constant value if V is directly applied_CTRLGiven the gate of M7, the LDO output voltage has a poor load regulation rate, so the current M1 is mirrored by M4 and the current I_n2The summed current to M5 is still proportional to the current of M7, and the effect of R2 and R3 is to reduce the sensitivity of the diode resistance to voltage.

In summary, the fast transient response LDO circuit according to the present embodiment includes a fast path and a slow path, the fast path is used to increase the loop bandwidth, and the slow path is used to increase the DC accuracy. Transistors M3, M8, M9, M12, M13, M14, M15 serve as current sources to provide bias current to the circuit. The capacitors C2 and C3 can sense load changes, currents flowing through the current source M14 and M3 are correspondingly increased or decreased in a capacitive coupling mode, the loop response speed is increased by increasing the charging and discharging speed of the load transistor Mpass grid capacitor, and the overshoot value of the output voltage is reduced. The capacitor C1 and the diode-connected M5 form an RC filter that further reduces the effect of the slow path on the fast path stability. And in the fast path, the grid node impedance of the transistor is reduced by using the diode-connected transistor, so that the output pole is the dominant pole, the gain bandwidth product GBW is increased, and the frequency range of power supply rejection is improved. In addition, the source and drain electrodes of the NMOS tube are also adopted to be connected with V_AAnd V_GNode, reduce V_AThe node is sensitive to load current and supply voltage, so the circuit can be suitable for wide supply voltage range applications.

The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.