阅读说明：本技术 放电用半导体集成电路以及电源系统 (Semiconductor integrated circuit for discharge and power supply system ) 是由 寺田忠平 高野阳一 于 2019-06-19 设计创作，主要内容包括：本发明提供一种放电用半导体集成电路以及电源系统,其能够通过一个控制信号控制多个电源或供给电压的切断时序,且能够容易地变更放电时间。在具备多个放电用元件、分别连接了这些多个放电用元件的一方的端子的多个外部端子、能够从外部输入表示内部电路动作的有效/无效的信号的控制用外部端子的放电用半导体集成电路中,构成为在多个放电用元件的控制端子输入从控制用外部端子输入的信号或以该信号为输入的逻辑电路的输出信号,根据多个放电用元件被设为导通状态,从对应的外部端子吸取电荷。(The invention provides a semiconductor integrated circuit for discharge and a power supply system, which can control the cut-off time sequence of a plurality of power supplies or supply voltage through one control signal and can easily change the discharge time. In a discharge semiconductor integrated circuit including a plurality of discharge elements, a plurality of external terminals to which one terminal of the plurality of discharge elements is connected, and a control external terminal to which a signal indicating validity/invalidity of an operation of an internal circuit can be externally input, a signal input from the control external terminal or an output signal of a logic circuit to which the signal is input to a control terminal of the plurality of discharge elements, and charges are drawn from the corresponding external terminal in accordance with a state in which the plurality of discharge elements are turned on.)

1. A semiconductor integrated circuit for discharge, comprising a plurality of discharge elements, a plurality of external terminals to which one terminal of the plurality of discharge elements is connected, and a control external terminal to which a signal indicating validity/invalidity of an operation of an internal circuit can be inputted from the outside,

a signal input from the control external terminal or an output signal of a logic circuit to which the signal is input to the control terminals of the plurality of discharge elements, and electric charges are drawn from the corresponding external terminals in accordance with the plurality of discharge elements being brought into an on state.

2. The semiconductor integrated circuit for discharge according to claim 1,

the other terminals of the plurality of discharge elements are connected to a common external terminal for grounding.

3. The semiconductor integrated circuit for discharge according to claim 1,

the discharge semiconductor integrated circuit includes a plurality of external terminals to which the other terminals of the plurality of discharge elements are connected.

4. The semiconductor integrated circuit for discharge according to claim 1 or 2,

the control external terminal is provided corresponding to each of the control terminals of the plurality of discharge elements.

5. The semiconductor integrated circuit for discharge according to claim 1 or 2,

the semiconductor integrated circuit for discharge includes a delay circuit that delays a signal input from the external terminal for control, and a schmitt trigger circuit that takes the signal delayed by the delay circuit as an input signal.

6. A power supply system, characterized in that,

the semiconductor integrated circuit for discharge of any one of claims 1 to 5 and a plurality of power supply devices are provided,

an output terminal of one of the plurality of power supply devices is connected to one of the plurality of external terminals of the semiconductor integrated circuit for discharge,

the output terminals of the other power supply devices among the plurality of power supply devices are connected to 2 or more external terminals other than the one external terminal among the plurality of external terminals of the semiconductor integrated circuit for discharge.

Technical Field

The present invention relates to a semiconductor integrated circuit for discharge incorporating a discharge element, and more particularly to a semiconductor integrated circuit for discharge and a power supply system capable of forming a plurality of discharge paths and adjusting a discharge time.

Background

In devices such as a CPU (microprocessor), SoC (system on chip), and system LSI, which require a plurality of power supplies, on/off timings (sequence) may be defined. For example, in the case of a CPU using 2 power supplies (regulators) for I/O and core, the potentials of the 2 power supplies are generally set to have a relationship of I/O power supply > core power supply. In such a device or system, if the potential relationship between the I/O power supply and the core power supply is reversed, a parasitic element inside the CPU serving as the core may be turned on and damaged. Therefore, in a device using a plurality of power sources, it is necessary to restrict the timing of on/off.

Conventionally, in the above-described devices and systems, when the timing at the time of shutdown is controlled, a discharge circuit shown in fig. 4B is configured by discrete components (an inverter, an FET, a resistor, and the like), for example, and when the supply of power is stopped (the regulator is turned off), the core power supply is first discharged and then the I/O power supply is discharged.

As an invention related to a reference voltage source circuit including a discharge circuit, for example, there is an invention disclosed in patent document 1. In the present invention, the discharge FET is turned on by a control signal ENABLE, thereby discharging the charge remaining in the output capacitor of the reference voltage source and rapidly decreasing the output voltage.

When the discharge circuit is configured by discrete components, there are problems in that 2 control signals (enable 1,2) are required as shown in fig. 4B, and a plurality of FETs need to be prepared when the discharge time of each of the plurality of power supply outputs is to be made different.

Further, in the invention disclosed in patent document 1, it is not easy to change the discharge time, and both the discharge transistor and the output voltage control transistor may be turned on at the same time, so that there is a problem that a through current may flow from the power supply terminal to the ground point.

Patent document 1: U.S. Pat. No. 6414537 publication

Disclosure of Invention

The present invention has been made in view of the above-described problems, and an object thereof is to provide a semiconductor integrated circuit for discharge and a power supply system capable of controlling a plurality of power supplies or a timing of cutting off a supply voltage by one control signal and easily changing a discharge time.

Another object of the present invention is to provide a discharge semiconductor integrated circuit capable of preventing a through current from flowing through a current supply path from a power supply and a discharge path from a discharge element from being simultaneously activated.

In order to achieve the above object, the present invention provides a semiconductor integrated circuit for discharge including a plurality of discharge elements, a plurality of external terminals to which one terminal of the plurality of discharge elements is connected, and a control external terminal to which a signal indicating validity/invalidity of an operation of an internal circuit can be inputted from outside, wherein a signal inputted from the control external terminal or an output signal of a logic circuit inputted with the signal is inputted to a control terminal of the plurality of discharge elements, and charges are drawn from the corresponding external terminal in accordance with a state in which the plurality of discharge elements are turned on.

According to the above-described means, the plurality of discharge elements are used individually or connected in parallel outside the chip, and the magnitude of the current drawn can be set, whereby the timing of turning off the plurality of power supplies or the supply voltage can be controlled by one control signal, and the discharge time can be easily changed.

Here, it is preferable that the other terminal of the plurality of discharge elements is connected to a common external terminal for grounding.

This can reduce the number of external terminals provided on the chip.

Alternatively, the discharge element may be provided with a plurality of external terminals each connected to the other terminal of the plurality of discharge elements.

In this way, the plurality of discharge elements are used individually or connected in series outside the chip, and the magnitude of the current drawn can be set, so that the timing of turning off the plurality of power supplies or the supply voltage can be controlled by one control signal, and the discharge time can be easily changed.

Preferably, the control external terminal is provided corresponding to each of the control terminals of the plurality of discharge elements.

Thus, by making the timings of signals inputted from the outside to the plurality of control terminals different, the discharge timing can be shifted, whereby the timing of turning off the plurality of power sources or supply voltages can be controlled, and the discharge time can be easily changed.

Preferably, the control circuit includes a delay circuit that delays a signal input from the control external terminal, and a schmitt trigger circuit that takes the signal delayed by the delay circuit as an input signal.

Thus, when the semiconductor integrated circuit is applied to a system including a switching element connected between an external power supply voltage terminal and an output terminal of a discharge semiconductor integrated circuit, it is possible to avoid that the switching element and a discharge element in the chip are simultaneously turned on by the same control signal and a through current flows. Further, since the schmitt trigger circuit is provided at the subsequent stage of the delay circuit, it is possible to prevent the operation of the discharge element from becoming unstable due to noise or the like entering the delay circuit.

A power supply system according to another invention of the present application includes the above-described semiconductor integrated circuit for discharge and a plurality of power supply devices,

an output terminal of one of the plurality of power supply devices is connected to one of the plurality of external terminals of the semiconductor integrated circuit for discharge,

the output terminals of the other power supply devices among the plurality of power supply devices are connected to 2 or more external terminals other than the one external terminal among the plurality of external terminals of the semiconductor integrated circuit for discharge.

In the power supply system having the above configuration, since the electric charges of the output terminals of the power supply devices whose output terminals are connected to 2 or more external terminals can be discharged earlier than the electric charges of the output terminals of the power supply devices whose output terminals are connected to 1 external terminal, the disconnection timing can be controlled, and the discharge time can be easily changed by changing the number of external terminals of the discharge semiconductor integrated circuit connected to the output terminals of the power supply devices.

According to the semiconductor integrated circuit for discharge of the present invention, the timing of turning off a plurality of power supplies or supply voltages can be controlled by one control signal, and the discharge time can be easily changed. In addition, there is an effect that it is possible to prevent a through current from flowing through a current supply path from a power supply and a discharge path from a discharge element which are simultaneously activated.

Drawings

Fig. 1 is a circuit configuration diagram showing an embodiment of a semiconductor integrated circuit for discharge to which the present invention is applied.

Fig. 2A is a circuit configuration diagram showing a configuration example of a system using the semiconductor integrated circuit for discharge of fig. 1, and fig. 2B is a circuit configuration diagram showing a configuration example of another system using the semiconductor integrated circuit for discharge of fig. 1.

Fig. 3A and 3B are circuit configuration diagrams showing specific examples of the power supply circuit in fig. 2A and 2B.

Fig. 4A is a circuit configuration diagram showing a configuration example of a power supply system using the semiconductor integrated circuit for discharge of fig. 1, and fig. 4B is a circuit configuration diagram showing a configuration example of a conventional power supply system in which a discharge circuit is configured using discrete components.

Fig. 5 is a circuit configuration diagram showing a configuration example of a power supply system using the semiconductor integrated circuit for discharge of the modification 1 with respect to the difference in size setting of the discharge elements (M1 < M2 < M3).

Fig. 6 is a circuit configuration diagram showing a modification 2 of the semiconductor integrated circuit for discharge according to the embodiment shown in fig. 1 and a configuration example of a voltage supply system using the semiconductor integrated circuit for discharge.

Fig. 7 is a circuit configuration diagram showing embodiment 2 of a semiconductor integrated circuit for discharge to which the present invention is applied.

Fig. 8A is a circuit configuration diagram showing embodiment 3 of a semiconductor integrated circuit for discharge to which the present invention is applied, and fig. 8B is a circuit configuration diagram showing a use example thereof.

Description of reference numerals

10 … semiconductor integrated circuit for discharge (IC for discharge), 11 … inverter (rectifier circuit), 12 … delay circuit, 13 … schmitt trigger circuit, 20 … power supply (regulator), 30 … object system, MOS transistor for discharge of M1, M2, M3 …, MT1 … switching MOS transistor.

Detailed Description

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

Fig. 1 shows an embodiment of a semiconductor integrated circuit for discharge according to the present invention. Further, elements constituting a circuit surrounded by a chain line a in fig. 1 are formed on one semiconductor chip and constitute a semiconductor Integrated Circuit (IC).

The discharge semiconductor integrated circuit (hereinafter referred to as a discharge IC)10 of the present embodiment includes a power supply terminal VDD to which a power supply voltage is applied from the outside, a ground terminal GND to which a ground potential is applied, a chip Enable terminal CE to which an Enable signal "Enable (Enable)" indicating the validity/invalidity of a chip operation (operation of an internal circuit) is input, and three output terminals Vo1, Vo2, and Vo 3. Although not particularly limited, the discharge IC of the present embodiment is configured as a low-level active IC in which a discharge element inside a chip is turned on and performs a discharge operation when an Enable signal "Enable (Enable)" input to a terminal CE is at a low level. The output terminals Vo1, Vo2, and Vo3 function as external terminals to which elements such as capacitors and electronic components can be connected outside the chip.

In addition, three N-channel MOS transistors M1, M2, and M3 for discharge connected between the output terminals Vo1, Vo2, Vo3 and the ground terminal GND and an inverter 11 for connecting an input terminal and the chip enable terminal CE are provided inside the chip, and the MOS transistors M1, M2, and M3 are controlled to be turned on and off by an output signal of the inverter 11.

Specifically, when the Enable signal "Enable (Enable)" is at a low level, the output signal of the inverter 11 changes to a high level, and the MOS transistors M1, M2, and M3 are turned on, and function as a discharge element that draws electric charge from a load, a capacitor, and the like connected to the output terminals Vo1, Vo2, and Vo 3. Therefore, the MOS transistors M1, M2, M3 are designed to have an element size capable of obtaining a desired discharge speed. Although not particularly limited, in this embodiment, the MOS transistors M1, M2, and M3 have the same size. Instead of the inverter 11, a schmitt trigger circuit may be used. This can avoid malfunction due to noise entering the terminal CE.

Next, a configuration example of a system using the discharge IC of the above embodiment will be described with reference to fig. 2A and 2B.

In fig. 2A, in a circuit that supplies or cuts off the voltage VOUT generated by the power supply circuit 20 to the target system 30, the voltage VOUT is rapidly lowered when the power supply circuit 20 is cut off, thereby preventing malfunction of the target system 30. The power supply circuit 20 may employ a regulator, a DC/DC converter, or another power supply circuit.

Specifically, in a circuit in which a voltage stabilizing capacitor C1 is provided at a ground point between the power supply circuit 20 and the target system 30, and an Enable signal "Enable" (Enable) as a control signal for turning on and off the power supply circuit 20 is input, as shown by a solid line in fig. 2A, a wiring L1 connecting a connection node N1 of the power supply circuit 20 and the capacitor C1 and the output terminal Vo1 of the discharging IC10 of the above embodiment is provided, and when the power supply circuit 20 is turned off, residual charges of the capacitor C1 are discharged by the discharging IC10, and the voltage VOUT supplied to the target system 30 is rapidly reduced.

In addition, when the discharge speed of the discharge IC is to be increased, wirings L2 and L3 for connecting the output terminals Vo2 and Vo3 to the connection node N1 are provided as indicated by broken lines in fig. 2A. When the discharge speed is to be set to a medium speed, the output terminals Vo1 and Vo2 or Vo1 and Vo3 may be connected to the connection node N1.

In the configuration of fig. 2A, the signal input to the chip Enable terminal CE of the discharging IC10 is an Enable signal "Enable (Enable)" which is the same as a signal for turning on/off the power supply circuit 20. Therefore, when the Enable signal "Enable (Enable)" becomes low level, the power supply circuit 20 is turned off, and the supply to the target system 30 is cut off, the MOS transistor M1 in the discharge IC is immediately turned on, the residual charge of the capacitor C1 is absorbed, and the potential of the node N1 rapidly decreases.

Fig. 2B is a configuration example of a case where, in the case of the target system 30A to which the voltage VOUT1 generated by the power supply circuit 20A is supplied and the target system 30B to which the voltage VOUT2 generated by the power supply circuit 20B is supplied, it is desired to promptly lower the voltages VOUT1 and VOUT2 when the voltages VOUT1 and VOUT2 are cut off, thereby preventing the target systems 30A and 30B from malfunctioning, and causing VOUT1 to fall earlier than VOUT 2.

In the circuit of fig. 2B, output terminals Vo1 and Vo2 of the discharging IC10 of the above-described embodiment are connected to a node N1 as indicated by solid lines L1 and L2, and an output terminal Vo3 of the discharging IC is connected to a connection node N2 as indicated by solid line L3. With this configuration, when the power supply circuits 20A and 20B are turned off, the residual charges in the capacitors C1 and C2 are discharged, and the voltages VOUT1 and VOUT2 supplied to the target systems 30A and 30B can be rapidly reduced, and VOUT1 can be reduced earlier than VOUT 2.

Specifically, a capacitor C1 is provided between the power supply circuit 20A and the ground point, and a capacitor C2 is provided between the power supply circuit 20B and the ground point. In fig. 2B, the power supply circuits 20A and 20B are turned on and off by an Enable signal "Enable (Enable)", but Enable signals for turning on and off the power supply circuits 20A and 20B may be provided separately.

Specifically, as shown in fig. 3A, the power supply circuit 20 in fig. 2A and the power supply circuits 20A and 20B in fig. 2B include a regulator REG, a switching MOS transistor MT1 that controls supply/cutoff of a voltage VOUT generated by the regulator REG, and an inverter 21 that receives an Enable signal "Enable" and generates a signal that controls a gate terminal of the transistor MT 1.

Alternatively, as shown in fig. 3B, a simple regulator may be provided as the power supply circuits 20A and 20B, which includes the differential amplifier 22 having the gate terminal of the control MOS transistor MT2, the resistors R1 and R2 for dividing the drain voltage of the MT2, and the reference voltage Vref, and applies the voltage divided by the resistors R1 and R2 to the inverting input terminal of the differential amplifier 22, thereby generating a voltage proportional to the reference voltage Vref and supplying the voltage as the output voltage VOUT. In this circuit, the differential amplifier 22 may be turned off by an Enable signal "Enable" to cut off the output voltage VOUT, and the MOS transistor MT1 for switching is not required.

Fig. 4A shows a configuration example of a case where the discharge IC of the above embodiment is applied to a power supply system.

Specifically, the output terminal Vout1 of the discharging IC10 of the above embodiment is connected to the output terminal Vout of the 1 st power supply device (DC/DC converter or regulator LDO)20A, and the output terminals Vo2 and Vo3 of the discharging IC10 of the above embodiment are connected to the output terminal Vout of the 2 nd power supply device 20B. The Enable signal "Enable (Enable)" of the discharging IC10 is common to Enable signals for turning on and off the power supply devices 20A, 20B.

In the power supply system of fig. 4A, when the 2 power supply devices 20A and 20B are turned off by the Enable signal "Enable (Enable)", the electric charges of the output voltage stabilizing capacitors C1 and C2 connected to the output terminals Vout of the power supply devices 20A and 20B are discharged, and the output voltages VoutA and VoutB can be rapidly reduced. In the power supply system of fig. 4A, since 2 output terminals Vo2 and Vo3 of the discharging IC10 are connected to the output terminal Vout of the power supply device 20B, VoutB can be lowered earlier than the output voltage VoutA.

In a conventional power supply system having the same function, a discharge circuit as shown in fig. 4B is configured by discrete components (an inverter, an FET, and the like), for example. As can be seen from a comparison of fig. 4A and 4B, the power supply system of fig. 4A has a small number of components. In the conventional system of fig. 4B, it is necessary to prepare MOS transistors having different sizes as the MOS transistors M11 and M12 for discharge, but the power supply system of fig. 4A has an advantage that it is easy to manage components because only one discharge IC10 is required.

(modification 1)

In the IC10 for discharge of the above embodiment, the MOS transistors M1, M2, and M3 for discharge are designed as elements of the same size, but the transistors M1, M2, and M3 may be designed to have a size of, for example, 1: 2: a ratio of 3. By configuring the power supply system shown in fig. 5 using the discharge IC10 thus designed, the output voltages VoutA, VoutB, and VoutC of the power supplies (regulators) 20A, 20B, and 20C can be lowered in the order VoutC → VoutB → VoutA.

(modification 2)

Fig. 6 shows a modification 2 of the discharge IC10 of the above embodiment.

In the modification of fig. 6, the chip enable terminals CE1, CE2, CE3 and the inverters 11A, 11B, 11C are provided corresponding to each of the MOS transistors M1, M2, M3 for discharge. According to such a configuration, the timing of the enable signals "enable 1, enable 2, and enable 3" input to the chip enable terminals CE1, CE2, and CE3 is controlled by a system control device such as an external microcomputer, and the discharge order of the transistors M1, M2, and M3 can be freely set.

(embodiment 2)

Fig. 7 shows a configuration of a discharge IC10 according to embodiment 2 and a system of an application example.

As shown in fig. 7, the discharging IC10 of this embodiment includes a delay circuit 12 including a resistor R1 and a capacitor C1, a 2 nd inverter 13, and a 3 rd inverter 14, between the inverter 11 that inverts the enable signal "enable" and the gate terminals of the discharging MOS transistors M1, M2, and M3. The 2 nd inverter 13 may be replaced with a schmitt trigger circuit or a comparator so that the input signal of the inverter 14 does not fluctuate due to noise or the like entering the delay circuit 12 and the operation of the discharge MOS transistors M1, M2, and M3 is not stabilized. Note that the 2 nd inverter 14 is used for logic adjustment, and may be omitted in the case of a configuration (configuration without the inverter INV 1) in which the power supply circuit is turned on when the enable signal "enable" for controlling the power supply circuit (IC) is low.

In the system of fig. 2A and 2B having the same functions as the system shown in fig. 7, the power supply circuit 20 and the MOS transistors M1 to M3 for discharge are turned on and off complementarily, but when the on and off are switched, the power supply circuit 20 and the MOS transistors M1 to M3 may be turned on simultaneously instantaneously, and a through current may flow.

In contrast, since the delay circuit 12 is provided in the system shown in fig. 7, the MOS transistors M1 to M3 for discharge can be turned on after the switching MOS transistor MT1 is turned off. Therefore, there is an advantage that a direct current can be reliably prevented from flowing through the MT1 and the M1 to M3.

(embodiment 3)

Fig. 8A and 8B show a structure of a discharge IC10 according to embodiment 3.

The discharging IC10 of this embodiment is provided with 2 nd and 3 rd ground terminals GND1 and GND2 in addition to the ground terminal GND0 of the ground potential of the inverter 11 to which the inversion enable signal "enable" is supplied, and source terminals of the MOS transistors M1 and M2 for discharging are connected to these ground terminals GND1 and GND 2.

According to the discharge IC having the above-described configuration, as shown in fig. 8A, by applying a ground potential to the ground terminals GND1 and GND2, it is possible to discharge the electric charges of the capacitor and the load connected to the output terminals Vo1 and Vo2, respectively.

As shown in fig. 8B, the output terminal Vo2 and the ground terminal GND1 are connected to each other by a short-circuit line L4 indicated by a broken line, whereby the MOS transistors M1 and M2 can be connected in series to increase the on-resistance, and the discharge rate can be made slower than that in the embodiment of fig. 8A.

The wiring L4 shown in fig. 8B may be an aluminum wiring inside the chip.

The invention made by the present inventors has been specifically described above based on the embodiments, but the present invention is not limited to the above embodiments. For example, in the discharge IC of the above embodiment, 2 or 3 MOS transistors for discharge are shown, but the number of transistors is not limited to 2 or 3, and may be 4 or more.

In addition, although the enable signal "enable" input to the chip enable terminal CE is received by the inverter and supplied to the gate terminals of the MOS transistors M1, M2, and M3 for discharge in the above embodiment, the enable signal "enable" may be received by a logic circuit such as an OR gate instead of the inverter. In the above embodiment, the case where the IC is configured as a discharge-dedicated IC has been described, but the present invention can also be applied to a case where the IC is configured as a part of an IC having another function such as a regulator control function.