阅读说明：本技术 一种对母线电压的采样方法及pfc控制电路、电源转换电路 (Bus voltage sampling method, PFC control circuit and power conversion circuit ) 是由 韦威胜 于 2019-08-13 设计创作，主要内容包括：本发明适用于电源控制技术领域,提供了一种对母线电压的采样方法及PFC控制电路、电源转换电路,包括：首先实时采样馒头波电压,以得到多个检测电压值；然后根据多个检测电压值获取馒头波电压的特征点,特征点为过零点和/或最大值,根据特征点找到对应的采样时间点；最后根据采样时间点获取对应的母线电压的采样值。本发明利用馒头波特征点和母线电压平均值之间的对应关系,来获取母线电压的采样值,本发明方法对PFC控制电路的开销非常小,并且开环方式不存在振荡的可能,算法设计简单,输出稳定,采用一般的微处理器,而不需要专用的高速DSP,即可实施对PFC母线的电压环进行适时补偿,节省了大量计算资源,芯片的选型自由度大。(The invention is suitable for the technical field of power control, and provides a bus voltage sampling method, a PFC control circuit and a power conversion circuit, which comprise: firstly sampling the wave voltage of the steamed bread in real time to obtain a plurality of detection voltage values; then acquiring characteristic points of the steamed bread wave voltage according to the plurality of detected voltage values, wherein the characteristic points are zero crossing points and/or maximum values, and finding corresponding sampling time points according to the characteristic points; and finally, acquiring a sampling value of the corresponding bus voltage according to the sampling time point. The method has the advantages that the cost of the PFC control circuit is very small, the possibility of oscillation does not exist in an open-loop mode, the algorithm design is simple, the output is stable, a general microprocessor is adopted, a special high-speed DSP is not needed, the voltage loop of the PFC bus can be timely compensated, a large amount of computing resources are saved, and the freedom degree of the type selection of a chip is large.)

1. A method for sampling bus voltage, one input voltage of a PFC control circuit is a steamed bread wave voltage, and the other input voltage is the bus voltage, and the method is characterized by comprising the following steps:

sampling the steamed bread wave voltage in real time to obtain a plurality of detection voltage values;

acquiring characteristic points of the steamed bread wave voltage according to the detection voltage values, wherein the characteristic points are zero crossing points and/or maximum values, and finding corresponding sampling time points according to the characteristic points;

and acquiring a corresponding sampling value of the bus voltage according to the sampling time point.

2. The method for sampling bus voltage according to claim 1, wherein the obtaining of the characteristic points of the steamed bread wave voltage according to the plurality of detected voltage values, the characteristic points being zero-crossing points and/or maximum values, and finding corresponding sampling time points according to the characteristic points specifically comprises:

comparing the bus voltage value sampled at present with the bus voltage value sampled last time;

if the difference value between the bus voltage value sampled at present and the bus voltage value sampled at last time is larger than a preset value, judging that the bus voltage is in a large disturbance state, acquiring characteristic points of the steamed bread wave voltage according to a plurality of detected voltage values, wherein the characteristic points are zero-crossing points and maximum values, and finding corresponding sampling time points according to the characteristic points;

if the difference value between the bus voltage value sampled at present and the bus voltage value sampled at last time is not larger than a preset value, the bus voltage is judged to be in a stable state, characteristic points of the steamed bun wave voltage are obtained according to a plurality of detected voltage values, the characteristic points are zero-crossing points or maximum values, and corresponding sampling time points are found according to the characteristic points.

3. The method for sampling bus voltage according to claim 1, wherein the obtaining of the sampling time point corresponding to the zero-crossing point of the steamed bread wave voltage specifically comprises: and acquiring a corresponding sampling time point when the steamed bread wave voltage is zero.

4. The method for sampling bus voltage according to claim 1, wherein the method for obtaining the maximum value of the steamed bread wave voltage comprises:

presetting a peak value holder and a counter, wherein the initial value in the peak value holder is 0, and the initial value of the counter is 0;

judging whether the current detection voltage value is larger than the voltage value stored in the peak value holder;

if the current detection voltage value is larger than the voltage value stored in the peak value keeper, updating the current detection voltage value to the voltage value stored in the peak value keeper;

if the current detection voltage value is not larger than the voltage value stored in the peak value holder, the peak value holder is not updated, and a counter is increased by 1;

and when the counting of the counter reaches a preset value, stopping judging, wherein the voltage value stored in the peak value retainer is the maximum value of the steamed bread wave voltage.

5. The method for sampling bus voltage of claim 4, wherein the preset value of the counter is 3.

6. The method for sampling bus voltage according to claim 4, wherein the peak value holder and the counter are preset, and the initial value in the peak value holder is 0, and before the initial value in the counter is 0, the method further comprises:

carrying out low-pass filtering on the steamed bread wave voltage to obtain an average value of the steamed bread wave voltage; judging whether the current detection voltage value is larger than the average value of the steamed bread wave voltage;

if the current detection voltage value is larger than the average value of the steamed bread wave voltage, the function of the peak value retainer is started;

if the current detection voltage value is not larger than the average value of the steamed bread wave voltage, the function of the peak value retainer is closed.

7. The method for sampling bus voltage according to claim 1, wherein said sampling said steamed bread wave voltage in real time to obtain a plurality of detected voltage values further comprises:

if the steamed bread wave voltage is temporarily powered off, setting a fixed time period;

and acquiring corresponding sampling values of the bus voltage every other fixed time period until the steamed bread wave voltage returns to normal.

8. The method for sampling bus voltage according to claim 7, wherein the fixed time period is 5-10 ms.

9. A PFC control circuit comprises a voltage loop compensation circuit, a current loop compensation circuit and a PWM control circuit, and further comprises: the bus voltage sampling circuit has the input of the steamed bread wave voltage and the bus voltage and is used for realizing the bus voltage sampling method according to any one of claims 1 to 8;

the input of the voltage loop compensation circuit is the steamed bread wave voltage and the output of the bus voltage sampling circuit, and the voltage loop compensation circuit is used for performing voltage compensation on the bus voltage;

the input of the current loop compensation circuit is the output of the voltage loop compensation circuit and is used for carrying out current compensation on the bus voltage;

the input of the PWM control circuit is the output of the current loop compensation circuit and is used for outputting a PWM control signal so as to realize power factor correction of the steamed bread wave voltage on the bus voltage.

10. A power conversion circuit is characterized by comprising an inductor, a diode, a switching tube, a capacitor and a DC-DC conversion circuit;

one end of the inductor is connected with the anode of the diode, the other end of the inductor is connected with the voltage of the steamed bread wave, the cathode of the diode is the voltage of a bus, the bus is electrically connected with the DC-DC conversion circuit in a voltage mode, and the voltage of the bus is grounded through a capacitor; the anode of the diode is grounded through a switch tube;

the PFC control circuit of claim 9, further comprising a PWM control signal coupled between the input of the PFC control circuit and the steamed bun wave voltage and the bus voltage, and coupled to the control terminal of the switching tube.

Technical Field

The invention belongs to the technical field of power electronics, and particularly relates to a bus voltage sampling method, a PFC (power factor correction) control circuit and a power conversion circuit.

Background

In the digital control, a software phase-locked loop is adopted to replace a traditional analog phase-locked loop so as to reduce errors generated in the phase-locked process of a hardware circuit, which brings the expense of CPU computing resources and relates to the work of discretization conversion of analog quantity and the like, so that the whole design work is more complicated.

The digital PFC circuit based on DSP control is the same as the traditional circuit topology controlled by an analog chip, and the difference lies in that the former control of a loop circuit samples input voltage, input current and output voltage (bus voltage) through analog-to-digital conversion and then carries out discretization conversion, the input of a PWM control circuit is obtained through software calculation according to the loop control rule and is used for driving a switch tube to complete the voltage stabilization of PFC output voltage, meanwhile, the input current is enabled to follow the input voltage of sinusoidal conversion, the function of power conversion with the power factor close to 1 is completed, the traditional analog control mode has similar flow, but the realization part is an analog device, the flexibility is far lower than that of digital control, such as frequency conversion, voltage transformation and the like.

Although a digitally controlled Power Factor Corrector (PFC) achieves highly flexible adjustment, it has certain requirements on DSP resources, on one hand, because an excessively high processor frequency causes an excessively high power consumption, and at the same time, there is a direct proportional relationship in cost, so that when a DSP model is selected, a relatively low-frequency CPU core is generally selected to reduce power consumption and cost.

However, if the DSP index after the compromise is not optimized in design, it will have a certain influence on the operation performance, so how to try to save the computation resource and simultaneously achieve the purpose of not influencing the performance of the DPFC, such as stability and dynamic response characteristics, is a topic worth discussing.

Disclosure of Invention

In view of this, the embodiment of the present invention provides a bus voltage sampling method, a PFC control circuit, and a power conversion circuit, and aims to solve the problem in the prior art that the performance requirement on the CPU core of the DSP is too high due to the fact that the bus voltage is subjected to discretization conversion and the input of the PWM control circuit is obtained through software calculation according to the loop control law.

A first aspect of an embodiment of the present invention provides a method for sampling a bus voltage, where an input voltage of a PFC control circuit is a steamed bread wave voltage, and another input voltage is a bus voltage, where the method includes:

sampling the steamed bread wave voltage in real time to obtain a plurality of detection voltage values;

acquiring characteristic points of the steamed bread wave voltage according to the detection voltage values, wherein the characteristic points are zero crossing points and/or maximum values, and finding corresponding sampling time points according to the characteristic points;

and acquiring a corresponding sampling value of the bus voltage according to the sampling time point.

A second aspect of the embodiments of the present invention provides a PFC control circuit, including a voltage loop compensation circuit, a current loop compensation circuit, and a PWM control circuit, further including: the bus voltage sampling circuit inputs the steamed bread wave voltage and the bus voltage and is used for realizing the bus voltage sampling method;

the input of the voltage loop compensation circuit is the steamed bread wave voltage and the output of the bus voltage sampling circuit, and the voltage loop compensation circuit is used for performing voltage compensation on the bus voltage;

the input of the current loop compensation circuit is the output of the voltage loop compensation circuit and is used for carrying out current compensation on the bus voltage;

the input of the PWM control circuit is the output of the current loop compensation circuit and is used for outputting a PWM control signal so as to realize power factor correction of the steamed bread wave voltage on the bus voltage.

A third aspect of the embodiments of the present invention provides a power conversion circuit, which is characterized by including an inductor and a diode connected in series, wherein the other end of the inductor is connected with a voltage of a header wave, a cathode of the diode is a bus voltage, the bus voltage is electrically connected to the DC-DC conversion circuit, and the bus voltage is grounded through a capacitor; the anode of the diode is grounded through a switch tube;

the input of the PFC control circuit is the steamed bread wave voltage and the bus voltage, the output of the PFC control circuit is a PWM control signal, and the PFC control circuit is connected with the control end of the switching tube.

Compared with the prior art, the embodiment of the invention has the following beneficial effects: firstly sampling the wave voltage of the steamed bread in real time to obtain a plurality of detection voltage values; then acquiring characteristic points of the steamed bread wave voltage according to the plurality of detected voltage values, wherein the characteristic points are zero crossing points and/or maximum values, and finding corresponding sampling time points according to the characteristic points; finally, acquiring a sampling value of the corresponding bus voltage according to the sampling time point; the method has the advantages that the cost of the PFC control circuit is very small, the possibility of oscillation does not exist in an open loop mode, the algorithm design is simple, the output is stable, a general microprocessor is adopted, a special high-speed DSP is not needed, the voltage loop of the PFC bus can be timely compensated, a large amount of computing resources are saved, and the freedom degree of selection of a chip is large.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

Fig. 1 is a schematic flow chart of an implementation of a bus voltage sampling method according to an embodiment of the present invention;

FIG. 2 is a schematic of a steamed bun wave voltage and an average value of the steamed bun wave voltage;

fig. 3 is a schematic flow chart of another implementation of the bus voltage sampling method provided by the embodiment of the present invention;

fig. 4 is a block diagram of an internal structure of a PFC control circuit according to an embodiment of the present invention;

fig. 5 is a schematic circuit diagram of a power conversion circuit according to an embodiment of the present invention.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.

In order to explain the technical means of the present invention, the following description will be given by way of specific examples.

Fig. 1 shows an implementation flow of a bus voltage sampling method provided by an embodiment of the present invention, and for convenience of description, only a part related to the embodiment of the present invention is shown, and the following details are described:

one input voltage of the PFC control circuit is a steamed bread wave voltage, the other input voltage is a bus voltage,

in step 101, sampling the steamed bread wave voltage in real time to obtain a plurality of detection voltage values;

step 101 may specifically be: and determining real-time detection frequency according to the frequency of the steamed bread wave voltage, and sampling the steamed bread wave voltage in real time according to the detection frequency to obtain a plurality of detection voltage values.

In step 102, feature points of the steamed bread wave voltage are obtained according to the multiple detected voltage values, the feature points are zero-crossing points and/or maximum values, and corresponding sampling time points are found according to the feature points.