阅读说明：本技术 一种dc-dc电路及其控制方法 (DC-DC circuit and control method thereof ) 是由 李永红 于 2019-10-25 设计创作，主要内容包括：本发明涉及一种DC-DC电路及其控制方法,用于电子领域,包括给系统提供时钟信号CLK的振荡器、将输出电压反馈信号VFB与基准电压VREF相比较并输出电平信号Y1的PWM比较器、根据CLK信号与Y1信号生成占空比控制信号PWM的PFM控制器、根据PWM信号分别生成DRV1信号与DRV2信号的功率管驱动电路、通过DRV1信号驱动导通与关闭的功率管及通过DRV2信号驱动导通与关闭的同步管,还包括通过比较同步管两端电压降生成一电平信号Y2控制非连续模式下同步管关断时刻的过零比较器,其特征在于,还包括动态偏置电路,动态偏置电路根据功率管关断时间的长短来控制输出至PWM比较器与过零比较器的偏置电流。(The invention relates to a DC-DC circuit and a control method thereof, which are used in the electronic field, and comprise an oscillator for providing a clock signal CLK for a system, a PWM comparator for comparing an output voltage feedback signal VFB with a reference voltage VREF and outputting a level signal Y1, a PFM controller for generating a duty ratio control signal PWM according to the CLK signal and a Y1 signal, a power tube driving circuit for respectively generating a DRV1 signal and a DRV2 signal according to the PWM signal, a power tube for driving the conduction and the closing through the DRV1 signal and a synchronous tube for driving the conduction and the closing through the DRV2 signal, and a zero-crossing comparator for controlling the turn-off time of the synchronous tube in a discontinuous mode by comparing voltage drops at two ends of the synchronous tube to generate a level signal Y2, the PWM comparator is characterized by further comprising a dynamic bias circuit, wherein the dynamic bias circuit controls bias current output to the PWM comparator and the zero-crossing comparator according to the turn-off time of the power tube.)

1. A DC-DC circuit comprises an oscillator for providing a clock signal CLK for a system, a PWM comparator for comparing an output voltage feedback signal VFB with a reference voltage VREF and outputting a level signal Y1, a PFM controller for generating a duty ratio control signal PWM according to the CLK signal and a Y1 signal, a power tube driving circuit for respectively generating a DRV1 signal and a DRV2 signal according to the PWM signal, a power tube which is driven to be switched on and off by a DRV1 signal and a synchronous tube which is driven to be switched on and off by a DRV2 signal, and a zero-crossing comparator for controlling the turn-off time of the synchronous tube in a discontinuous mode by comparing voltage drops at two ends of the synchronous tube to generate a level signal Y2.

2. A control method of the DC-DC circuit according to claim 1, wherein the bias current of the dynamic bias circuit is kept constant at a fixed value I1 during the TON phase;

the dynamic bias circuit changes bias current along with the turn-off time of the power tube in the TOFF stage, and when the power tube is turned to be within the first time length t1 of turn-off, the bias current is I1;

when the off time exceeds t1 and is less than a second time length t2, the bias current is reduced, and the lowest bias current is I2;

when the off time exceeds t2, the bias current is I2.

3. The method as claimed in claim 2, wherein the on/off state of the power transistor is a TON stage, and the off state of the power transistor is a TOFF stage.

4. A method for controlling a DC-exchanger according to claim 2, characterized in that said first time duration t1 is chosen to be larger than one switching period Ts.

Technical Field

The invention relates to the field of electronics, in particular to a DC-DC circuit and a control method thereof.

Background

DC-DC is widely used in various electronic devices to provide a stable power supply to the system. Among them, the PFM type DC-DC is widely used in battery-powered electronic systems due to its advantages of simple structure, low power consumption and low cost. DC-DC, although simple and easy to use and efficient, cannot meet the ultra-low power consumption requirements of the system in some emerging applications. For example, in the field of emerging internet of things, many applications are battery powered and require lengthy operating times. And for example, the intelligent wearable device is also provided with a battery for supplying power and requires an ultra-long standby time. Conventional PFM-type DC-DC, although already having a small quiescent current, typically a few uA or a few tens uA, may still not meet the more stringent low power consumption requirements.

Disclosure of Invention

The invention aims to solve the problem of overlarge static consumption of a traditional DC-DC circuit, and provides a DC-DC circuit and a control method.

The technical scheme of the invention is that the DC-DC circuit comprises an oscillator for providing a clock signal CLK for a system, a PWM comparator for comparing an output voltage feedback signal VFB with a reference voltage VREF and outputting a level signal Y1, a PFM controller for generating a duty ratio control signal PWM according to the CLK signal and a Y1 signal, a power tube driving circuit for respectively generating a DRV1 signal and a DRV2 signal according to the PWM signal, a power tube for driving the conduction and the closing through the DRV1 signal and a synchronous tube for driving the conduction and the closing through the DRV2 signal, and a zero-crossing comparator for generating a level signal Y2 by comparing voltage drops at two ends of the synchronous tube to control the turn-off time of the synchronous tube in a discontinuous mode, the PWM zero-crossing comparator is characterized by further comprising a dynamic bias circuit, wherein the dynamic bias circuit controls bias currents output to the PWM comparator and the zero-crossing comparator according to the turn-off time of the power tube.

The control method of the DC-DC circuit is characterized in that the bias current of the dynamic bias circuit is kept constant at a fixed value I1 in the TON stage;

the dynamic bias circuit changes bias current along with the turn-off time of the power tube in the TOFF stage, and when the power tube is turned to be within the first time length t1 of turn-off, the bias current is I1;

when the off time exceeds t1 and is less than a second time length t2, the bias current is reduced, and the lowest bias current is I2;

when the off time exceeds t2, the bias current is I2.

Furthermore, the on-off state of the power tube is a TON stage, and the off state of the power tube is a TOFF stage.

Further, the first time length t1 is selected to be greater than one switching period Ts.

Compared with the prior art, the invention has the beneficial effects that:

the technical scheme can obviously reduce the working current of the system during light load or no load, thereby realizing ultra-low power consumption.

And the bias current of the PWM comparator and the zero-crossing comparator is controlled through a dynamic bias circuit by receiving the feedback of the on-off of the power tube.

Drawings

FIG. 1 is a circuit configuration diagram of a DC-DC circuit of the present invention;

FIG. 2 is a diagram of the dynamic bias circuit TON phase bias current waveform of the DC-DC circuit of the present invention;

fig. 3 is a waveform diagram of the TOFF stage bias current of the dynamic bias circuit of the DC-DC circuit of the present invention.

Description of the main component symbols:

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings:

referring to fig. 1, a DC-DC circuit includes an oscillator 1 for providing a clock signal CLK to a system, a PWM comparator 4 for comparing an output voltage feedback signal VFB of an output voltage sampling resistor divider network 2 with a reference voltage VREF of a reference circuit 3 and outputting a level signal Y1, a PFM controller 5 for generating a duty control signal PWM according to the CLK signal and the Y1 signal, a power transistor driving circuit 6 for generating a DRV1 signal and a DRV2 signal according to the PWM signal, respectively, a zero crossing comparator 9 for the power transistor driving circuit 6 to drive a power transistor 7 to turn on and off through the DRV1 signal and the power transistor driving circuit 6 to drive a sync transistor 8 to turn on and off through the DRV2 signal, and generating a level signal Y2 by comparing voltage drops at two ends of the sync transistor 8 to control the turn-off time of the sync transistor 8 in a discontinuous mode, and is characterized by further including a dynamic bias circuit 10, the dynamic bias circuit 10 controls the bias current output to the PWM comparator 4 and the zero-crossing comparator 9 according to the turn-off time of the power tube 7.

Referring to fig. 1-3, a method for controlling a DC-DC circuit includes:

the bias current of the dynamic bias circuit 10 is kept constant at a fixed value I1 in the TON stage;

the dynamic bias circuit 10 changes the bias current along with the turn-off time of the power tube 7 in the TOFF stage, and when the power tube 7 is turned to be within the first time length t1 of turn-off, the bias current is I1;

when the off time exceeds t1 and is less than a second time length t2, the bias current is reduced, and the lowest bias current is I2;

when the off time exceeds t2, the bias current is I2.

The above-mentioned embodiments are only preferred embodiments of the present invention, and all equivalent changes and modifications made within the scope of the claims of the present invention should be covered by the claims of the present invention.