阅读说明：本技术 外延层及n型鳍式场效应晶体管的制备方法 (Epitaxial layer and N-type fin field effect transistor preparation method ) 是由 刘熙 于 2018-05-30 设计创作，主要内容包括：本发明提供了一种制备高浓度磷掺杂的硅外延层的方法,涉及半导体制造加工工艺领域。该方法首先通过低压化学气相沉积方法生长普通浓度磷掺杂的硅外延层,再通过气相原子层沉积方法在所述硅外延层表面接枝并吸附多分子层的磷-卟啉配合物,并通过快速热退火工艺,将磷-卟啉配合物中的磷原子扩散入硅磷外延层中,该工艺方法可大幅提高硅磷外延层中磷原子的掺杂浓度,提高其中载流子的迁移效率,同时降低接触电阻。(the invention provides a method for preparing a high-concentration phosphorus-doped silicon epitaxial layer, and relates to the field of semiconductor manufacturing and processing technologies. According to the method, a phosphorus-doped silicon epitaxial layer with common concentration is grown through a low-pressure chemical vapor deposition method, then a polymolecular layer of phosphorus-porphyrin complex is grafted and adsorbed on the surface of the silicon epitaxial layer through a vapor atomic layer deposition method, and phosphorus atoms in the phosphorus-porphyrin complex are diffused into the silicon phosphorus epitaxial layer through a rapid thermal annealing process.)

1. A preparation method of an epitaxial layer comprises the following steps:

Forming a silicon epitaxial layer with phosphorus doping;

Forming a complex polymolecular layer on the surface of the silicon epitaxial layer, wherein the central atom of the complex is phosphorus;

And performing rapid thermal annealing to diffuse at least part of phosphorus in the complex polymolecular layer into the phosphorus-doped silicon epitaxial layer.

2. The method for producing an epitaxial layer according to claim 1, wherein the complex is a complex compound of phosphorus and a porphyrin derivative.

3. the method for preparing an epitaxial layer according to claim 2, wherein the complex has a structure represented by formula (I):

Wherein R ₁ is independently selected from phenyl, biphenyl, naphthyl or anthracenyl;

R ₂ is each independently selected from hydrogen, hydroxy, or C1-C6 alkyl;

And at least one R ₂ is hydroxy.

4. The method of preparing the epitaxial layer of claim 3 wherein R ₁ is p-phenyl, R ₂ is independently selected from methyl or hydroxy, and at least one R ₂ is hydroxy.

5. The method for preparing an epitaxial layer according to claim 2, wherein the complex has a structure represented by formula (II):

6. The method for producing an epitaxial layer according to any one of claims 1 to 5, wherein the complex polymolecular layer is formed by a vapor phase atomic layer deposition method.

7. The method for producing an epitaxial layer according to claim 6, wherein the gas pressure in the vapor phase atomic layer deposition process is 20 to 100 mTorr.

8. The method for preparing an epitaxial layer according to any of claims 1 to 5 wherein the rapid thermal annealing step employs a uniform temperature anneal in the range of 400 ℃ to 600 ℃.

9. The method for preparing an epitaxial layer of claim 1 further comprising, prior to performing the rapid thermal annealing step: and forming a covering protective layer on the surface of the complex multi-molecular layer.

10. The method for preparing an epitaxial layer of claim 9 wherein the cap layer is made of a silicon nitride material.

11. A method for manufacturing an N-type fin field effect transistor, comprising the method for manufacturing the epitaxial layer of any one of claims 1 to 10.

12. The method of claim 11, wherein the epitaxial layer is formed on a surface of the fin not covering the gate structure.

13. The method of claim 11, further comprising a source-drain annealing step that activates phosphorous in the epitaxial layer during the source-drain annealing step.

Technical Field

The invention relates to the technical field of semiconductor processes, in particular to a preparation method of an epitaxial layer and a fin field effect transistor.

Background

With the development of semiconductor structures and processes, the size of integrated circuits has been continuously reduced, and the integrated circuits have been converted from the conventional planar-field-effect-transistor (FinFET) to the fin-field-effect-transistor (FinFET). FinFET devices may in turn be classified into P-type finfets and N-type finfets according to carrier type.

In order to improve the carrier migration efficiency, an epitaxial layer is generally required to be grown on a fin portion of a FinFET, wherein a germanium-doped silicon epitaxy is used in a P-type FinFET to form a compressive stress on a channel so as to improve the hole carrier migration efficiency; in the N-type FinFET, phosphorus-doped silicon epitaxy or carbon-phosphorus-doped silicon epitaxy is used, and tensile stress is formed on a channel to improve the migration efficiency of electron carriers.

For N-type FinFET, the doping concentration of phosphorus in silicon epitaxy grown by Low Pressure Chemical Vapor Deposition (LPCVD) method usually adopted at present is not high, and the doping concentration can only substantially satisfy the requirement of channel tensile stress, and if the contact resistance of the source and drain regions is further reduced on this basis, phosphorus doping with higher concentration is performed on the source and drain regions.

Accordingly, those skilled in the art have made an effort to develop a method for effectively increasing the doping concentration of phosphorus in the silicon epitaxial layer to further increase the electron mobility of the channel region while reducing the contact resistance of the source and drain regions.

Disclosure of Invention

in view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method for effectively increasing the phosphorus doping concentration in a silicon epitaxial layer.

The preparation method provided by the invention comprises the following steps: forming a silicon epitaxial layer with phosphorus doping; forming a complex polymolecular layer on the surface of the silicon epitaxial layer, wherein the central atom of the complex is phosphorus; rapid Thermal Annealing (RTA) causes phosphorus in at least a portion of the complex monolayer to diffuse into the phosphorus doped silicon epitaxial layer. The concentration and the quantity of phosphorus atoms in the complex polymolecular layer are higher, and the phosphorus atoms in the complex polymolecular layer are diffused into the silicon epitaxial layer, so that the doping concentration of the phosphorus atoms in the silicon epitaxial layer can be improved to a greater extent.

In a preferred technical scheme of the invention, the complex is a coordination compound formed by phosphorus and a porphyrin derivative.

Further, in a preferred embodiment of the present invention, the complex has a structure shown in formula (I):

The main reasons for adopting the R ₂ substituent are that on one hand, the hydroxyl is utilized to react with silicon oxygen bonds on a silicon epitaxial layer, so that molecules can be fixed with the silicon epitaxial layer through chemical bonding, and on the other hand, the cross-linking between the hydroxyl groups can facilitate the molecules to form a more stable multi-molecular layer structure.

Still further, in a preferred embodiment of the invention, R ₁ is p-phenyl, R ₂ is independently selected from methyl or hydroxy, and at least one R ₂ is hydroxy.

preferably, the complex has a structure shown in formula (II):

In a preferred technical scheme of the invention, the complex polymolecular layer is formed by a vapor phase atomic layer deposition method. The compact and stable complex multi-molecular layer film can be grown by a gas phase atomic layer deposition method.

Further, in a preferred embodiment of the present invention, the gas pressure of the vapor phase atomic layer deposition process is 20 mTorr to 100 mTorr. This atmospheric pressure scope can control the molecular layer and grow with suitable speed, and the too fast one side of growth rate can make thickness be difficult to control, and the one side can make the polymolecular layer compactness that obtains relatively poor, influences the even degree of phosphorus atom concentration distribution in the silicon epitaxial layer that follow-up diffusion step obtained, and too slow growth rate can influence efficiency, reduces the productivity.

In the preferred technical scheme of the invention, the rapid thermal annealing step adopts 400-600 ℃ uniform temperature annealing (Soak Anneal). On the one hand, the decomposition temperature of the hydroxyl-phenyl-phosphorus porphyrin molecule is 400-600 ℃; in one aspect, the suitable temperature range facilitates the subsequent rapid thermal annealing step.

In a preferred embodiment of the present invention, before performing the rapid thermal annealing step, the method further comprises: and forming a covering protective layer on the surface of the complex multi-molecular layer.

Further, in a preferred embodiment of the present invention, the cover protection layer is made of a silicon nitride material. The silicon nitride covering protective layer can prevent phosphorus atoms in the complex polymolecular layer from diffusing to other parts in the device in the subsequent rapid thermal annealing process, and the improvement effect of phosphorus doping concentration is ensured.

The invention also provides a preparation method of the N-type fin field effect transistor.

In a preferred embodiment of the present invention, the epitaxial layer is formed on a surface of a portion of the fin portion not covering the gate structure. By using the epitaxial layer preparation method provided by the invention to carry out epitaxial growth on the source and drain regions, the phosphorus doping concentration of the silicon epitaxial layer of the source and drain regions of the N-type fin field effect transistor can be greatly improved, meanwhile, the contact resistance of the source and drain regions is reduced, and the operation rate of a device is improved.

in the preferred technical scheme of the invention, the method further comprises a source-drain annealing step, and the phosphorus in the epitaxial layer is activated during the source-drain annealing step. The activation of the phosphorus atoms is completed in the subsequent source-drain annealing step, so that the process flow is simplified, and the manufacturing cost is reduced.

drawings

FIG. 1 is a schematic structural view of conformal doping of a self-assembled monolayer;

Fig. 2 is a schematic structural view of conformal doping of a polymolecular layer in one embodiment of the present invention;

FIG. 3 is a schematic diagram of the atomic layer deposition apparatus of FIG. 2 for forming a multi-molecular layer;

Fig. 4-9 are schematic cross-sectional views illustrating a finfet formation process in the embodiment of fig. 2.

Detailed Description

As described in the background art, a phosphorus-doped silicon epitaxial layer is generally grown by a low-pressure vapor deposition method at present, however, the doping concentration of phosphorus in the epitaxial layer obtained by the method is not high, and the doping concentration can only substantially meet the requirement of channel tensile stress, but cannot further reduce the contact resistance of a source region and a drain region on the basis.

Fig. 1 shows a method for increasing the phosphorus doping concentration in a silicon epitaxial layer by Self-Assembled Monolayer (SAM) conformal doping.

The method mainly comprises the following steps:

Firstly, forming a phosphorus-doped silicon epitaxial layer 100 by in-situ doping by adopting an LPCVD (low pressure chemical vapor deposition) method; in the deposition step, dichlorosilane, silane and hydrogen chloride are used as reaction gases, phosphine is used as a doping gas, and hydrogen and nitrogen are used as protective gases. The reaction pressure is controlled at 300-600Torr, and the reaction temperature is controlled at 600-720 ℃.

The semiconductor structure with the phosphorus-doped silicon epitaxial layer 100 that has just been formed is then transferred to a precursor solution in which the phosphorus-containing complex molecules are dissolved. In a solution system, complex molecules form a closely arranged complex monomolecular layer 101 on the surface of the silicon epitaxial layer 100 due to the balance of steric hindrance and intermolecular interaction force, and the formed structure is shown in fig. 1.

Finally, the structure shown in fig. 1 is subjected to rapid thermal annealing, so that phosphorus atoms in the complex monolayer 101 diffuse into the silicon epitaxial layer 101 until equilibrium is reached.

The doping concentration of phosphorus in the epitaxial layer obtained by the method is slightly improved, but the improvement effect is difficult to meet the requirement of reducing the source-drain contact resistance because the total amount of phosphorus atoms of the monomolecular layer of the complex is limited. In order to further improve the doping concentration of phosphorus atoms in the epitaxial layer, the invention provides a method for preparing the epitaxial layer.

The embodiment first provides a preparation method of a high-concentration phosphorus-doped silicon epitaxial layer, which comprises the following steps:

Referring to fig. 2, a silicon epitaxial layer 200 with phosphorus doping is first formed by epitaxial growth on the already formed semiconductor structure; the formation process of the silicon epitaxial layer can be realized by a conventional LPCVD process of in-situ doping or post-doping, which is not described herein again.

then, a complex polymer layer 201 is formed on the surface of the silicon epitaxial layer 200, and in this embodiment, the central atom of the complex used is phosphorus and the ligand is a porphyrin derivative. Due to the fact that porphyrin rings of different complex molecules have strong pi-pi interaction, the complex molecules can form a stable multi-molecular-layer structure. In addition, the strong pi-pi interaction can also enable the continuously deposited complexes to be arranged in an edge-on mode, and the compactness of the film layer is improved.

In the present invention, the side-standing arrangement means an arrangement in which a molecular plane and a substrate plane have a certain inclination angle; and face-on refers to an arrangement in which the molecular planes are parallel to the substrate plane.

In this embodiment, a gas phase atomic layer deposition process is used to assemble and form the polymolecular layer 201 on the surface of the silicon epitaxial layer 200. Vapor phase atomic layer deposition may employ an apparatus as shown in fig. 3, the deposition method comprising the steps of: first, the precursor is dissolved in a toluene solution and loaded in a bubbling device 301, and then nitrogen gas 302 is bubbled into the solution system to obtain an aerosol or spray of the solution, and the aerosol or spray is further introduced into a reaction chamber 306 through a gas distribution device 303.

In the reaction chamber 306, the silicon wafer 304 to be deposited with the multi-molecular layer is placed on the supporting platform 305, and the reaction chamber 306 is connected with a vacuum pumping device to control the pressure inside the chamber body, in this embodiment, the temperature inside the reaction chamber is near room temperature, preferably 20-25 ℃, and the internal pressure is maintained at 20-100 mTorr. This atmospheric pressure scope can control the molecular layer and grow with suitable speed, and the too fast one side of growth rate can make thickness be difficult to control, and the one side can make the polymolecular layer compactness that obtains relatively poor, influences the even degree of phosphorus atom concentration distribution in the silicon epitaxial layer that follow-up diffusion step obtained, and too slow growth rate can influence efficiency, reduces the productivity.

Finally, rapid thermal annealing is performed to decompose and diffuse phosphorus in the complex polymer layer 201 into the silicon epitaxial layer 200. The phosphorus doping concentration in the silicon epitaxial layer after diffusion annealing can be greatly improved compared with the process of the monolayer conformal doping. Through the manner, in the preparation method of the epitaxial layer provided by the embodiment, the phosphorus-containing complex polymolecular layer 201 is firstly deposited on the surface of the silicon epitaxial layer 200, and then phosphorus atoms in the polymolecular layer 201 are diffused into the silicon epitaxial layer 200 by using rapid thermal annealing, so that the phosphorus doping concentration of the silicon epitaxial layer 200 is improved.

In other embodiments of the invention, the complexes employed have the structure shown in formula (I):

The preparation method comprises the following steps of preparing a silicon epitaxial layer, preparing a porphyrin derivative, preparing a base material, wherein R ₁ is independently selected from phenyl, biphenyl, naphthyl or anthryl, the group is used as R ₁, the conjugated structure of the porphyrin derivative can be expanded, the acting force of pi-pi bonds among molecules can be improved, and a more stable multi-molecular-layer structure can be formed, R ₂ is independently selected from hydrogen, hydroxyl or C1-C6 alkyl, at least one R ₂ is hydroxyl, and the group selection of R ₂ is considered to be that the hydroxyl reacts with silicon oxygen bonds on the silicon epitaxial layer, so that the molecules can be.

The embodiment also provides a preparation method of the fin field effect transistor, which comprises the following steps:

Referring to fig. 4, a substrate 400 is provided, a plurality of discrete fins 401 are formed on the substrate 400, and an isolation layer 402 is formed on the surface of the substrate 400, wherein the surface of the isolation layer 402 is lower than the top surface of the fins 401 and covers part of the sidewalls of the fins 401.

The substrate 400 may be bulk silicon or silicon-on-insulator (SOI), the substrate 400 may also be germanium, silicon-germanium, gallium arsenide, or germanium-on-insulator, and the material of the substrate 400 in this embodiment is bulk silicon. The bulk silicon substrate is adopted as the substrate, so that the cost for forming the fin field effect transistor can be reduced, and the manufacturing process is compatible with the existing manufacturing process of the planar transistor.

The substrate 400 includes an N-type region (I-region) for forming an N-type fin field effect transistor and a P-type region (II-region) for forming a P-type fin field effect transistor.

In this embodiment, the fin portion 401 is formed by patterning the semiconductor. Specifically, a patterned mask layer for defining the fin portion 401 is formed on the substrate 400, and then the semiconductor substrate is etched by using the patterned mask layer as a mask, so that the fin portion 401 is formed.

The isolation layer 402 may be made of an insulating dielectric material such as silicon oxide, silicon nitride, or silicon oxycarbide, and the isolation layer 402 serves as an isolation structure between adjacent fins 401 and an isolation structure between a gate structure of the finfet and the semiconductor substrate.

Referring to fig. 5, a gate structure is formed, the gate structure includes a gate oxide layer 403 and a gate 404, and the gate oxide layer 403 and the gate 404 are covered on the sidewalls and the top of a portion of the fin;

In this embodiment, the isolation layer 402 of the N-type region II and the P-type region I are both formed with gate structures. Specifically, the gate oxide layer 403 is silicon oxide or a high-k gate dielectric material, such as hafnium oxide, and the gate layer 404 is polysilicon or a metal material, where the metal material includes one or more of Ti, Ta, TiN, TiAl, Cu, Al, W, Ag, or Au.

In other embodiments of the present invention, the gate structure is a dummy gate structure, the dummy gate structure is subsequently removed, and then a metal gate structure of a semiconductor device is formed again at a position where the gate structure is located, where the gate structure is a single-layer or stacked structure, the gate structure includes a dummy gate layer, or the gate structure includes a dummy gate oxide layer and a dummy gate layer located on a surface of the dummy gate oxide layer, where the dummy gate layer is made of polysilicon or amorphous carbon, and the dummy gate oxide layer is made of silicon oxide or silicon oxynitride.

the subsequent process steps further comprise: forming an offset side wall on the surface of the side wall of the grid structure; lightly doping the fin parts 401 on two sides of the grid structure of the N-type region I by taking the offset side wall of the N-type region I as a mask to form an N-type source drain lightly doped region; and lightly doping the fin parts 401 at two sides of the gate structure of the P-type region II by taking the offset side walls of the P-type region II as masks to form a P-type source drain lightly doped region.

referring to fig. 6, a hard mask layer 405 is formed on the sidewall of the fin 401 not covered by the gate structure, the active structure of the P-type region II is protected by the patterning layer 406 to prevent the active structure from being affected in the subsequent process steps, the fin 401 and the hard mask layer 405 of the N-type region I are etched to a certain thickness to form a groove, and a phosphorus-doped silicon epitaxial layer 407 is grown in the groove.

fig. 5 and 6 are schematic cross-sectional views of the same three-dimensional structure cut along different cut lines, where fig. 6 is a cross-sectional view of a portion of the fin 401 not covered with the gate structure, taken along a direction perpendicular to an extending direction of the fin 401.

In this embodiment, the hard mask layer 405 is made of silicon nitride, silicon oxide, boron nitride, or silicon oxynitride, and the patterning layer 406 is made of a photoresist material.

And growing the phosphorus-doped silicon epitaxial layer by adopting a low-pressure chemical vapor deposition method, wherein reaction gases adopted by the low-pressure chemical vapor deposition method are dichlorosilane, silane, hydrogen and hydrogen chloride, phosphine is used as in-situ doped doping gas, and nitrogen is used as protective gas and carrier gas. The pressure of the chamber during the reaction is 300-600Torr, and the temperature of the chamber is 600-720 ℃.

In other embodiments of the present invention, the N-type region I may be protected by a photoresist, and then the growth of the silicon epitaxial layer in the N-type region I is completed after the silicon epitaxial layer (e.g., germanium-doped silicon epitaxial layer) of the P-type region II is formed.

Referring to fig. 7, a complex polymolecular layer 408 is formed on the surface of the silicon epitaxial layer 407, and the complex molecules used in the present embodiment are complex molecules formed by coordination of hydroxy-phenyl-porphyrin shown as formula (II) with phosphorus, and are hereinafter referred to as hydroxy-phenyl-phosphorus porphyrin.

the complex molecules adopted by the embodiment are hydroxyl-phenyl-phosphorus porphyrin complexes shown as a formula (II). The use of the complex molecule can bring the following benefits: firstly, the molecular structure is small, and the molecular structure can be dissolved in organic solutions such as toluene and the like, so that the molecular structure is convenient to disperse into mist-shaped aerosol; strong pi-pi bond interaction can be formed among porphyrin rings, and the conjugated structure is further expanded by the p-phenyl group, so that the pi-pi bond interaction is enhanced, and thus, complex molecules can form a stable polymolecular layer structure; in addition, the hydroxyl-phenyl-phosphorus porphyrin molecules are arranged in a side-standing mode when being deposited on the surface of the silicon epitaxial layer, so that the compactness of the film layer is improved; furthermore, the decomposition temperature of the hydroxy-phenyl-phosphoporphyrin molecule is 400-600 ℃, and the subsequent rapid thermal annealing step can be conveniently carried out in the proper temperature range.

It should be noted that, although fig. 7 shows the arrangement of the phosphorus-porphyrin complex polymolecular layer 408 on the surface of the silicon epitaxial layer 407, the relative ratio of the sizes of the polymolecular layer 408 and the silicon epitaxial layer 407 in the drawing does not represent the thickness ratio of the polymolecular layer 408 and the silicon epitaxial layer 407 in actual cases, and the angle between the polymolecular layer 408 and the surface of the epitaxial layer is only schematic.

In this embodiment, the hydroxyl-phenyl-phosphoporphyrin complex macromolecular layer 408 is also prepared by a vapor atomic layer deposition method, and the deposition process may use the same or similar apparatuses and steps as those in the first embodiment, which are not described herein again.

With reference to fig. 8, in order to prevent phosphorus atoms in the hydroxyl-phenyl-phosphorus porphyrin complex macromolecular layer 408 from diffusing to other parts in the subsequent rapid thermal annealing process and ensure the effect of increasing the phosphorus doping concentration, a covering protection layer 409 needs to be arranged to wrap the outer side of the existing complex macromolecular layer 408, the covering protection layer 409 is made of silicon nitride, silicon oxynitride, silicon carbide or boron nitride, and in this embodiment, silicon nitride is used; the protective cover layer 409 is formed using an atomic layer deposition process.

^{20 21 3 21 3}And then carrying out rapid thermal annealing on the semiconductor structure, wherein the rapid thermal annealing step in the embodiment adopts uniform temperature annealing within a temperature range of 400-600 ℃ corresponding to the decomposition temperature of the complex molecules, the annealing time is 1-100 seconds, and the rapid thermal annealing step can diffuse phosphorus atoms in the complex multi-molecular layer 408 into the silicon epitaxial layer 407 after decomposition at 400-600 ℃ so as to improve the doping concentration of the phosphorus atoms in the silicon epitaxial layer 407.

After the rapid thermal annealing step is completed, the excess capping protective layer 409 is removed using phosphoric acid, resulting in the structure shown in fig. 9. The etching liquid adopted by the etching treatment is phosphoric acid solution, the concentration of phosphoric acid in the phosphoric acid solution is 75-85%, and the temperature of the solution is 80-200 ℃. In order to make the etching rate of the etching step small, suspended particles, such as nano silica particles, may be added to the phosphoric acid solution.

In this embodiment, the source and drain regions are formed by an in-situ doped epitaxial process. In other embodiments of the present invention, the source and drain regions may also be formed by a source and drain implantation method. The activation of the phosphorus atoms is completed in the subsequent source-drain annealing step, so that the process flow is simplified, and the manufacturing cost is reduced.

the foregoing detailed description of the preferred embodiments of the invention has been presented. It should be understood that numerous modifications and variations could be devised by those skilled in the art in light of the present teachings without departing from the inventive concepts. Therefore, the technical solutions available to those skilled in the art through logic analysis, reasoning and limited experiments based on the prior art according to the concept of the present invention should be within the scope of protection defined by the claims.