阅读说明：本技术 一种电荷泵电路的四相过流检测保护电路及其实现方法 (Four-phase overcurrent detection protection circuit of charge pump circuit and implementation method thereof ) 是由 魏郅 马俊 于 2019-09-11 设计创作，主要内容包括：本发明公开了一种电荷泵电路的四相过流检测保护电路及其实现方法,主要解决电荷泵运行过程中突然短路,VX或者VY电压突然被短路到地或者电源,CFLY电容的顶极板或底极板突然被短路到地或者电源引起瞬间大电流而损坏功率管的问题。该电路包括与电荷泵芯片的NMOS管Q2相连的NMOS管Q2_SNS_REV、NMOS管Q2_SNS_FWD,与电荷泵芯片的NMOS管Q3相连的NMOS管Q3_SNS_REV、NMOS管Q3_SNS_FWD,以及比较器MOS_OCP_REV和比较器MOS_OCP_FWD。通过上述设计,本发明中比较器的输入电压没有大幅度的跳变,不需要屏蔽,意味着可以在电路过流的第一时间就可以检测到,速度相应更快。同时,这样既方便了电路实现,抗干扰能力也强。因此,具有很高的使用价值和推广价值。(The invention discloses a four-phase over-current detection protection circuit of a charge pump circuit and an implementation method thereof, and mainly solves the problems that a charge pump is suddenly short-circuited in the operation process, VX or VY voltage is suddenly short-circuited to the ground or a power supply, and a top plate or a bottom plate of a CFLY capacitor is suddenly short-circuited to the ground or the power supply causes instantaneous large current to damage a power tube. The circuit comprises an NMOS tube Q2_ SNS _ REV and an NMOS tube Q2_ SNS _ FWD which are connected with an NMOS tube Q2 of the charge pump chip, an NMOS tube Q3_ SNS _ REV and an NMOS tube Q3_ SNS _ FWD which are connected with an NMOS tube Q3 of the charge pump chip, and a comparator MOS _ OCP _ REV and a comparator MOS _ OCP _ FWD. Through the design, the input voltage of the comparator does not jump to a large extent, shielding is not needed, the comparator can be detected at the first time of overcurrent of a circuit, and the speed is correspondingly higher. Meanwhile, the circuit is convenient to realize, and the anti-interference capability is strong. Therefore, the method has high use value and popularization value.)

1. a four-phase over-current detection protection circuit of a charge pump circuit, comprising an NMOS tube Q2_ SNS _ REV and an NMOS tube Q2_ SNS _ FWD, each of which has a gate G connected to a gate G of an NMOS tube Q2 of a charge pump chip, an NMOS tube Q3_ SNS _ REV and an NMOS tube Q3_ SNS _ FWD, each of which has a gate G connected to a gate G of an NMOS tube Q3 of the charge pump chip, a comparator MOS _ OCP _ REV having a cathode connected to a drain D of a source S, NMOS tube Q3_ SNS _ REV of the NMOS tube Q2_ SNS _ REV and an anode connected to a VY pin of the charge pump chip, a comparator MOS _ OCP _ FWD having an anode connected to a source S, NMOS tube Q2_ SNS _ REV and a cathode connected to a drain D of a Q3_ SNS _ FWD of the NMOS tube Q539 _ REF and a cathode connected to a VY pin of the charge pump chip, a comparator MOS _ OCP _ FWD having one end connected to a cathode connected to a charge pump pin of the other end of the comparator MOS _ OCP _ REV and a charge pump chip, a charge pump current source of the charge pump chip, and a charge pump chip VXI _ OCP _ FWD, and, parasitic diodes D1 and D2 connected between the positive and negative of the comparator MOS _ OCP _ REV in parallel, and parasitic diodes D3 and D4 connected between the positive and negative of the comparator MOS _ OCP _ FED in parallel; the parasitic diodes D1 and D2 are connected in parallel and have opposite poles, and the parasitic diodes D3 and D4 are connected in parallel and have opposite poles.

2. The four-phase over-current detection protection circuit of claim 1, wherein the size of the NMOS transistors Q2_ SNS _ REV, Q2_ SNS _ FWD is 1/N of the size of Q2.

3. the method for implementing the four-phase over-current detection protection circuit of the charge pump circuit as claimed in any one of claims 1 or 2, comprising the steps of:

(S1) pulling the voltage of the connection node VREF _ REV between the cathode of the comparator MOS _ OCP _ REV and Q2_ SNS _ REV, Q3_ SNS _ REV to a voltage higher than CFH with the current source I _ REF 1;

(S2) comparing the voltage of VY with the voltage of VREF _ REV using a comparator MOS _ OCP _ REV;

(S3) determining the overcurrent condition of the reverse current when the charge pump chips Q2 and Q4 are in the on-phase according to the comparison result;

(S4) pulling the voltage of the connection node VREF _ FED between the positive electrode of the comparator MOS _ OCP _ FED and Q2_ SNS _ FED, Q3_ SNS _ FED to a voltage lower than CFL with the current source I _ REF 2;

(S5) comparing the voltage of VY with VREF _ FED using a comparator MOS _ OCP _ FED;

(S6) determining the overcurrent condition of the forward current when the charge pump chips Q2 and Q4 are in the on-phase according to the comparison result.

4. The method of claim 3, wherein in step (S3), if the VY voltage is lower than the VREF _ REV voltage, the current indicating that the Q2 tube is forward or reverse is smaller than I _ REF 1N; if the VY voltage is equal to the VREF _ REV voltage, the Q2 tube is indicated to flow the reverse current I _ REF1 xN; if the VY voltage is higher than VREF _ REV voltage, the reverse current of the Q2 tube is larger than I _ REF 1N, and at the moment, the comparator is overturned, and the error is reported to be 'Q2/Q4 conduction phase, and the reverse current is overcurrent'; the positive direction indicates that current flows from the drain D to the source S of the power transistor, and the negative direction indicates that current flows from the source S to the drain D of the power transistor.

5. The method of claim 4, wherein in step (S6), if the VY voltage is higher than the VREF _ FWD voltage, it indicates that Q2 is reverse conduction current or forward conduction current is less than I _ REF 2N; if the VY voltage is equal to the VREF _ FWD voltage, the current indicating that Q2 is conducting in the forward direction is equal to I _ REF2 × N; if the VY voltage is lower than VREF _ FWD voltage, it indicates that Q2 is conducting current greater than I _ REF2 × N, and the comparator flips to report "Q2/Q4 conducting phase, forward current is over-current".

6. the method of claim 5, wherein the detecting of the over-current in the conducting phase of the Q1 and Q3 tubes is the same as the detecting of the over-current in the conducting phase of the Q2 and Q4 tubes.

Technical Field

The invention relates to an overcurrent detection circuit, in particular to a four-phase overcurrent detection protection circuit of a charge pump circuit and an implementation method thereof.

Background

Charge pumps are switching converters that store energy using capacitors, wherein the capacitors are switched between a supply and a discharge state using switches, so that the supply voltage can be raised or lowered. In a mobile terminal or a portable electronic device, the voltage of the power supply may be lower than the operating voltage, and the charge pump may provide the voltage of the power supply to operate the system, for example, the voltage generated by the charge pump is in a range of 3.3V to 4.0V, so as to meet the operating requirement of the electronic device.

As shown in fig. 1, which is a schematic circuit diagram of the charge pump, four power tubes are divided into two phases Φ 1 and Φ 2, and are respectively turned on, and in an ideal case of no load, VX is 2 × VY. The most common application is to use VX as the input power source, resulting in approximately half the output voltage VY. Similarly, if VY is used as the input power, then approximately twice the output voltage VX will be obtained.

When the ideal charge pump works in a steady state, V _ CFLY (V _ COUT) and VY (VX/2) are set. However, if there is any sudden change in these voltages during operation, because the on-resistance of the power transistor is very small, a very large current will be instantaneously generated, which is enough to burn out the chip and pull down the power supply.

the voltage of some nodes is suddenly changed due to many reasons, such as that the CFLY capacitor is suddenly short-circuited during operation, the VX or VY voltage is suddenly short-circuited to ground or power, the top plate or bottom plate of the CFLY capacitor is suddenly short-circuited to ground or power, and so on. If these conditions occur, they result in momentary high currents, which requires the charge pump circuit to be able to check these high currents and immediately shut down the power tube to ensure safety.

Firstly, because the charge pump circuit has two phases during operation, Q1/Q3 is conducted and Q2/Q4 is conducted; in addition, the charge pump current may be bi-directional, with steady state current flowing from VX to VY if VX >2 x VY, and from VY to VX if VX <2 x VY.

There are four current paths:

A. Positive direction Q1/Q3 is on, VX- > Q1 drain to source- > CFLY- > Q3 source to drain- > VY;

B. the positive direction Q2/Q4 is conducted, and the CFLY top plate- > Q2 drain-to-source- > VY- > Q4 source-to-drain- > CFLY bottom plate;

C. reverse Q1/Q3 conduction, VY- > Q3 drain to source- > CFLY- > Q1 source to drain- > VX;

D. Reverse Q2/Q4 conduction, VY- > Q2 source to drain- > CFLY- > Q4 drain to source.

Therefore, four-phase overcurrent protection is required for the charge pump circuit.

disclosure of Invention

The invention aims to provide a four-phase overcurrent detection protection circuit of a charge pump circuit and an implementation method thereof, which mainly solve the problems that a charge pump is suddenly short-circuited in the operation process, VX or VY voltage is suddenly short-circuited to the ground or a power supply, and a top plate or a bottom plate of a CFLY capacitor is suddenly short-circuited to the ground or the power supply causes instantaneous large current to damage a power tube.

In order to achieve the purpose, the technical scheme adopted by the invention is as follows:

A four-phase over-current detection protection circuit of a charge pump circuit comprises an NMOS tube Q2_ SNS _ REV and an NMOS tube Q2_ SNS _ FWD, the gates G of which are connected to the gate G of an NMOS tube Q2 of a charge pump chip, an NMOS tube Q3_ SNS _ REV and an NMOS tube Q3_ SNS _ FWD, the gates G of which are connected to the gate G of an NMOS tube Q3 of the charge pump chip, a comparator MOS _ OCP _ REV, the cathode of which is connected to the drain D of a source S, NMOS tube Q3_ SNS _ REV of the NMOS tube Q2_ SNS _ REV and the anode of which is connected to a VY pin of the charge pump chip, a comparator MOS _ OCP _ FWD, the anode of which is connected to the source S, NMOS tube Q3_ SNS _ REF _ FWD of the NMOS tube Q2_ SNS _ FWD and the cathode of which is connected to the drain D of the charge pump chip VY pin, a MOS _ OCP _ FWD, a charge pump chip, the other end of which is connected to the negative pole of which is connected to a charge pump chip VXI pin of which is connected to the charge pump chip, and a charge pump chip of which is connected to the charge pump chip, and a, parasitic diodes D1 and D2 connected between the positive and negative of the comparator MOS _ OCP _ REV in parallel, and parasitic diodes D3 and D4 connected between the positive and negative of the comparator MOS _ OCP _ FED in parallel; the parasitic diodes D1 and D2 are connected in parallel and have opposite poles, and the parasitic diodes D3 and D4 are connected in parallel and have opposite poles.

further, the size of the NMOS transistors Q2_ SNS _ REV and Q2_ SNS _ FWD is 1/N of the size of Q2.

Based on the four-phase overcurrent detection protection circuit of the charge pump circuit, the invention also provides an implementation method of the four-phase overcurrent detection protection circuit of the charge pump circuit, which comprises the following steps:

(S1) pulling the voltage of the connection node VREF _ REV between the cathode of the comparator MOS _ OCP _ REV and Q2_ SNS _ REV, Q3_ SNS _ REV to a voltage higher than CFH with the current source I _ REF 1;

(S2) comparing the voltage of VY with the voltage of VREF _ REV using a comparator MOS _ OCP _ REV;

(S3) determining the overcurrent condition of the reverse current when the charge pump chips Q2 and Q4 are in the on-phase according to the comparison result;

(S4) pulling the voltage of the connection node VREF _ FED between the positive electrode of the comparator MOS _ OCP _ FED and Q2_ SNS _ FED, Q3_ SNS _ FED to a voltage lower than CFL with the current source I _ REF 2;

(S5) comparing the voltage of VY with VREF _ FED using a comparator MOS _ OCP _ FED;

(S6) determining the overcurrent condition of the forward current when the charge pump chips Q2 and Q4 are in the on-phase according to the comparison result.

Specifically, in step (S3), if the VY voltage is lower than the VREF _ REV voltage, the current indicating that the Q2 tube is in the forward direction or the reverse direction is less than I _ REF1 × N; if the VY voltage is equal to the VREF _ REV voltage, the Q2 tube is indicated to flow the reverse current I _ REF1 xN; if the VY voltage is higher than VREF _ REV voltage, the reverse current of the Q2 tube is larger than I _ REF 1N, and at the moment, the comparator is overturned, and the error is reported to be 'Q2/Q4 conduction phase, and the reverse current is overcurrent'; the positive direction indicates that current flows from the drain D to the source S of the power transistor, and the negative direction indicates that current flows from the source S to the drain D of the power transistor.

Specifically, in step (S6), if the VY voltage is higher than the VREF _ FWD voltage, it indicates that Q2 is reverse conduction current or forward conduction current is less than I _ REF2 × N; if the VY voltage is equal to the VREF _ FWD voltage, the current indicating that Q2 is conducting in the forward direction is equal to I _ REF2 × N; if the VY voltage is lower than VREF _ FWD voltage, it indicates that Q2 is conducting current greater than I _ REF2 × N, and the comparator flips to report "Q2/Q4 conducting phase, forward current is over-current".

Furthermore, the overcurrent detection of the conduction phases of the Q1 and Q3 tubes is the same as the overcurrent detection method of the conduction phases of the Q2 and Q4 tubes.

compared with the prior art, the invention has the following beneficial effects:

(1) in the invention, the voltage of the middle point of the power tubes Q2 and Q3 is unchanged, so the input voltage of the comparator has no large jump (which is important, if the input voltage has the large jump, the operation of the comparator is influenced, the time needs to be shielded for the consideration of false triggering, the shielded time comparator does not work, the shielding time is usually conservative, and the time longer than the jump is ensured). No shielding is required, meaning that it can be detected at the first time of overcurrent, with a correspondingly faster rate. Meanwhile, the circuit is convenient to realize, and the anti-interference capability is strong.

(2) according to the invention, through adding the sense tubes Q2_ SNS _ REV and Q3_ SNS _ REV of the power tubes Q2 and Q3 and the size of the sense tube is 1/N of that of the power tube, if the voltage drop of the sense tube is the same as that of the power tubes Q2 and Q3, the current flowing through the sense tube Q2/Q3 is N times of the current flowing through the sense tube, so that the over-current detection is facilitated.

(3) The invention skillfully maintains the connection relationship of Q2_ SNS _ REV and Q3_ SNS _ REV similar to Q2 and Q3. For two phases (Q2 conducting phase and Q3 conducting phase) in one current direction (forward direction or reverse direction), the same comparator and the same reference current can be multiplexed, so that the cost is saved, and the power consumption of the circuit is reduced.

(4) In practical applications, there is a dead time for Q2/Q3. And in dead time, all the tubes are turned off, and the clamp is required to be clamped by the diode. In the circuit of the invention, when the dead time voltage is clamped, the two comparators do not report errors, the result of the comparators does not need to be shielded, and the comparators can react at the first time when overcurrent is proved, thereby further improving the anti-interference capability of the system.

Drawings

Fig. 1 is a schematic diagram of a charge pump.

Fig. 2 is a schematic circuit diagram of the present invention.

FIG. 3 is a schematic diagram of the critical node voltage during normal forward operation of the charge pump.

FIG. 4 is a schematic diagram of the critical node voltage during reverse normal operation of the charge pump.

Detailed Description

The present invention will be further described with reference to the following description and examples, which include but are not limited to the following examples.