阅读说明：本技术 脉冲信号输出电路 (Pulse signal output circuit ) 是由 岩野阳一 于 2019-05-24 设计创作，主要内容包括：本发明涉及脉冲信号输出电路。该脉冲信号输出电路包括：脉冲变压器,包括初级线圈和次级线圈；开关部,切换初级侧电流的作用方向；初级侧电容器,布置在初级侧电流的路径上；整流部,对在次级线圈上感应的次级侧电压进行整流并输出整流电压；次级侧电容器,通过整流电压充电并释放电荷；晶体管,根据次级侧电容器的电压接通和断开；及切换时序控制器,控制开关部切换初级侧电流的作用方向的时序,其中,切换时序控制器进行控制,以当初级侧电压振荡且改变为与初级侧电压在开关部的一个切换周期的开始时刻的极性相反的极性时,切换初级侧电流的作用方向。本发明能够提高从脉冲变压器的初级侧到次级侧的电力传输效率。(The present invention relates to a pulse signal output circuit. The pulse signal output circuit includes: a pulse transformer including a primary coil and a secondary coil; a switching unit that switches the direction of action of the primary-side current; a primary side capacitor arranged on a path of the primary side current; a rectifying unit configured to rectify a secondary side voltage induced in the secondary coil and output a rectified voltage; a secondary side capacitor that is charged by the rectified voltage and discharges electric charge; a transistor which is turned on and off according to a voltage of the secondary side capacitor; and a switching timing controller controlling a timing at which the switching section switches an acting direction of the primary side current, wherein the switching timing controller controls to switch the acting direction of the primary side current when the primary side voltage oscillates and changes to a polarity opposite to a polarity of the primary side voltage at a start timing of one switching cycle of the switching section. The present invention can improve the power transmission efficiency from the primary side to the secondary side of the pulse transformer.)

1. a pulse signal output circuit for outputting a pulse signal based on a current supplied from a DC power supply connected to the pulse signal output circuit, the pulse signal output circuit comprising:

A pulse transformer including a primary coil and a secondary coil;

A switching unit for switching a direction of action of the current as a primary side current on the primary coil of the pulse transformer;

A primary side capacitor arranged on a path of the primary side current;

A rectifying section for rectifying a secondary-side voltage induced on the secondary coil based on a primary-side voltage applied to the primary coil in accordance with the primary-side current, and outputting the rectified voltage;

A secondary side capacitor that is charged by the rectified voltage and discharges a charge;

A transistor that is turned on and off according to a voltage of the secondary side capacitor; and

A switching timing controller which controls a timing at which the switching section switches the acting direction of the primary side current,

Wherein the switching timing controller is configured to control to switch the acting direction of the primary side current when the primary side voltage oscillates due to series resonance of the primary coil and the primary side capacitor and changes to a polarity opposite to a polarity of the primary side voltage at a start timing of one switching cycle of the switching section.

2. The pulse signal output circuit according to claim 1,

The switching timing controller is configured to control to switch the acting direction of the primary side current at a timing at which oscillation of the primary side voltage has a peak of the opposite polarity.

3. The pulse signal output circuit according to claim 2,

The switching timing controller is configured to control to switch the acting direction of the primary side current at a timing at which the oscillation of the primary side voltage has a first peak of the opposite polarity after the start timing.

4. The pulse signal output circuit according to any one of claims 1 to 3,

The switching time representing the moment of switching the acting direction of the primary side current is predetermined and

The switching timing controller is configured to measure an elapsed time from the start timing, and to control to switch the acting direction of the primary-side current at a timing at which the measured elapsed time reaches the switching time set in advance.

5. The pulse signal output circuit according to claim 4,

The switching time is a time calculated in advance based on an inductance value of the primary coil and a capacitance value of the primary side capacitor.

6. The pulse signal output circuit according to claim 3,

The switching timing controller further includes a timing detection circuit configured to acquire a voltage value of the primary side voltage and detect a timing of switching the acting direction of the primary side current based on the acquired voltage value, and

The switching timing controller is configured to control to switch the acting direction of the primary side current when the timing detection circuit detects a timing of switching the acting direction of the primary side current.

7. the pulse signal output circuit according to any one of claims 1 to 3, further comprising:

A primary side resistance configured to suppress oscillations of the primary side voltage, the oscillations being caused by the series resonance.

8. The pulse signal output circuit according to any one of claims 1 to 3,

The switching section includes an output voltage selection circuit configured to: outputting a reference voltage or a DC voltage supplied from the DC power supply according to control for switching the acting direction of the primary side current by the switching timing controller.

9. The pulse signal output circuit according to any one of claims 1 to 3,

The rectifying section is a bridge rectifier circuit having a bridge circuit including four diodes.

10. The pulse signal output circuit according to any one of claims 1 to 3,

the rectifying section is a voltage-doubler rectifying circuit including one capacitor and two diodes.

Technical Field

the present invention relates to a pulse signal output circuit.

Background

A pulse signal output circuit for generating a pulse signal and outputting the pulse signal has been used in various applications. For example, in japanese patent application laid-open No. 2013-222978 (hereinafter referred to as patent document 1), a technique of a pulse signal output circuit is disclosed: can be used to send out by means of a pulse signal the number of treatments measured by a site indicator installed at the machining site. The pulse signal output circuit disclosed in patent document 1 includes a switching section, a primary side capacitance, a pulse transformer, a rectifying section, a secondary side capacitance, a resistor, and a Field Effect Transistor (FET). In addition, the pulse signal output circuit disclosed in patent document 1 generates a pulse signal by turning on or off each switch included in a switch section connected to a DC power supply, and outputs the pulse signal.

Specifically, in the pulse signal output circuit disclosed in patent document 1, in order to switch the pulse signal to be output to a low level, each switch included in the switch section is turned on or off so that the current output from the DC power supply acts on the primary side of the pulse transformer through the primary side capacitor. In this case, in the pulse signal output circuit disclosed in patent document 1, a current applied to the primary side excites a pulse transformer, whereby a voltage is induced between both ends of the secondary coil due to a voltage between both ends of the primary coil. Thereafter, in the pulse signal output circuit disclosed in patent document 1, the voltage induced on the secondary side by the pulse transformer is full-wave rectified by the rectifying section, and acts between the gate and the source of the FET and between both ends of each of the secondary side capacitance and the resistor. Therefore, in the pulse signal output circuit disclosed in patent document 1, by the voltage subjected to full-wave rectification, the secondary side capacitance changes, and the FET turns on, and the pulse signal transitions to a low level. In the pulse signal output circuit disclosed in patent document 1, if a switch included in a switch unit provided ON the primary side of the pulse transformer is switched from an OFF state to an ON state, a large amount of current flows in a secondary side circuit of the pulse transformer for a short time. After that, the current flowing in the secondary side circuit decreases and becomes 0A. Therefore, in the pulse signal output circuit disclosed in patent document 1, the voltage acting between the gate and the source of the FET and between both ends of each of the secondary side capacitance and the resistor also decreases. However, in the pulse signal output circuit disclosed in patent document 1, if the current flowing in the secondary side circuit of the pulse transformer becomes 0A, the charge stored in the secondary side capacitance is discharged, and then the FET is held in the ON state, and the pulse signal is also held at the low level.

Further, in the pulse signal output circuit disclosed in patent document 1, the switch section is configured to be switched on or off so that the direction of action of the current output from the DC power supply to the primary side of the pulse transformer is reversed. More specifically, in the pulse signal output circuit disclosed in patent document 1, the switching section has a switch for applying a positive current (hereinafter referred to as "positive switch"), and a switch for applying a negative current (hereinafter referred to as "negative switch"). Also, in the pulse signal output circuit disclosed in patent document 1, switching of each of the positive-direction switch and the negative-direction switch between the ON state and the OFF state is exclusively (complementarily) controlled. In other words, in the pulse signal output circuit disclosed in patent document 1, when the positive switch is switched on, the negative switch is switched off, thereby applying a positive current to the primary side of the pulse transformer, and when the negative switch is switched on, the positive switch is switched off, thereby applying a negative current to the primary side of the pulse transformer. Therefore, in the pulse signal output circuit disclosed in patent document 1, when the switching section applies a negative current to the primary side of the pulse transformer, a reverse voltage is induced between both ends of the secondary coil in the pulse transformer. Therefore, in the pulse signal output circuit disclosed in patent document 1, the direction of the current flowing through the secondary side of the pulse transformer is also reversed.

However, in the pulse signal output circuit disclosed in patent document 1, since the voltage induced at the secondary side is full-wave rectified by the rectifying section, even if a reverse voltage is induced at the secondary side of the pulse transformer, a voltage in the same state as that when the switching section applies a forward current to the primary side of the pulse transformer is applied between both ends of each of the secondary side capacitor and the resistor. In other words, in the pulse signal output circuit disclosed in patent document 1, even if the pulse transformer causes a reverse voltage to be induced on the secondary side of the pulse transformer, the voltage between the gate and the source of the FET rises. Therefore, in the pulse signal output circuit disclosed in patent document 1, even if the switching section applies a negative current to the primary side of the pulse transformer, the FET is maintained in the ON state, and the pulse signal is maintained at the low level.

Meanwhile, in the pulse signal output circuit disclosed in patent document 1, in order to switch the pulse signal to a high level, the state of the switch included in the switch section is maintained as it is. Then, in the pulse signal output circuit disclosed in patent document 1, the voltage induced on the secondary side by the pulse transformer is kept constant without change. In other words, in the pulse signal output circuit disclosed in patent document 1, the direction of the voltage induced on the secondary side of the pulse transformer is fixed to either one of the positive direction and the negative direction, and the direction of the current is also fixed to one direction. Therefore, in the pulse signal output circuit disclosed in patent document 1, if the current flowing in the secondary side circuit of the pulse transformer becomes 0A and all the charges stored in the secondary side capacitor are discharged, the FET switches off and the pulse signal transitions to a high level.

As described above, in the pulse signal output circuit disclosed in patent document 1, each of the switches included in the switch section connected to the DC power supply is switched on or off, whereby the FET is switched on or off. Thus, a pulse signal is generated.

In addition, as in the pulse signal output circuit disclosed in patent document 1, the primary side and the secondary side are insulated from each other in a direct current manner by a pulse transformer. The primary side and the secondary side of the pulse transformer are combined in an alternating current manner. Therefore, when the AC coupling degree is low, the amount of power transmitted from the primary side to the secondary side of the pulse transformer is small. Therefore, it is necessary to improve the power transmission efficiency from the primary side to the secondary side.

However, in the pulse signal output circuit disclosed in patent document 1, since the voltage between the terminals of each of the primary coil and the secondary coil of the pulse transformer oscillates due to the inductance component of the primary side of the pulse transformer and the series resonance of the primary side capacitor (such oscillation is referred to as "oscillation"), depending on the timing at which the switch included in the switch section is switched on or off, when the switch is switched, the voltage value of the voltage may decrease by a certain value depending on the oscillation. In this case, the amount of power transmitted from the primary side to the secondary side decreases, and the transmission efficiency of power from the primary side to the secondary side of the pulse transformer decreases (which will be described later in detail with reference to fig. 12).

Now, an example of the following case will be explained: in the pulse signal output circuit disclosed in patent document 1, the transmission efficiency of electric power from the primary side to the secondary side of the pulse transformer is reduced. Fig. 12 is a timing chart showing an example of a case where the power transmission efficiency of the pulse signal output circuit of the related art is reduced. Fig. 12 shows an example: the pulse signal output circuit disclosed in patent document 1 controls the ON/OFF states of the positive-direction switch and the negative-direction switch to convert the pulse signal to be output to a low level, and the voltage and the current amount of the primary side of the pulse transformer (the primary-side voltage and the primary-side current) are changed according to the states of the switches. Further, it can be said that the waveform of the primary side voltage shown in fig. 12 is the same as the waveform of the secondary side voltage (secondary side voltage) of the pulse transformer, although the voltage values of the primary side voltage and the secondary side voltage are different.

In the timing chart shown in fig. 12, each of the positive-going switch and the negative-going switch is switched on or off at time t0, time t1, and time t 2. As shown in fig. 12, if each of the positive-direction switch and the negative-direction switch is switched on or off, the primary-side voltage of the pulse transformer oscillates due to the inductance component of the primary side of the pulse transformer and the series resonance of the primary-side capacitor. The primary side current of the pulse transformer oscillates in accordance with the oscillation of the primary side voltage. Also, the oscillation frequency of the primary side voltage is determined according to the inductance value of the inductance component of the primary side of the pulse transformer and the capacitance value of the primary side capacitor, and the damping degree of the oscillation is determined according to the resistance value of each of the positive-going switch and the negative-going switch in the ON state and the resistance value of the primary coil of the pulse transformer.

In the timing chart shown in fig. 12, the waveform of the primary-side voltage around time t1 is worth noting when the positive-going switch and the negative-going switch are switched. At time t1, the positive-going switch and the negative-going switch are switched, whereby a negative-going current is applied to the primary side of the pulse transformer. Therefore, the primary side voltage becomes a negative voltage. In addition, at time t0, the positive switch and the negative switch are switched, whereby a positive current is applied to the primary side of the pulse transformer, and the primary side voltage becomes a positive voltage. Then, the primary side voltage oscillates due to the series resonance of the primary side capacitor and the inductance component of the primary side of the pulse transformer. However, the oscillation of the primary-side voltage does not converge until a time just before the time t1 at which the switch is switched, and at the time t1, the primary-side voltage has the voltage value Va. For this reason, at time t1, the primary side voltage becomes a voltage value of-V + Va, i.e., a negative voltage higher by Va than-V. In fig. 12, there is shown: since the direction of the primary-side voltage is switched to the negative direction at time t1, the primary-side voltage drops to a voltage higher than the voltage-V by the voltage value Va, not to the voltage-V. In this case, the secondary-side voltage induced on the secondary side of the pulse transformer also changes similarly. Therefore, in the pulse signal output circuit of the related art, the amount of power transmitted from the primary side to the secondary side of the pulse transformer decreases, and the power transmission efficiency from the primary side to the secondary side decreases.

Further, in fig. 12, there are shown: at time t2 when the positive switch and the negative switch are switched, since the oscillation of the primary side voltage has converged, the primary side voltage becomes a voltage + V, not a voltage lower than the voltage + V. However, even at time t2 shown in fig. 12, if the oscillation of the primary side voltage does not converge, similarly, the primary side voltage becomes a voltage lower than the voltage + V, the secondary side voltage induced on the secondary side by the pulse transformer varies, and the power transmission efficiency from the primary side to the secondary side decreases.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a pulse signal output circuit having a structure using a pulse transformer that insulates a primary side and a secondary side from each other, and capable of improving power transmission efficiency from the primary side to the secondary side of the pulse transformer.

disclosure of Invention

in order to solve the above-described problems, a pulse signal output circuit according to the present invention is a pulse signal output circuit for outputting a pulse signal based on a current supplied from a DC power supply connected to the pulse signal output circuit. The pulse signal output circuit includes: a pulse transformer including a primary coil and a secondary coil; a switching unit for switching a direction of action of the current as a primary side current on the primary coil of the pulse transformer; a primary side capacitor arranged on a path of the primary side current; a rectifying section for rectifying a secondary-side voltage induced on the secondary coil based on a primary-side voltage applied to the primary coil in accordance with the primary-side current, and outputting the rectified voltage; a secondary side capacitor that is charged by the rectified voltage and discharges a charge; a transistor that is turned on and off according to a voltage of the secondary side capacitor; and a switching timing controller that controls a timing at which the switching section switches the acting direction of the primary side current. And the switching timing controller is configured to control to switch the acting direction of the primary side current when the primary side voltage oscillates due to series resonance of the primary coil and the primary side capacitor, and a polarity of the primary side voltage is opposite to a polarity of the primary side voltage at a start timing of one switching cycle of the switching section.

According to the present invention, after the switching section switches the direction of the primary current, the primary voltage applied to the primary coil of the pulse transformer becomes high. Therefore, the pulse signal output circuit can efficiently transmit the primary-side voltage applied to the primary coil of the pulse transformer to the secondary coil, thereby inducing the secondary-side voltage on the secondary coil.

The switching timing controller may be configured to control to switch the acting direction of the primary side current at a timing at which oscillation of the primary side voltage has a peak of the opposite polarity.

According to the present invention, in the case where the primary side voltage oscillates due to the series resonance of the primary coil and the polarity of the primary side voltage is opposite, the pulse signal output circuit switches when the primary side voltage has a high voltage value peak value of opposite polarity, so that the primary side current becomes a voltage value having a higher absolute value. Therefore, the power transmission efficiency from the primary coil to the secondary coil of the pulse transformer can be further improved.

The switching timing controller may be configured to control to switch the acting direction of the primary side current at a timing at which the oscillation of the primary side voltage has a first peak value of the opposite polarity after the start timing.

According to the present invention, in the case where the primary side voltage oscillates due to the series resonance of the primary coil and the polarity of the primary side voltage is opposite, the pulse signal output circuit switches when the primary side voltage has the highest voltage value peak value of the opposite polarity, so that the primary side current becomes a voltage value having a higher absolute value. Therefore, the power transmission efficiency from the primary coil to the secondary coil of the pulse transformer can be further improved.

A switching time indicating a timing of switching the acting direction of the primary side current may be set in advance, and the switching timing controller may be configured to measure an elapsed time from the start timing and to control to switch the acting direction of the primary side current at a timing at which the measured elapsed time reaches the switching time set in advance.

The switching time may be a time calculated in advance based on an inductance value of the primary coil and a capacitance value of the primary side capacitor.

According to the present invention, the pulse signal output circuit sets in advance a switching time calculated from characteristic values of the pulse transformer and the primary side capacitor, and controls the switching section at the switching time by the switching timing controller having a simple structure so that the switching section switches the acting direction of the primary side current. Therefore, according to the pulse signal output circuit, the power transmission efficiency from the primary coil to the secondary coil of the pulse transformer can be improved by a simple configuration suitable for the characteristic values of the pulse transformer and the primary side capacitor.

The switching timing controller may further include a timing detection circuit configured to acquire a voltage value of the primary side voltage and detect a timing of switching the acting direction of the primary side current based on the acquired voltage value, and the switching timing controller may be configured to control to switch the acting direction of the primary side current when the timing detection circuit detects a timing of switching the acting direction of the primary side current.

According to the present invention, in the pulse signal output circuit, the switching timing controller measures the primary side voltage. Therefore, if the primary side voltage oscillates and the polarity of the primary side voltage is opposite, it is possible to ensure the timing at which the highest voltage value peak having the opposite polarity is detected, and to control the switching section so that the switching section switches the acting direction of the primary side current. Therefore, according to the pulse signal output circuit, the power transmission efficiency from the primary coil to the secondary coil of the pulse transformer can be more certainly improved.

The pulse signal output circuit may further include a primary side resistance configured to suppress oscillation of the primary side voltage, the oscillation being caused by the series resonance.

According to the present invention, after the switching section switches the acting direction of the primary side current, the pulse signal output circuit can rapidly converge the oscillation of the primary side voltage through the primary side resistance. Therefore, according to the pulse signal output circuit, the power transmission efficiency from the primary coil to the secondary coil of the pulse transformer can be improved, and the additional power consumption caused by the large oscillation of the primary side circuit can be suppressed.

The switching section may include an output voltage selection circuit configured to: and outputting a DC voltage or a reference voltage provided by a DC voltage source according to the control for switching the acting direction of the primary side current by the switching timing controller.

According to the present invention, the pulse signal output circuit can switch the acting direction of the primary side current by the switching section having fewer elements. Therefore, according to the pulse signal output circuit, the power transmission efficiency from the primary coil to the secondary coil of the pulse transformer can be improved, and the pulse signal output circuit can be realized in a smaller size at a lower cost. Further, it is possible to reduce leakage of the DC power supply connected to the pulse signal output circuit and to reduce a load of the DC power supply.

The rectifying section may be a bridge rectifier circuit having a bridge circuit including four diodes.

According to this configuration, the pulse signal output circuit can rectify the secondary side voltage transmitted with high transmission efficiency and apply the rectified voltage as the drive voltage to drive the gate terminal of the transistor.

The rectifying section may be a voltage-multiplying rectifying circuit including one capacitor and two diodes.

According to the present invention, the pulse signal output circuit can rectify a secondary side voltage transmitted with high transmission efficiency by the rectifying section having fewer elements and apply the rectified voltage as a driving voltage to drive the gate terminal of the transistor, and can realize the pulse signal output circuit in a smaller size at a lower cost.

According to the present invention, the following effects can be achieved: it is possible to provide a pulse signal output circuit having a structure using a pulse transformer that insulates a primary side and a secondary side from each other, and capable of improving power transmission efficiency from the primary side to the secondary side of the pulse transformer.

Drawings

Exemplary embodiments of the present invention will be described in detail based on the accompanying drawings, in which:

Fig. 1 is a structural diagram showing the structure of a pulse signal output circuit according to a first embodiment of the present invention;

Fig. 2 is a waveform diagram for explaining the overall operation of the pulse signal output circuit of the first embodiment of the present invention;

Fig. 3 is a waveform diagram for explaining an example of timings at which switches included in the switch section in the pulse signal output circuit according to the first embodiment of the present invention are switched;

Fig. 4 is a waveform diagram for explaining another example of timings at which switches included in the switch section in the pulse signal output circuit according to the first embodiment of the present invention are switched;

Fig. 5 is a structural diagram showing the structure of a pulse signal output circuit according to a second embodiment of the present invention;

Fig. 6 is a waveform diagram for explaining an example of timings at which switches included in the switch section in the pulse signal output circuit according to the second embodiment of the present invention are switched;

fig. 7 is a structural diagram showing the structure of a pulse signal output circuit according to a first modification of the present invention;

Fig. 8 is a structural diagram showing the structure of a pulse signal output circuit according to a second modification of the present invention;

Fig. 9 is a structural diagram showing the structure of a pulse signal output circuit according to a third modification of the present invention;

Fig. 10 is a waveform diagram for explaining an example of timing at which a switch included in a switch unit in a pulse signal output circuit according to a third modification of the present invention is switched;

Fig. 11 is a configuration diagram showing a configuration of a pulse signal output circuit according to a fourth modification of the present invention; and

fig. 12 is a timing chart showing an example of a case where the power transmission efficiency is lowered in the pulse signal output circuit of the related art.

Detailed Description

< first embodiment >

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Fig. 1 is a structural diagram showing the structure of a pulse signal output circuit according to a first embodiment of the present invention. The pulse signal output circuit 10 includes a switching section 11, a primary side capacitor 12, a switching timing controller 13, a pulse transformer 14, a rectifying section 15, a secondary side capacitor 16, a secondary side resistor 17, and a Field Effect Transistor (FET) 18. Fig. 1 also shows a DC power supply PS and a receiver RE connected to the pulse signal output circuit 10.

The DC power supply PS is a power supply for supplying a current required for the pulse signal output circuit 10 to generate a pulse signal. In the following description, a voltage according to a current supplied from the DC power supply PS will be referred to as a voltage Vs. In the following description, the DC power supply PS will be referred to as an output voltage Vs for convenience of description.

The receiver RE receives the pulse signal generated and output by the pulse signal output circuit 10 and performs processing based on the received pulse signal. Also, fig. 1 shows a configuration in which the receiver RE receives the pulse signal output from the pulse signal output circuit 10 via the transmission line TL.

When a current is supplied from the DC power supply PS connected to the pulse signal output circuit 10, the pulse signal output circuit 10 generates a pulse signal by switching the direction of application of the current by the switch section 11, and outputs the generated pulse signal to the receiver RE. The pulse signal output circuit 10 can be used, for example, for a field device that is installed at a machining position for transmitting a machining amount such as a flow rate measured by a pulse signal at the installation position. Also, in the case where the pulse signal output circuit 10 is used for a field device, a power supply that supplies a current, which is, for example, in the range of 4mA to 20mA and is generated from a DC analog signal, so that the field device can transmit a measured process value using the current, may be used as the DC power supply PS. Also, in the case where the pulse signal output circuit 10 is used for a field device, for example, the receiver RE may include a pulse counter for counting the number of received pulse signals and outputting information as information on the measured process amount based on a count value representing the number of received pulse signals.

the pulse transformer 14 has one coil on the primary side and one coil on the secondary side. The pulse transformer 14 is excited by a current acting on a coil on the primary side (hereinafter referred to as a primary coil), thereby inducing a voltage based on a voltage between both ends of the primary coil between both ends of a coil on the secondary side (hereinafter referred to as a secondary coil).

In fig. 1, black dots shown near the coils included in the pulse transformer 14 indicate the first turn positions of the wires of the coils, respectively. In fig. 1, the first turn positions (positions of black dots) of the wires of the coil included in the pulse transformer 14 are on the same side. Therefore, in the pulse transformer 14, the winding direction of the wire of the coil is the same. In the following description, the first turn of the wire of the primary coil of the pulse transformer 14 is referred to as a first terminal a1, and the last turn of the wire is referred to as a second terminal B1. Also, the first turn of the wire of the secondary coil of the pulse transformer 14 is referred to as a first terminal a2, and the last turn of the wire is referred to as a second terminal B2.

the primary side circuit and the secondary side circuit of the pulse signal output circuit 10 are insulated from each other in the dc mode by the pulse transformer 14. When a current is supplied from the DC power supply PS connected to the pulse signal output circuit 10, the primary side circuit of the pulse signal output circuit applies a current to the primary coil of the pulse transformer 14. Therefore, in the pulse signal output circuit 10, a voltage based on a voltage between the first terminal a1 and the second terminal B1 of the primary coil is induced between the first terminal a2 and the second terminal B2 of the secondary coil of the pulse transformer 14. Then, the secondary side circuit of the pulse signal output circuit 10 rectifies the current flowing in the secondary coil of the pulse transformer 14, generates a pulse signal based on the voltage according to the rectified current, and outputs the generated pulse signal to the receiver RE.

in fig. 1, the current applied to the primary coil of the pulse transformer 14 by the primary side circuit is shown as a primary side current i1, and the voltage between the first terminal a1 and the second terminal B1 of the primary coil of the pulse transformer 14 is shown as a primary side voltage V1. Also, in fig. 1, a voltage between the first terminal a2 and the second terminal B2 of the secondary coil of the pulse transformer 14 is shown as a secondary-side voltage V2, and a current flowing according to the secondary-side voltage V2 is shown as a secondary-side current i 2. Also, in fig. 1, a current flowing in the secondary side circuit after the secondary side current i2 flowing along the secondary coil of the pulse transformer 14 is rectified is shown as a rectified current i3, and a voltage according to the rectified current i3 is shown as a rectified voltage V3.

The primary side circuit of the pulse signal output circuit 10 is composed of a switch section 11, a primary side capacitor 12, a switching timing controller 13, and a primary coil of a pulse transformer 14. In the primary side circuit of the pulse signal output circuit 10, the first terminal a1 of the primary coil of the pulse transformer 14 is connected to the first output terminal of the switch section 11. Also, the second terminal B1 of the primary coil of the pulse transformer 14 is connected to the first terminal of the primary-side capacitor 12. Further, a second terminal of the primary-side capacitor 12 is connected to a second output terminal of the switching section 11.

The primary-side capacitor 12 causes a primary-side current i1 to flow for a short time in the primary-side circuit of the pulse signal output circuit 10. Also, in the case where the pulse signal output circuit 10 is used for a field device, if the field device satisfies the explosion-proof standard, the primary side capacitor 12 functions as an explosion-proof circuit.

when a current is supplied from the DC power supply PS connected to the input terminal of the switching section 11, the switching section switches the acting direction of the current so that the primary side current i1 acts between the first output terminal and the second output terminal in the switched direction. The switch section 11 has a switch S1, a switch S2, a switch S3, and a switch S4. Each of the switch S1, the switch S2, the switch S3, and the switch S4 of the switch section 11 is switched between an ON state in which the first terminal and the second terminal are short-circuited and an OFF state in which the first terminal and the second terminal are open-circuited according to a control signal output from the switching timing controller 13, thereby switching the direction of the primary-side current i1 acting between the first output terminal and the second output terminal. In the following description, when it is not necessary to distinguish the switch S1, the switch S2, the switch S3, and the switch S4 included in the switch unit 11, they are referred to as switches S.

In the switch section 11, a first terminal of the switch S1 and a first terminal of the switch S3 are connected, and this connection point serves as an input terminal of the switch section 11 and is connected to a forward terminal (DC voltage output terminal) of the DC power supply PS. Also, in the switch section 11, the second terminal of the switch S1 is connected to the first terminal of the switch S2, and this connection point serves as the first output terminal of the switch section 11 and is connected to the first terminal a1 of the primary coil of the pulse transformer 14. Also, in the switch section 11, the second terminal of the switch S3 is connected to the first terminal of the switch S4, and this connection point serves as the second output terminal of the switch section 11 and is connected to the second terminal of the primary-side capacitor 12. In the switch section 11, a reference voltage for the primary side circuit is applied to the second terminal of the switch S2 and the second terminal of the switch S4. A reference voltage for the primary side circuit is also applied to one terminal of the DC power supply PS. Also, in the switch section 11, a corresponding one of the control signals output from the switching timing controller 13 is applied to the control terminal of each of the switch S1, the switch S2, the switch S3, and the switch S4. More specifically, in the switch section 11, the control signal CP output from the switching timing controller 13 is applied to the control terminals of the switch S1 and the switch S4, and the control signal CN output from the switching timing controller 13 is applied to the control terminals of the switch S2 and the switch S3. In the following description, the control signal CP and the control signal CN output from the switching timing controller 13 and input to the control terminal of the switch S are referred to as a control signal C without distinction.

The switching timing controller 13 controls each switch S included in the switching section 11. In the switching timing controller 13, a timing indicating a timing of switching each switch S included in the switch section 11 is set in advance. The switching timing controller 13 includes, for example, a timer circuit or a clock circuit which is provided in a processor such as a Central Processing Unit (CPU) and uses a timer function or the like, and when the measured time is a preset time, the switching timing controller 13 outputs each of the control signals C for switching the ON/OFF state of the switches S included in the switch section 11 to the corresponding switch S. More specifically, the switching timing controller 13 outputs a control signal CP for simultaneously switching the switch S1 and the switch S4 between the ON state and the OFF state and a control signal CN for simultaneously switching the switch S2 and the switch S3 to a control terminal of the switch S. The switching timing controller 13 exclusively (complementarily) controls switching of the switch S1 and the switch S4 between the ON state and the OFF state and switching of the switch S2 and the switch S3 between the ON state and the OFF state. In other words, the switching timing controller 13 turns off the switch S2 and the switch S3 when the switch S1 and the switch S4 are turned on, and turns off the switch S1 and the switch S4 when the switch S2 and the switch S3 are turned on. In this way, in the primary side circuit of the pulse signal output circuit 10, the respective switches S included in the switch section 11 are switched between the ON state and the OFF state, thereby switching the direction of action of the current that is supplied from the DC power supply PS connected to the switch section 11 and that is to flow as the primary side current i1 in the primary coil of the pulse transformer 14. Thus, the direction of the primary side current i1 is reversed. The timing of switching the respective switches S included in the switching section 11 between the ON state and the OFF state by the switching timing controller 13 will be described later together with the operation of the pulse signal output circuit 10.

The secondary side circuit of the pulse signal output circuit 10 is constituted by the secondary coil of the pulse transformer 14, the rectifier 15, the secondary side capacitor 16, the secondary side resistor 17, and the FET 18. In the secondary side circuit of the pulse signal output circuit 10, the first terminal a2 of the secondary coil of the pulse transformer 14 is connected to the first input terminal of the rectifying section 15. Further, a second terminal B2 of the secondary coil of the pulse transformer 14 is connected to a second input terminal of the rectifying portion 15. In the secondary side circuit of the pulse signal output circuit 10, the first output terminal of the rectifying unit 15 is connected to the first terminal of the secondary side capacitor 16, the first terminal of the secondary side resistor 17, and the gate terminal of the FET 18. Also, in the secondary side circuit of the pulse signal output circuit 10, the drain terminal of the FET18 serves as the first output terminal O1 of the pulse signal output circuit 10. Also, in the secondary side circuit of the pulse signal output circuit 10, the second output terminal of the rectifying section 15 is connected to the second terminal of the secondary side capacitor 16, the second terminal of the secondary side resistance 17, and the source terminal (and back gate terminal) of the FET18, and this connection point serves as the second output terminal O2 of the pulse signal output circuit 10. Also, in fig. 1, the first output terminal O1 and the second output terminal O2 of the pulse signal output circuit 10 are connected to the corresponding transmission lines TL, respectively, and are connected to the receiver RE via these transmission lines TL.

The rectifying section 15 rectifies a voltage supplied between the first input terminal and the second input terminal, and supplies the rectified voltage between the first output terminal and the second output terminal. In other words, the rectifying section 15 supplies a rectified voltage between the gate terminal and the source terminal of the FET18 and between both ends of each of the secondary-side capacitor 16 and the secondary-side resistor 17. The rectifying section 15 has a diode D1, a diode D2, a diode D3, and a diode D4. The rectifying unit 15 is a bridge rectifier circuit having a bridge circuit composed of a diode D1, a diode D2, a diode D3, and a diode D4, full-wave rectifies a voltage supplied between the first input terminal and the second input terminal, and supplies the rectified voltage between the first output terminal and the second output terminal through the bridge circuit. In the following description, when it is not necessary to distinguish the diode D1, the diode D2, the diode D3, and the diode D4 included in the rectifying unit 15, they are referred to as a diode D.

In the rectifying section 15, the positive terminal of the diode D1 is connected to the negative terminal of the diode D3, and this connection point serves as a first input terminal of the rectifying section 15 and is connected to the first terminal a2 of the secondary coil of the pulse transformer 14. Also, in the rectifying section 15, the positive terminal of the diode D2 is connected to the negative terminal of the diode D4, and this connection point serves as the second input terminal of the rectifying section 15 and is connected to the second terminal B2 of the secondary coil of the pulse transformer 14. Further, in the rectifying section 15, the negative terminal of the diode D1 is connected to the negative terminal of the diode D2, and this connection point serves as a first output terminal of the rectifying section 15 and is connected to the first terminal of the secondary side capacitor 16, the first terminal of the secondary side resistor 17, and the gate terminal of the FET 18. Further, in the rectifying section 15, the positive terminal of the diode D3 is connected to the positive terminal of the diode D4, and the connection point serves as the second output terminal of the rectifying section 15 and is connected to the second terminal of the secondary side capacitor 16, the second terminal of the secondary side resistor 17, and the source terminal of the FET18, and the connection point serves as the second output terminal O2 of the pulse signal output circuit 10.

The secondary side capacitor 16 is charged by the rectified voltage V3 provided between the first terminal and the second terminal, i.e. stores charge according to the rectified voltage V3. In other words, the secondary side capacitor 16 is charged by the rectified current i3 flowing between the first terminal and the second terminal.

The secondary side resistor 17 functions to discharge the charge stored in the secondary side capacitor 16.

In the pulse signal output circuit 10, a voltage is applied between the gate terminal and the source terminal of the FET18 by the structure of the secondary side capacitor 16 and the secondary side resistor 17. In other words, in the pulse signal output circuit 10, even if the supply of the rectified voltage from the rectifying section 15 is stopped, the potential between the gate terminal and the source terminal of the FET18 is held for a certain period of time depending on the capacitance value of the secondary side capacitor 16 and the resistance value of the secondary side resistor 17.

The FET18 switches between an ON state (the drain terminal and the source terminal are connected) and an OFF state (the drain terminal and the source terminal are disconnected) in accordance with a rectified voltage V3 applied between the gate terminal and the source terminal, thereby generating a pulse signal. The pulse signal generated by the FET18 is transmitted to the receiver RE via the transmission line TL. The receiver RE recognizes a pulse signal of a low level when the FET18 is in the ON state, and recognizes a pulse signal of a high level when the FET18 is in the OFF state. More specifically, the FET18 controls the flow of current supplied from the receiver RE in accordance with the rectified voltage V3 applied to the gate, thereby generating a voltage across a resistor (not shown in the figure) provided on the transmission line TL, which is transmitted as a pulse signal to the receiver RE. As the pulse signal, for example, a signal representing the voltage across the resistance, which is high in a state where the FET18 is ON (hereinafter referred to as an ON state) and low in a state where the FET18 is OFF (hereinafter referred to as an OFF state), is transmitted to the receiver RE as the pulse signal. However, in the following description, for convenience of description, the FET18 is referred to as a generation pulse signal and a transmission pulse signal.

According to this configuration, the pulse signal output circuit 10 switches the action direction of the current supplied from the DC power supply PS connected to the primary side circuit and flowing as the primary side current i1 by the switch section 11, thereby generating a pulse signal, and outputs the generated pulse signal to the receiver RE.

In the following description, the direction of action of the primary-side current i1 from the first terminal a1 to the second terminal B1 of the primary coil of the pulse transformer 14 is referred to as a positive direction, and the direction of action of the primary-side current i1 from the second terminal B1 to the first terminal a1 is referred to as a negative direction. The direction of each of the primary side current i1 and the secondary side current i2 shown in fig. 1 represents the forward direction.

now, the operation of the pulse signal output circuit 10 is explained. First, the overall operation of the pulse signal output circuit 10 for generating a pulse signal and outputting the pulse signal will be described. Fig. 2 is a waveform diagram for explaining an example of the overall operation of the pulse signal output circuit 10 of the first embodiment of the present invention. An example of the overall operation of the pulse signal output circuit 10 shown in fig. 2 is an example of a case where the pulse signal output circuit 10 generates a pulse signal of one cycle. Fig. 2 schematically shows the ON/OFF state of each switch S included in the switch section 11, the primary side voltage V1 of the primary coil of the pulse transformer 14, the secondary side current i2 flowing according to the secondary side voltage V2 (voltage induced in the secondary coil of the pulse transformer 14), the rectified current i3 obtained by full-wave rectification by the rectifying section 15, the rectified voltage V3 according to the rectified current i3, and the waveform (signal) and level of the ON/OFF state of the FET 18.

The pulse transformer 14 included in the pulse signal output circuit 10 is excited by a primary-side current i1 flowing in the primary coil, thereby inducing a secondary-side voltage V2 due to the primary-side voltage V1 (acting between the first terminal a1 and the second terminal B1 of the primary coil) between the first terminal a2 and the second terminal B2 of the secondary coil. Therefore, it can be said that the waveform of the primary-side voltage V1 of the primary coil shown in fig. 2 is the same as the waveform of the secondary-side voltage V2 induced in the secondary coil of the pulse transformer 14, but their voltage values are different. Therefore, in the following description, the waveform of the primary side voltage V1 of the primary coil of the pulse transformer 14 and the waveform of the secondary side voltage V2 of the secondary coil will be appropriately substituted for each other.

In the period between time t0 and time t1, the switching timing controller 13 controls the switches S included in the switch section 11 by the control signal C so that each switch is alternately switched between the ON state and the OFF state, thereby causing the pulse signal output circuit 10 to output a pulse signal of a low level. Fig. 2 shows a manner in which the switching timing controller 13 alternately switches the control signal CP and the control signal CN from time t0 at which one pulse signal period starts, thereby switching the respective switches S between the ON state and the OFF state. Hereinafter, an operation of generating a pulse signal of one cycle by switching of the control signal C by the switching timing controller 13 will be described.

at time t0, the switching timing controller 13 switches the switch S1 and the switch S4 from the OFF state to the ON state by the control signal CP, and switches the switch S2 and the switch S3 from the ON state to the OFF state by the control signal CN. Therefore, the voltage Vs output from the DC power supply PS is applied to the primary side circuit of the pulse signal output circuit 10, and the primary side current i1 flows in the forward direction. In other words, in the primary side circuit of the pulse signal output circuit 10, the primary side current i1 flows along the switch S1 included in the switch section 11, the primary coil (from the first terminal a1 to the second terminal B1) of the pulse transformer 14, the primary side capacitor 12, and the switch S4 included in the switch section 11. Therefore, as the primary side voltage V1, a voltage having a voltage value of +2Vs is applied to the primary coil of the pulse transformer 14. Thereafter, the switching timing controller 13 switches the switch S1 and the switch S4 from the ON state to the OFF state by the control signal CP, and switches the switch S2 and the switch S3 from the OFF state to the ON state by the control signal CN. Therefore, the voltage output from the DC power supply PS acts on the primary side circuit of the pulse signal output circuit 10, and the primary side current i1 flows in the negative direction. In other words, in the primary side circuit of the pulse signal output circuit 10, the primary side current i1 flows along the switch S3 included in the switch section 11, the primary side capacitor 12, the primary coil (from the second terminal B1 to the first terminal a1) of the pulse transformer 14, and the switch S2 included in the switch section 11. Therefore, as the primary side voltage V1, a voltage having a voltage value of-2 Vs is applied to the primary coil of the pulse transformer 14.

In this case, in the pulse signal output circuit 10, the secondary-side voltage V2 due to the primary-side voltage V1 is induced in the secondary coil of the pulse transformer 14, and the secondary-side current i2 according to the secondary-side voltage V2 flows in the secondary coil. In the pulse signal output circuit 10, the rectifier 15 full-wave rectifies the secondary side current i2 based on the secondary side voltage V2 induced in the secondary coil of the pulse transformer 14. Therefore, in the pulse signal output circuit 10, as shown in fig. 2, the rectified current i3 obtained by full-wave rectification by the rectifying section 15 flows in one direction, and the rectified voltage V3 according to the rectified current i3 becomes a unidirectional voltage. In the pulse signal output circuit 10, a rectified voltage V3 according to a rectified current i3 obtained by full-wave rectification by the rectifying section 15 acts between the terminals of the secondary side capacitor 16, between the terminals of the secondary side resistor 17, and between the gate terminal and the source terminal of the FET. Therefore, in the pulse signal output circuit 10, the secondary side capacitor 16 is charged by the rectified current i 3. Also, in the pulse signal output circuit 10, the FET18 is turned on by the rectified voltage V3 applied between the gate terminal and the source terminal, whereby the pulse signal to be output transitions to a low level.

Further, in the pulse signal output circuit 10, as shown in fig. 2, the voltage value of the primary side voltage V1 changes between a voltage value +2Vs and a voltage value-2 Vs according to the switching of the switch S. Therefore, in the pulse signal output circuit 10, the secondary side voltage V2 induced in the secondary coil of the pulse transformer 14 according to the primary side voltage V1 also varies similarly to the primary side voltage V1. Therefore, in the pulse signal output circuit 10, the secondary side current i2 flowing through the secondary coil of the pulse transformer 14 temporarily changes to a high current at each time when the voltage value of the secondary side voltage V2 changes from a positive voltage value to a negative voltage value. As can be seen from fig. 2, the timing at which the secondary-side current i2 temporarily increases to a high current in the pulse signal output circuit 10 is a timing just after the ON/OFF state of each switch S is switched. However, if the voltage value of the secondary-side voltage V2 is stable, the secondary-side current i2 decreases and disappears soon. Fig. 2 shows the manner in which the secondary side current i2 varies.

In the pulse signal output circuit 10, as shown in fig. 2, if the secondary side current i2 becomes 0A, the current value of the rectified current i3 obtained by full-wave rectification by the rectifying section 15 also becomes 0A. Therefore, in the pulse signal output circuit 10, the rectified voltage V3 according to the rectified current i3 decreases. In the pulse signal output circuit 10, the secondary side capacitor 16 is charged by the rectified current i 3. Therefore, in the pulse signal output circuit 10, if the value of the rectified current i3 obtained by full-wave rectification by the rectifying unit 15 becomes zero (the current value becomes 0A), the secondary side capacitor 16 discharges the stored charge due to the configuration of the secondary side capacitor 16 and the secondary side resistor 17. Therefore, in the pulse signal output circuit 10, even if the rectified current i3 obtained by full-wave rectification by the rectifying section 15 becomes 0A, as shown in fig. 2, the rectified voltage V3 between the gate terminal and the source terminal of the FET18 is maintained at a voltage value capable of bringing the FET into an ON state, and the pulse signal to be output is maintained at a low level.

meanwhile, in the period between the time t1 and the time t2, the switching timing controller 13 controls the switch S included in the switch section 11 by the control signal C so that the switch is kept in its ON/OFF state, thereby causing the pulse signal output circuit 10 to output a pulse signal of high level. Fig. 2 shows such a manner that the control signal CP and the control signal CN of the timing controller 13 are switched from time t1 in one pulse signal period, thereby causing the ON/OFF state of the switch S to be maintained.

More specifically, at time t1, the switching timing controller 13 turns off the switch S1 and the switch S4 by the control signal CP, and turns on the switch S2 and the switch S3 by the control signal CN. Therefore, the voltage Vs output from the DC power supply PS acts on the primary side circuit of the pulse signal output circuit 10, and the primary side current i1 keeps flowing in the negative direction. In other words, in the primary side circuit of the pulse signal output circuit 10, the primary side current i1 keeps flowing along the switch S3 included in the switch section 11, the primary side capacitor 12, the primary coil (from the second terminal B1 to the first terminal a1) of the pulse transformer 14, and the switch S2 included in the switch section 11. Therefore, the primary side voltage V1 having a voltage value of-2 Vs remains applied to the primary coil of the pulse transformer 14. In other words, the state of the primary side voltage V1 applied to the primary coil of the pulse transformer 14 is fixed at a voltage value of-2 Vs without change.

Therefore, in the pulse signal output circuit 10, the secondary side voltage V2 due to the primary side voltage V1 is induced in the secondary coil of the pulse transformer 14. At this time, as shown in fig. 2, the primary side voltage V1 is kept constant at a voltage value of-2 Vs. Therefore, in the pulse signal output circuit 10, the voltage value of the secondary side voltage V2 induced in the secondary coil of the pulse transformer 14 in accordance with the primary side voltage V1 is also kept constant similarly to the primary side voltage V1. In the pulse signal output circuit 10, at a time t1 when the voltage value of the secondary side voltage V2 changes from the positive voltage value to the negative voltage value, the secondary side current i2 flowing in the secondary coil of the pulse transformer 14 temporarily becomes a high current, and thereafter, if the voltage value of the secondary side voltage V2 is stabilized, the secondary side current decreases and disappears soon.

Also, in the pulse signal output circuit 10, if all the electric charges stored in the secondary side capacitor 16 by the rectified current i3 are discharged in the period between the time t0 and the time t1 so that the pulse signal output circuit 10 outputs the pulse signal of the low level, the current value of the rectified current i3 obtained by full-wave rectifying the secondary side current i2 in the rectifying section 15 and the voltage value of the rectified voltage V3 according to the rectified current i3 are held at 0A and 0V, respectively. Therefore, in the pulse signal output circuit 10, the FET18 is turned on by the rectified voltage V3 having a voltage value of 0V acting between the gate terminal and the source terminal, and the pulse signal to be output transitions to a high level.

In this way, in the pulse signal output circuit 10, the switching timing controller 13 controls (switches) the ON/OFF states of the respective switches S included in the switch section 11 connected to the DC power supply PS, thereby turning ON and OFF the FET18, so that the FET generates a pulse signal and outputs the pulse signal. Fig. 2 shows that the pulse signal output circuit 10 starts outputting the pulse signal of the low level again at time t 2.

also, in the pulse signal output circuit 10, the primary side circuit includes a primary side capacitor 12. Therefore, in the pulse signal output circuit 10, the primary-side voltage V1 applied to the primary coil of the pulse transformer 14 in accordance with the primary-side current i1 flowing in accordance with the control of the respective switches S included in the switching section 11 by the switching timing controller 13 oscillates due to the series resonance of the primary coil of the pulse transformer 14 and the primary-side capacitor 12 (such oscillation is referred to as oscillation). Therefore, in the pulse signal output circuit 10, if the timing of switching the switch S included in the switch section 11, that is, the timing of reversing the direction of action of the primary side current i1 on the primary coil of the pulse transformer 14 is not considered, the primary side voltage V1 becomes a voltage value whose absolute value is smaller than an absolute value of a certain value based on the voltage value of the supplied current (see the waveform of the primary side voltage in the primary side circuit of the related art shown in fig. 12), depending on the oscillation due to the series resonance of the primary coil of the pulse transformer 14 and the primary side capacitor 12. Therefore, the switching timing controller 13 controls the timing of the ON/OFF state of each switch S included in the switching section 11 in view of the oscillation frequency of the primary side voltage V1 due to the series resonance of the primary coil of the pulse transformer 14 and the primary side capacitor 12.

Meanwhile, in the present invention, the ON/OFF state of the control switch is switched at a timing different from that in the related art shown in fig. 12, and such a switching timing will be described. The switching timing controller 13 switches the ON/OFF states of the respective switches S included in the switching section 11 based ON the state of the oscillated primary side voltage V1. More specifically, in each switching period, the primary side voltage V1 acting on the primary coil of the pulse transformer 14 starts at a certain voltage value (voltage value at time t 0) and oscillates. And when the primary side voltage has a voltage value of a polarity opposite to the polarity of the voltage value at the start timing of the switching period (hereinafter referred to as opposite polarity), the switching timing controller 13 switches the ON/OFF state of each switch S included in the switching section 11. Such switching may be performed, for example, at each timing when a time preset by the switching timing controller 13 comes.

Fig. 3 is a waveform diagram for explaining an example of the timing of switching the switch S included in the switch section 11 in the pulse signal output circuit 10 of the first embodiment of the present invention. An example of the timing of switching the switch S included in the switch section 11 shown in fig. 3 is an example corresponding to one cycle, in which the switching timing controller 13 switches the ON/OFF state of the switch S so that the pulse signal output circuit 10 outputs a pulse signal of a low level. In other words, the example of the timing of switching the switch S included in the switch section 11 shown in fig. 3 is an example corresponding to one cycle included in the following period: in the example shown in fig. 2 for explaining the overall operation of the pulse signal output circuit 10, the period between the time t0 and the time t1 when the switching timing controller 13 alternately switches the control signal C. Fig. 3 also shows a part of the operation of the secondary side circuit of the pulse signal output circuit 10. Fig. 3 schematically shows the ON/OFF state of each switch S included in the switch section 11, the primary side voltage V1 of the primary coil of the pulse transformer 14, the primary side current i1 acting ON the primary coil of the pulse transformer 14, the rectified current i3 obtained by full-wave rectifying the secondary side current i2 according to the secondary side voltage V2 induced in the secondary coil of the pulse transformer 14 in the rectifying section 15, the rectified voltage V3 according to the rectified current i3, and the waveform (signal) and level of the ON/OFF state of the FET 18.

It can also be said that, similar to the example of the overall operation of the pulse signal output circuit 10 shown in fig. 2, the waveform of the primary-side voltage V1 of the primary coil shown in fig. 3 is the same as the waveform of the secondary-side voltage V2 induced at the secondary coil of the pulse transformer 14. Therefore, in the following description, similarly to the description of the example of the overall operation of the pulse signal output circuit 10 shown in fig. 2, the waveform of the primary side voltage V1 of the primary coil of the pulse transformer 14 and the waveform of the secondary side voltage V2 of the secondary coil will be appropriately replaced with each other.

At time t10, the switching timing controller 13 switches the switch S1 and the switch S4 from the OFF state to the ON state by the control signal CP, and switches the switch S2 and the switch S3 from the ON state to the OFF state by the control signal CN. Then, as described above, the voltage Vs output from the DC power supply PS acts on the primary side circuit of the pulse signal output circuit 10, and the primary side current i1 flows in the forward direction along the switch S1 included in the switch section 11, the primary coil (from the first terminal a1 to the second terminal B1) of the pulse transformer 14, the primary side capacitor 12, and the switch S4 included in the switch section 11. Therefore, as the primary side voltage V1, a voltage having a voltage value of +2Vs is applied to the primary coil of the pulse transformer 14. However, the waveform of the primary side voltage V1 oscillates due to the series resonant circuit constituted by the inductance component of the primary coil of the pulse transformer 14 and the primary side capacitor 12.

At this time, as described above, the secondary side voltage V2 based on the primary side voltage V1 of the primary coil of the pulse transformer 14 is induced in the secondary coil of the pulse transformer 14. The waveform of the secondary side voltage V2 induced in the secondary coil of the pulse transformer 14 also oscillates. Further, as described above, in the secondary side circuit of the pulse signal output circuit 10, the rectified current i3 obtained by full-wave rectifying the secondary side current i2 (according to the secondary side voltage V2 induced in the secondary coil of the pulse transformer 14) in the rectifying section 15 flows, and the rectified voltage V3 according to the rectified current i3 acts between the terminals of the secondary side capacitor 16, between the terminals of the secondary side resistor 17, and between the gate terminal and the source terminal of the FET. Therefore, in the pulse signal output circuit 10, the secondary side capacitor 16 is charged by the rectified current i3, and the FET18 is turned on by the rectified voltage V3 acting between the gate terminal and the source terminal, and the pulse signal of the low level is transmitted to the receiver RE.

Thereafter, in the pulse signal output circuit 10, the voltage value of the primary side voltage V1 decreases due to oscillation due to series resonance, and at time t11, the secondary side voltage V2 is a voltage value below the forward voltage of some of the diodes D (more specifically, the diode D1 and the diode D4) included in the rectifying section 15, whereby the diodes D are turned off. Then, in the pulse signal output circuit 10, the current value of the rectified current i3 obtained by full-wave rectification by the rectifying section 15 becomes 0A, that is, the value of the rectified current i3 acting between the terminals of the secondary side capacitor 16 and between the terminals of the secondary side resistor 17 becomes zero. Therefore, in the pulse signal output circuit 10, the rectified voltage V3 based on the rectified current i3, that is, the voltage between the gate terminal and the source terminal of the FET18 also stops increasing. In the pulse signal output circuit 10, if the rectified current i3 obtained by full-wave rectification by the rectifying section 15 becomes 0A, the charge stored in the secondary side capacitor 16 is discharged by the structure of the secondary side capacitor 16 and the secondary side resistor 17, so that the FET18 is held in the ON state. Therefore, in the pulse signal output circuit 10, the pulse signal to be output is kept at the low level.

In the pulse signal output circuit 10, the voltage value of the primary-side voltage V1 continues to decrease after time t 11. Meanwhile, in the pulse signal output circuit 10, from the time t10, the timing controller 13 is switched to start measuring the time to determine whether or not the preset time has elapsed. Thereafter, at time t12 when the measurement time is equal to the preset time, the switching timing controller 13 switches the switch S1 and the switch S4 from the ON state to the OFF state by the control signal CP, and switches the switch S2 and the switch S3 from the OFF state to the ON state by the control signal CN. As shown in fig. 3, at time t12, the primary side voltage V1 becomes a negative voltage value that is lower than the negative voltage value-2 Vs according to the supplied current by a negative voltage value-Va. Therefore, when the switching timing controller 13 switches the respective switches S, the primary side voltage V1 becomes a negative voltage value- (2Vs + Va) that is lower than the negative voltage value according to the supplied current by a negative voltage value-Va. In fig. 3, the timing at which the oscillating waveform of the primary side voltage V1 first has a peak of opposite polarity is a timing t 12.

As described above, in the pulse signal output circuit 10, at the time t12, the switching timing controller 13 switches each of the switches S, however, when the switches S are switched, the voltage value of the primary side voltage V1 does not change to the opposite polarity. Therefore, the primary-side voltage can be changed to a voltage value having a larger absolute value when switching the respective switches S, as compared with, for example, the case where the switches are switched when the polarity of the primary-side voltage V1 is positive (the case of the related art shown in fig. 12) or when the voltage value of the primary-side voltage is 0V. Therefore, in the pulse signal output circuit 10, the primary side current i1 acting on the primary coil of the pulse transformer 14 and the primary side capacitor 12 increases, and the secondary side voltage V2 induced in the secondary coil of the pulse transformer 14 also increases. Therefore, in the pulse signal output circuit 10, the power transmission efficiency from the primary coil to the secondary coil of the pulse transformer 14 can be improved. Therefore, in the pulse signal output circuit 10, the secondary side current i2 flowing in accordance with the secondary side voltage V2 induced in the secondary coil of the pulse transformer 14 and the rectified current i3 obtained by full-wave rectification by the rectifying section 15 also increase, and the rectified voltage V3 acting between the terminals of the secondary side capacitor 16, between the terminals of the secondary side resistor 17, and between the gate terminal and the source terminal of the FET18 also increases in accordance with the rectified current i 3. Therefore, in the pulse signal output circuit 10, the secondary side capacitor 16 is charged by a larger amount of the rectified current i3, and a high drive voltage for the gate terminal of the FET18 can be obtained.

After that, in the pulse signal output circuit 10, the voltage value of the primary side voltage V1 increases due to oscillation due to series resonance, and at time t13, the secondary side voltage V2 becomes a voltage value below the forward voltage of some of the diodes D (more specifically, the diode D2 and the diode D3) included in the rectifying section 15, whereby the diodes D turn off. Then, in the pulse signal output circuit 10, similarly to the case at time t11, the current value of the rectified current i3 obtained by full-wave rectification by the rectifying section 15 becomes 0A, that is, the value of the rectified current i3 acting between the terminals of the secondary side capacitor 16 and between the terminals of the secondary side resistor 17 becomes zero. Therefore, in the pulse signal output circuit 10, similarly to the case at the time t11, the rectified voltage V3 (the voltage between the gate terminal and the source terminal of the FET 18) according to the rectified current i3 also stops increasing. However, in the pulse signal output circuit 10, even if the rectified current i3 obtained by full-wave rectification of the rectifying section 15 becomes 0A at time t13, similarly to the case at time t11, since the charge stored in the secondary side capacitor 16 is discharged through the structure of the secondary side capacitor 16 and the secondary side resistor 17, the ON state of the FET18 is maintained. Therefore, in the pulse signal output circuit 10, similarly to the case at the time t11, the pulse signal to be output is kept at the low level.

As described above, in the pulse signal output circuit 10, when the primary side voltage has a voltage value of opposite polarity after the oscillating waveform of the primary side voltage V1 becomes opposite polarity, the switching timing controller 13 switches the ON/OFF state of each switch S included in the switching section 11. The timing at which the switching timing controller 13 switches the ON/OFF state of the switch S may be any timing at which the oscillating waveform of the primary side voltage V1 has a voltage value of opposite polarity. In other words, the switching timing may be a timing at which the oscillation waveform of the primary side voltage has a peak, or may be a timing after the second oscillation period of the primary side voltage V1. However, in the pulse signal output circuit 10, in order to improve the power transmission efficiency from the primary coil to the secondary coil of the pulse transformer 14, that is, in order to induce a voltage having a larger absolute value of the voltage value at the secondary coil of the pulse transformer 14 as the secondary side voltage V2, the timing at which the oscillating waveform of the primary side voltage V1 has a peak value of opposite polarity is set as the timing at which the ON/OFF state of the switch S is switched by the timing controller 13. Alternatively, in the pulse signal output circuit 10, the timing at which the oscillating waveform of the primary side voltage V1 has the first peak value of the opposite polarity is set as the timing at which the timing controller 13 switches the ON/OFF state of the switch S. The reason is that, at the timing when the oscillating waveform of the primary side voltage V1 has the first peak of the opposite polarity, the primary side voltage V1 is a voltage value whose voltage value of the opposite polarity has the largest absolute value.

in the pulse signal output circuit 10, after switching the ON/OFF state of each switch S, the switching timing controller 13 measures a preset time, that is, a time required for the next time to switch the ON/OFF state of each switch S. In the example shown in fig. 3 for explaining the timing of switching the switches S included in the switch section 11, the timing (time t12) at which the oscillating waveform of the primary-side voltage has the first peak of opposite polarity is set in advance as the next timing to switch the ON/OFF state of each switch S. Therefore, from the time t10 at which the ON/OFF states of the respective switches S are switched, the switching timing controller 13 measures a preset time required until the time (time t12) at which the oscillating waveform of the primary side voltage V1 has the first peak value of the opposite polarity comes. The time measured by the switching timing controller 13 (here, the time required for the oscillating waveform of the primary side voltage V1 to have the first peak of the opposite polarity) can be obtained based on the case where the primary side voltage V1 oscillates, and can be set in advance.

More specifically, in the pulse signal output circuit 10, the frequency (oscillation frequency) at which the primary side voltage V1 oscillates is determined according to the inductance value of the primary coil of the pulse transformer 14 and the capacitance value of the primary side capacitor 12, and the degree of damping of the oscillation of the primary side voltage V1 is determined according to the resistance value of each of the switches S included in the switch section 11 that is in the ON state and the resistance value of the primary coil. Therefore, in the pulse signal output circuit 10, the time required for the oscillating waveform of the primary side voltage V1 to have the first peak value of the opposite polarity (the time required for the oscillating waveform of the primary side voltage V1 to have the first peak value of the opposite polarity, that is, the time until the time t12) can be calculated in advance based ON the inductance value of the primary coil of the pulse transformer 14 and the capacitance value of the primary side capacitor 12, and the calculated time can be set in advance as the time at which the switching timing controller 13 switches the ON/OFF state of each switch S included in the switching section 11.

More specifically, the oscillation frequency f ₀ of the primary side voltage V1 can be obtained by the following expression 1, and the time required for the oscillation waveform of the primary side voltage V1 to have the first peak value of the opposite polarity (the time from the time T10 to the time T12) corresponds to the time 1/4 of the oscillation period of the primary side voltage V1 that can be obtained from the oscillation frequency f ₀ of the primary side voltage V1, therefore, in the pulse signal output circuit 10, the time required for the oscillation waveform of the primary side voltage V1 to have the first peak value of the opposite polarity is calculated by the following expression 2 as the switching time T for the switching timing controller 13 to switch the ON/OFF state of each switch S.

[ expression 1]

[ expression 2]

In expressions 1 and 2, L denotes an inductance value of the primary coil of the pulse transformer 14, and C denotes a capacitance value of the primary-side capacitor 12. The switching time T of 1/4 corresponding to the oscillation period is calculated, however, it is also possible to calculate the switching time for which the primary side voltage V1 has a voltage value of opposite polarity (for example, a voltage value of opposite polarity that is not a peak value, or a voltage value of opposite polarity after the second oscillation period of the primary side voltage V1).

in the pulse signal output circuit 10, after switching the ON/OFF state of each switch S (for example, at time T10), the switching timing controller 13 measures the time required for the switching time T calculated by expression 2 to come. When the measurement time reaches the switching time T (for example, time T12), the switching timing controller 13 switches the ON/OFF state of each switch S. Therefore, in the pulse signal output circuit 10, as described above, the power transmission efficiency from the primary coil to the secondary coil of the pulse transformer 14 can be improved. Therefore, in the pulse signal output circuit 10, a high driving voltage can be obtained to the gate terminal of the FET18 for generating the pulse signal.

In fig. 2, at the start timing of each pulse signal period (timing t0 and timing t2), the switching timing controller 13 switches the switch S1 and the switch S4 from the OFF state to the ON state, and switches the switch S2 and the switch S3 from the ON state to the OFF state, so that the pulse signal output circuit 10 outputs a pulse signal. In this case, in the pulse signal output circuit 10, the primary side current i1 acts on the primary side circuit of the pulse signal output circuit 10 in the order of positive and negative directions, so that a pulse signal of a low level is output. However, the order in which the switching timing controller 13 first switches which of the respective switches S causes the pulse signal output circuit 10 to output the pulse signal (i.e., the order in which the primary-side current i1 acts on the primary-side circuit of the pulse signal output circuit 10 in the positive and negative directions) is not limited to the order shown in fig. 2. In other words, in the pulse signal output circuit 10, at the start timing of each pulse signal period, the switching timing controller 13 may switch the switch S2 and the switch S3 from the OFF state to the ON state, and switch S1 and the switch S4 from the ON state to the OFF state. In this case, in the pulse signal output circuit 10, the primary side current i1 acts on the primary side circuit of the pulse signal output circuit 10 in the order of negative and positive. Even in this case, the pulse signal output circuit 10 can output a pulse signal of a low level.

Now, the operation of the pulse signal output circuit 10 in the case where the primary-side current i1 acts on the primary-side circuit in the order of negative and positive will be described. Even in the case where the primary-side current i1 acts ON the primary-side circuit of the pulse signal output circuit 10 in the order of negative and positive, the switching timing controller 13 switches the ON/OFF state of each switch S included in the switching section 11 at a preset time after the oscillating waveform of the primary-side voltage V1 becomes opposite polarity, based ON the state of the oscillating primary-side voltage V1. By inverting the ON/OFF states of the respective switches S, the primary-side voltage V1 of the primary coil of the pulse transformer 14 (the secondary-side voltage V2 of the secondary coil of the pulse transformer 14), and the polarity of the waveform of the secondary-side current i2 flowing in the secondary coil of the pulse transformer 14 in the overall operation of the pulse signal output circuit 10 shown in fig. 2, the overall operation of the pulse signal output circuit 10 in this case can be easily given. Therefore, the overall operation of the pulse signal output circuit 10 in the case where the primary side current i1 acts ON the primary side circuit of the pulse signal output circuit 10 in the order of negative and positive is not specifically described, but only the timing (timing within one cycle of the switches) at which the switching timing controller 13 switches the ON/OFF state of each switch S included in the switch section 11 in this case is described with reference to fig. 4.

Fig. 4 is a waveform diagram for explaining another example of the timing of switching the switch S included in the switch section 11 in the pulse signal output circuit 10 according to the first embodiment of the present invention. An example of the timing of switching the switch S included in the switch section 11 shown in fig. 4 is an example of the following case: the switching timing controller 13 switches the ON/OFF state of each switch S, whereby the primary side current i1 acts ON the primary side circuit of the pulse signal output circuit 10 in the order of negative and positive, so that the pulse signal output circuit 10 outputs a pulse signal of low level. Similarly to the example of the timing of the switch S included in the changeover switch section 11 shown in fig. 3, the example of the timing of the switch S included in the changeover switch section 11 shown in fig. 4 is also an example corresponding to one cycle in which the changeover timing controller 13 changes over the ON/OFF state of the switch S so that the pulse signal output circuit 10 outputs a pulse signal of a low level. Fig. 4 also shows a part of the operation of the secondary side circuit of the pulse signal output circuit 10, similarly to fig. 3 showing an example of the timing of switching the switch S included in the switch section 11. Fig. 4 also schematically shows the ON/OFF state of each switch S included in the switch section 11, the primary side voltage V1 of the primary coil of the pulse transformer 14, the primary side current i1 acting ON the primary coil of the pulse transformer 14, the rectified current i3 obtained by full-wave rectifying the secondary side current i2 according to the secondary side voltage V2 induced in the secondary coil of the pulse transformer 14 in the rectifying section 15, the rectified voltage V3 according to the rectified current i3, and the waveform (signal) and level of the ON/OFF state of the FET 18.

Also, similar to the example of the timing of switching the switch S included in the switch section 11 shown in fig. 3, it can be said that the waveform of the primary-side voltage V1 of the primary coil shown in fig. 4 is the same as the waveform of the secondary-side voltage V2 induced in the secondary coil of the pulse transformer 14. Therefore, in the following description, similarly to the example of the timing of switching the switch S included in the switch section 11 shown in fig. 3, the waveform of the primary-side voltage V1 of the primary coil of the pulse transformer 14 and the waveform of the secondary-side voltage V2 of the secondary coil will be appropriately substituted for each other.

At time t10, the switching timing controller 13 switches the switch S1 and the switch S4 from the OFF state to the ON state by the control signal CP, and switches the switch S2 and the switch S3 from the ON state to the OFF state by the control signal CN. Then, as described above, the voltage Vs output from the DC power supply PS acts on the primary side circuit of the pulse signal output circuit 10, and the primary side current i1 flows in the negative direction along the switch S3 included in the switch section 11, the primary side capacitor 12, the primary coil (from the second terminal B1 to the first terminal a1) of the pulse transformer 14, and the switch S2 included in the switch section 11. Therefore, the primary side voltage V1 having a voltage value of-2 Vs is applied to the primary coil of the pulse transformer 14. The waveform of the primary-side voltage V1 also oscillates due to the series resonant circuit formed by the inductance component of the primary coil of the pulse transformer 14 and the primary-side capacitor 12. The waveform of the secondary side voltage V2 induced in the secondary coil of the pulse transformer 14 also oscillates in accordance with the primary side voltage V1 of the primary coil of the pulse transformer 14.

As described above, in the secondary side circuit of the pulse signal output circuit 10, the rectified current i3 obtained by full-wave rectifying the secondary side current i2 according to the secondary side voltage V2 induced in the secondary coil of the pulse transformer 14 in the rectifying unit 15 flows. Since the rectified current i3 is obtained by full-wave rectification of the rectifying portion 15, the rectified current flows in the same direction as in the timing example shown in fig. 3 showing the switch S included in the switching portion 11. In other words, in the secondary side circuit of the pulse signal output circuit 10, the rectified current i3 flows in the same direction as in the case where the primary side current i1 is applied in the order of positive and negative directions. Therefore, in the secondary side circuit of the pulse signal output circuit 10, the rectified voltage V3 acts between the terminals of the secondary side capacitor 16, between the terminals of the secondary side resistance 17, and between the gate terminal and the source terminal of the FET in the same direction as in the case where the primary side current i1 is applied in the order of positive and negative directions. Therefore, in the pulse signal output circuit 10, similarly to the case where the primary side current i1 is applied in the order of positive and negative directions, the secondary side capacitor 16 is charged by the rectified current i3, and the FET18 is turned on by the rectified voltage V3 between the gate terminal and the source terminal, and transmits the pulse signal of the low level to the receiver RE.

After that, in the pulse signal output circuit 10, the voltage value of the primary side voltage V1 rises due to oscillation due to series resonance, and at time t11, the secondary side voltage V2 becomes a voltage value below the forward voltage of some of the diodes D (more specifically, the diode D2 and the diode D3) included in the rectifying section 15, whereby the diodes D turn off. Then, in the pulse signal output circuit 10, similarly to the timing example of the switch S included in the switching switch section 11 shown in fig. 3, the current value of the rectified current i3 obtained by full-wave rectification by the rectification section 15 becomes 0A, that is, the value of the rectified current i3 acting between the terminals of the secondary side capacitor 16 and between the terminals of the secondary side resistor 17 becomes zero. Therefore, in the pulse signal output circuit 10, similarly to the timing example of switching the switch S included in the switch section 11 shown in fig. 3, the rectified voltage V3 (the voltage between the gate terminal and the source terminal of the FET 18) according to the rectified current i3 also stops rising. In the pulse signal output circuit 10, if the rectified current i3 obtained by full-wave rectification of the rectifying section 15 becomes 0A, similarly to the case where the primary side current i1 is applied in the order of positive and negative directions, the charge stored in the secondary side capacitor 16 is discharged through the structure of the secondary side capacitor 16 and the secondary side resistor 17, and the FET18 is held in the ON state, and the pulse signal to be output is held at the low level.

Meanwhile, in the pulse signal output circuit 10, the switching timing controller 13 measures a time from the time T10 to determine whether or not it is a preset time, i.e., the switching time T. Here, the switching time T is a time calculated by the above expression 2. At time T12 when the measurement time reaches the switching time T, the switching timing controller 13 switches the switch S1 and the switch S4 from the OFF state to the ON state by the control signal CP, and switches the switch S2 and the switch S3 from the ON state to the OFF state by the control signal CN. As shown in fig. 4, the voltage value of the primary side voltage V1 remains increased even after time t11, and at time t12, the primary side voltage has a positive voltage value Va. Therefore, when the switching timing controller 13 switches the respective switches S, the primary side voltage V1 becomes a positive voltage value 2Vs + Va that is higher than the positive voltage value 2Vs according to the supplied current by the positive voltage value Va. Even in fig. 4, similarly to the example of the timing of switching the switch S included in the switch section 11 shown in fig. 3, the timing at which the oscillating waveform of the primary side voltage V1 has the first peak of the opposite polarity is represented as a timing t 12.

After that, in the pulse signal output circuit 10, the voltage value of the primary side voltage V1 decreases due to oscillation due to series resonance, and at time t13, the secondary side voltage V2 becomes a voltage value below the forward voltage of some of the diodes D (more specifically, the diode D1 and the diode D4) included in the rectifying section 15, whereby the diode D turns off. Then, in the pulse signal output circuit 10, similarly to the case at time t11, the current value of the rectified current i3 obtained by full-wave rectification by the rectifying section 15 becomes 0A, that is, the value of the rectified current i3 acting between the terminals of the secondary side capacitor 16 and between the terminals of the secondary side resistor 17 becomes zero, and the rectified voltage V3 (the voltage between the gate terminal and the source terminal of the FET 18) according to the rectified current i3 also stops rising. However, in the pulse signal output circuit 10, even if the rectified current i3 obtained by full-wave rectification of the rectifying section 15 becomes 0A at time t13, similarly to the case at time t11, the charge stored in the secondary side capacitor 16 is discharged through the structure of the secondary side capacitor 16 and the secondary side resistor 17, and the ON state of the FET18 is maintained. Therefore, in the pulse signal output circuit 10, similarly to the case of the time t11, the pulse signal to be output is kept at the low level.

as described above, in the pulse signal output circuit 10, even in the case where the switching timing controller 13 applies the primary side current i1 in the order of the negative and positive directions, at the time t12, the switching timing controller switches the respective switches S, whereby the pulse signal output circuit operates similarly to the case of the example of the timing of switching the switches S included in the switch section 11 shown in fig. 3. Therefore, in the pulse signal output circuit 10, even in the case where the primary side current i1 is applied in the order of negative and positive directions by the switching timing controller 13, the primary side voltage V1 can be changed to a higher voltage value at the time of switching the switch S, as compared with the case where the switch is switched when the polarity of the primary side voltage V1 is negative or when the voltage value of the primary side voltage is 0V. Therefore, in the pulse signal output circuit 10, even in the case where the switching timing controller 13 applies the primary side current i1 in the order of negative and positive, the primary side current i1 flowing in the primary coil of the pulse transformer 14 and the primary side capacitor 12 is higher, and the secondary side voltage V2 induced in the secondary coil of the pulse transformer 14 is also higher. Therefore, in the pulse signal output circuit 10, even in the case where the switching timing controller 13 applies the primary side current i1 in the order of negative and positive, the power transmission efficiency from the primary coil to the secondary coil of the pulse transformer 14 can be improved. Therefore, in the pulse signal output circuit 10, even in the case where the switching timing controller 13 applies the primary side current i1 in the order of the negative and positive directions, the secondary side current i2 flowing in accordance with the secondary side voltage V2 induced in the secondary coil of the pulse transformer 14, the rectified current i3 obtained by full-wave rectification by the rectifying section 15 are higher, and the rectified voltage V3 acting between the terminals of the secondary side capacitor 16, between the terminals of the secondary side resistor 17, and between the gate terminal and the source terminal of the FET in accordance with the rectified current i3 is also higher. Therefore, in the pulse signal output circuit 10, even in the case where the switching timing controller 13 applies the primary side current i1 in the order of negative and positive, the secondary side capacitor 16 is charged by the higher rectified current i3, and a high driving voltage of the gate terminal of the FET18 can be obtained.

As described above, in the pulse signal output circuit 10, the switching timing controller 13 switches the ON/OFF state of each switch S included in the switch section 11 when the oscillating waveform of the primary side voltage V1 has an opposite polarity regardless of the direction in which the primary side current i1 is applied for the first time (the order of the primary side current application directions). Therefore, in the pulse signal output circuit 10, regardless of the direction in which the primary side current i1 is first applied, the power transmission efficiency from the primary coil to the secondary coil of the pulse transformer 14 can be improved, and a high drive voltage to the gate terminal of the FET18 can be obtained.

Further, in the pulse signal output circuit 10, the switching timing controller 13 switches the ON/OFF state of each switch S at the timing when the oscillation waveform of the primary side voltage V1 has the first peak value of the opposite polarity and the absolute value of the voltage value is Va. Therefore, when switching the ON/OFF state of each switch S, the primary side voltage V1 can be changed to a voltage value of opposite polarity whose absolute value is greater than the absolute value of the voltage value of opposite polarity according to the supplied current by Va. Further, in the pulse signal output circuit 10, the switching timing controller 13 measures the switching time T calculated in advance based on the inductance value of the primary coil of the pulse transformer 14 and the capacitance value of the primary side capacitor 12 by a simple clock circuit such as a timer circuit or a CPU. Therefore, the ON/OFF state of the switch S can be switched at the timing when the oscillating waveform of the primary side voltage V1 has the first peak of the opposite polarity. Therefore, in the pulse signal output circuit 10, the power transmission efficiency from the primary coil to the secondary coil of the pulse transformer 14 can be improved, and a high driving voltage to the gate terminal of the FET18 can be obtained. Therefore, in the pulse signal output circuit 10, for example, by lowering the voltage Vs output from the DC power supply PS, the power consumption of the pulse signal output circuit 10 can be reduced. In the pulse signal output circuit 10, for example, an FET having a low threshold voltage can be used, and a diode having a low forward voltage can be used to configure the rectifying portion. In this way, since the limitation of the elements constituting the pulse signal output circuit 10 is relaxed, the elements can be easily selected.

In the pulse signal output circuit 10, a time (switching time T) indicating a timing at which the switching timing controller 13 switches the ON/OFF state of each switch S is calculated based ON the inductance value of the primary coil of the pulse transformer 14 and the capacitance value of the primary side capacitor 12, and is set in advance. In other words, in the pulse signal output circuit 10, the time required for the oscillating waveform of the primary side voltage V1 to have the first peak of the opposite polarity in the primary side circuit of the pulse signal output circuit 10 is calculated in advance. Also, the case has been explained: the pulse signal output circuit 10 is configured such that the switching timing controller 13 measures time from the timing (timing T10) at which the ON/OFF state of each switch S is switched, and sets the timing (timing T12) at which the measured time reaches the switching time T as the next timing at which the ON/OFF state of each switch S is switched. However, the pulse signal output circuit of the present invention is not limited to the structure in which the next timing of switching the ON/OFF state of each switch S is judged by measuring the predetermined time, and the pulse signal output circuit of the present invention may be configured to detect the next timing of switching the ON/OFF state of each switch S.

< second embodiment >

Now, a second embodiment of the present invention will be explained. Fig. 5 is a structural diagram showing the structure of a pulse signal output circuit according to a second embodiment of the present invention. The pulse signal output circuit 20 includes a switching section 11, a primary side capacitor 12, a switching timing controller 23, a pulse transformer 14, a rectifying section 15, a secondary side capacitor 16, a secondary side resistor 17, and an FET 18. Also, the switching timing controller 23 has a timing detection circuit 231. Fig. 5 also shows a DC power supply PS and a receiver RE connected to the pulse signal output circuit 20.

The pulse signal output circuit 20 has the same configuration as that of the pulse signal output circuit 10 of the first embodiment shown in fig. 1, except that it has a switching timing controller 23 instead of the switching timing controller 13. Other elements of the pulse signal output circuit 20 are the same as those of the pulse signal output circuit 10 of the first embodiment shown in fig. 1. Therefore, in the following description, among the elements of the pulse signal output circuit 20, the same elements as those of the pulse signal output circuit 10 of the first embodiment are denoted by the same reference numerals, and detailed description thereof will not be given.

Similar to the pulse signal output circuit 10, the pulse signal output circuit 20 also generates a pulse signal by switching the action direction of the primary side current i1 supplied from the DC power supply PS connected to the pulse signal output circuit by the switch section 11, thereby generating a pulse signal, and outputs the generated pulse signal to the receiver RE. Similar to pulse signal output circuit 10, pulse signal output circuit 20 can also be used, for example, in field devices.

Similarly to in the pulse signal output circuit 10, the primary side circuit and the secondary side circuit of the pulse signal output circuit 20 are also insulated from each other in the direct current mode by the pulse transformer 14. Similarly in the pulse signal output circuit 10, even in the primary side circuit of the pulse signal output circuit 20, the current supplied from the DC power supply PS connected to the pulse signal output circuit is applied as the primary side current i1 to the primary coil of the pulse transformer 14. Therefore, similarly in the pulse signal output circuit 10, even in the pulse signal output circuit 20, the secondary-side voltage V2 based on the primary-side voltage V1 acting between the first terminal a1 and the second terminal B1 of the primary coil of the pulse transformer 14 is induced between the first terminal a2 and the second terminal B2 of the secondary coil. Also, similarly in the pulse signal output circuit 10, even in the secondary side circuit of the pulse signal output circuit 20, the secondary side current i2 flowing in the secondary coil of the pulse transformer 14 is rectified, and based on the rectified voltage V3 (which is in accordance with the rectified current i3 obtained by the rectification), a pulse signal is generated, and the generated pulse signal is output to the receiver RE.

The primary side circuit of the pulse signal output circuit 20 is composed of the switch section 11, the primary side capacitor 12, the switching timing controller 23, and the primary coil of the pulse transformer 14. In the primary side circuit of the pulse signal output circuit 20, the first terminal a1 of the primary coil of the pulse transformer 14 (the first output terminal of the switch section 11) is connected to the timing detection circuit 231 included in the switching timing controller 23. However, instead of the first terminal a1 of the primary coil of the pulse transformer 14 (the first output terminal of the switching section 11), the second terminal B1 of the primary coil of the pulse transformer 14 (the first terminal of the primary-side capacitor 12) or the second terminal of the primary-side capacitor 12 (the second output terminal of the switching section 11) may be connected to the timing detection circuit 231. The other connection method in the primary-side circuit of the pulse signal output circuit 20 (i.e., the other connection method of the elements constituting the primary-side circuit of the pulse signal output circuit 20) is the same as the connection method of the elements in the primary-side circuit of the pulse signal output circuit 10.

The switching timing controller 23 controls each switch S included in the switch section 11, similarly to the switching timing controller 13 included in the pulse signal output circuit 10. However, in the switching timing controller 23, the timing detection circuit 231 detects each timing of switching the ON/OFF state of each switch S.

The timing detection circuit 231 acquires a voltage value of the primary-side voltage V1 applied to the primary coil of the pulse transformer 14 from the first terminal a1 (the first output terminal of the switch section 11) of the primary coil of the pulse transformer 14, and monitors the voltage value. Based ON the acquired and monitored voltage value of the primary-side voltage V1, the timing detection circuit 231 detects the timing of switching the ON/OFF state of each switch S included in the switch section 11.

As an element used for the timing detection circuit 231, a method for detecting each timing of switching the ON/OFF state of each switch S, which is used in the timing detection circuit 231, can be considered various elements (methods). For example, the timing detection circuit 231 may be provided with an integration circuit. The integration circuit may be implemented by a resistor and a capacitor. In this case, the timing detection circuit 231 integrates (sums) the voltage values of the primary-side voltage V1, and detects the timing at which the ON/OFF states of the respective switches S are switched based ON the integrated values. More specifically, the timing detection circuit 231 integrates (sums) the voltage values of the input primary side voltage V1 that alternate between two polarities (i.e., between positive and negative polarities). The timing detection circuit 231 detects a timing when the integrated (sum) value of the voltage value of the primary-side voltage V1 is 0 (for example, the output voltage of the integration circuit is 0V). The timing at which the integrated value of the voltage value of the primary-side voltage V1 is 0 can be regarded as a timing very close to: the oscillating waveform of the primary side voltage V1 that oscillates due to the series resonance of the primary side capacitor and the inductance component of the primary side of the pulse transformer has a timing of a peak of opposite polarity. Since the timing detection circuit 231 detects the timing at which the integrated value is 0, it is considered that, for example, even if the oscillating waveform of the primary-side voltage V1 changes, a timing very close to a timing at which the oscillating waveform has a peak value of opposite polarity can be detected as a timing at which the ON/OFF state of each switch S is switched.

Alternatively, for example, the timing detection circuit 231 may be provided with a differentiation circuit. The differentiating circuit may be implemented by a capacitor and a resistor. In this case, the timing detection circuit 231 differentiates the voltage value of the monitored input primary-side voltage V1, thereby detecting the timing at which the ON/OFF state of each switch S is switched. More specifically, the timing detection circuit 231 differentiates the voltage value of the primary side voltage V1 that alternates between the two polarities, thereby obtaining the slope of the oscillating waveform of the primary side voltage V1. The timing detection circuit 231 detects the timing at which the slope of the oscillating waveform of the primary-side voltage V1 obtained by differentiating the voltage value of the primary-side voltage V1 is 0 (for example, the output voltage of the differentiation circuit is 0V). The timing at which the slope of the oscillating waveform of the primary side voltage V1 is 0 can be regarded as being very close to the timing at which the waveform of the oscillating primary side voltage V1 has peaks of opposite polarity. Since the timing detection circuit 231 detects the timing at which the slope is 0, it is considered that, for example, even when the oscillation waveform of the primary-side voltage V1 changes, a timing very close to a timing at which the oscillation waveform has a peak of opposite polarity can be detected as a timing at which the ON/OFF state of each switch S is switched.

With such an element (method), the timing detection circuit 231 detects the timing of the opposite-polarity peak corresponding to the oscillating waveform of the primary-side voltage V1 as the timing of switching the ON/OFF state of each switch S. Then, if the timing of switching the ON/OFF state of each switch S is detected, the timing detection circuit 231 notifies it.

When receiving a notification from the timing detection circuit 231 that the timing of switching the ON/OFF states of the respective switches S has been detected (for example, when the integration value of the voltage value of the primary-side voltage V1 is 0 in the case where the timing detection circuit 231 is provided with an integration circuit), the switching timing controller 23 outputs the control signal C for switching the ON/OFF states of the respective switches S to the respective switches S included in the switch section 11. The control signal C output to each switch S by the switching timing controller 23 is the same as the control signal C output by the switching timing controller 13 included in the pulse signal output circuit 10. In this way, in the primary side circuit of the pulse signal output circuit 20, at the timing detected based ON the acquired and monitored voltage value of the primary side voltage V1, the ON/OFF states of the respective switches S included in the switch section 11 are switched, thereby switching (reversing) the direction of action of the primary side current i1 supplied from the DC power supply PS connected to the switch section 11 ON the primary coil of the pulse transformer 14. The timing at which the switching timing controller 23 switches the ON/OFF states of the respective switches S included in the switching section 11 will be described later.

The secondary side circuit of the pulse signal output circuit 20 is constituted by the secondary coil of the pulse transformer 14, the rectifier 15, the secondary side capacitor 16, the secondary side resistor 17, and the FET 18. The configuration of the secondary side circuit of the pulse signal output circuit 20 is the same as that of the secondary side circuit of the pulse signal output circuit 10. Therefore, the structure and operation of the secondary side circuit of the pulse signal output circuit 20 will not be specifically described.

With this configuration, the pulse signal output circuit 20 detects each timing of switching the direction of action of the primary side current i1 supplied from the DC power supply PS connected to the pulse signal output circuit. Also, at each detected timing, the pulse signal output circuit 20, similarly to the pulse signal output circuit 10, switches the direction of action of the primary side current i1 supplied from the DC power supply PS, thereby generating a pulse signal, and outputs the generated pulse signal to the receiver RE.

Now, the operation of the pulse signal output circuit 20 will be explained. The overall operation of the pulse signal output circuit 20 is the same as that of the pulse signal output circuit 10. In other words, by referring to the ON/OFF state of each switch S, the polarity of the waveforms of the primary side voltage V1 (secondary side voltage V2) and the secondary side current i2 in the overall operation of the pulse signal output circuit 10 shown in fig. 2, the overall operation of the pulse signal output circuit 20 can be easily derived along the direction of action of the primary side current i1 in the primary side circuit of the pulse signal output circuit 20. Therefore, without specifically describing the overall operation of the pulse signal output circuit 20, only the timing at which the switching timing controller 23 switches the ON/OFF state of each switch S included in the switch section 11 (the timing in one switching cycle) will be described with reference to fig. 6 with respect to the operations of the switching timing controller 23 and the timing detection circuit 231 included in the pulse signal output circuit 20. In the pulse signal output circuit 20 shown in fig. 5, similarly to the direction indicated by each of the primary side current i1, the secondary side current i2, and the rectified current i3 in the pulse signal output circuit 10 shown in fig. 1, the direction indicated by each of the primary side current i1, the secondary side current i2, and the rectified current i3 is a forward direction.

Fig. 6 is a waveform diagram for explaining an example of the timing at which the switch S included in the switch section 11 is switched in the pulse signal output circuit 20 according to the second embodiment of the present invention. An example of the timing of switching the switches S included in the switch section 11 shown in fig. 6 is an example corresponding to one cycle of the switches S in which the switching timing controller 23 switches the ON/OFF state of each switch S so that the pulse signal output circuit 20 outputs a pulse signal of a low level in the case where the timing detection circuit 231 of the switching timing controller 23 is constituted by an integration circuit. In other words, the example of the timing of switching the switches S included in the switch section 11 shown in fig. 6 is an example of a case where the timing detection circuit 231 included in the switching timing controller 23 integrates the acquired voltage value of the primary side voltage V1, and detects the timing at which the integrated value is 0 as the timing of switching the ON/OFF state of each switch S. Fig. 6 schematically shows the ON/OFF state of each switch S included in the switch section 11, the primary side voltage V1 of the primary coil of the pulse transformer 14, and the waveform (signal) and level of the change in the integral value of the voltage value of the primary side voltage V1 obtained by the timing detection circuit 231.

Also, similarly in the pulse signal output circuit 10, even in the pulse signal output circuit 20, the secondary side voltage V2 based on the primary side voltage V1 is induced in the secondary coil of the pulse transformer 14. Therefore, it can be said that the waveform of the primary-side voltage V1 of the primary coil shown in fig. 6 is the same as the waveform of the secondary-side voltage V2 induced in the secondary coil of the pulse transformer 14. Therefore, in the following description, similarly to the description of the example in which the primary side voltage and the secondary side voltage vary in the pulse signal output circuit 10, the waveform of the primary side voltage V1 of the primary coil of the pulse transformer 14 and the waveform of the secondary side voltage V2 of the secondary coil will be appropriately substituted for each other.

At time t20, the switching timing controller 23 switches the switch S1 and the switch S4 from the OFF state to the ON state by the control signal CP, and switches the switch S2 and the switch S3 from the ON state to the OFF state by the control signal CN. Then, the voltage Vs output from the DC power supply PS acts on the primary side circuit of the pulse signal output circuit 20, and the primary side current i1 flows in the forward direction along the switch S1 included in the switch section 11, the primary coil (from the first terminal a1 to the second terminal B1) of the pulse transformer 14, the primary side capacitor 12, and the switch S4 included in the switch section 11. Therefore, similarly in the pulse signal output circuit 10, the primary side voltage V1 having a voltage value of +2Vs is applied to the primary coil of the pulse transformer 14. Even in the pulse signal output circuit 20, similarly to in the pulse signal output circuit 10, the waveform of the primary side voltage V1 oscillates due to the series resonance circuit constituted by the inductance component of the primary coil of the pulse transformer 14 and the primary side capacitor 12.

At this time, the secondary side circuit of the pulse signal output circuit 20 also operates similarly to the secondary side circuit of the pulse signal output circuit 10. In other words, at the secondary coil of the pulse transformer 14, a secondary side voltage V2 based on the primary side voltage V1 of the primary coil of the pulse transformer 14 is induced. Also, even in the pulse signal output circuit 20, the waveform of the secondary side voltage V2 induced in the secondary coil of the pulse transformer 14 oscillates similarly to in the pulse signal output circuit 10. Moreover, even in the secondary side circuit of the pulse signal output circuit 20, similarly to in the secondary side circuit of the pulse signal output circuit 10, when the secondary side voltage V2 is induced in the secondary coil of the pulse transformer 14, the secondary side current i2 flows, and the rectifying section 15 full-wave rectifies the secondary side current, the rectified current i3 flows, whereby the rectified voltage V3 according to the rectified current i3 acts between the terminals of the secondary side capacitor 16, between the terminals of the secondary side resistor 17, and between the gate terminal and the source terminal of the FET. Therefore, even in the pulse signal output circuit 20, similarly to in the pulse signal output circuit 10, the secondary-side capacitor 16 is charged by the rectified current i3, and the FET18 is turned on by the rectified voltage V3 acting between the gate terminal and the source terminal, and transmits the pulse signal of the low level to the receiver RE.

After that, even in the pulse signal output circuit 20, similarly in the pulse signal output circuit 10, the primary side voltage V1 is lowered due to oscillation due to series resonance. In this case, the secondary side circuit of the pulse signal output circuit 20 operates similarly to the secondary side circuit of the pulse signal output circuit 10. In other words, when the voltage value of the primary side voltage V1 decreases in the primary side circuit of the pulse signal output circuit 20, in the secondary side circuit of the pulse signal output circuit 20, the diode D turns off when the secondary side voltage V2 falls below the forward voltage of some of the diodes D (more specifically, the diode D1 and the diode D4) included in the rectifying section 15. Then, even in the pulse signal output circuit 20, similarly in the pulse signal output circuit 10, the current value of the rectified current i3 obtained by full-wave rectification by the rectifying section 15 becomes 0A, that is, the value of the rectified current i3 acting between the terminals of the secondary side capacitor 16 and between the terminals of the secondary side resistor 17 becomes zero. Therefore, even in the pulse signal output circuit 20, similarly to in the pulse signal output circuit 10, the rectified voltage V3 according to the rectified current i3, that is, the voltage between the gate terminal and the source terminal of the FET18 stops rising. Even in the pulse signal output circuit 20, similarly to in the pulse signal output circuit 10, if the rectified current i3 obtained by full-wave rectification of the rectifying portion 15 becomes 0A, the electric charge stored in the secondary side capacitor 16 is discharged through the structure of the secondary side capacitor 16 and the secondary side resistor 17, so that the FET18 is held in the ON state. Therefore, even in the pulse signal output circuit 20, similarly in the pulse signal output circuit 10, the pulse signal to be output is kept at the low level.

Further, in the pulse signal output circuit 20, at time t20, the timing detection circuit 231 included in the pulse signal output circuit 20 starts integration (summation) of the voltage value of the primary side voltage V1. Therefore, when the primary-side voltage V1 having a voltage value of +2Vs is input, the integrated value of the voltage value of the primary-side voltage V1 obtained by the timing detection circuit 231 increases, and thereafter, the integrated value decreases as the voltage value of the primary-side voltage V1 decreases to the voltage value of-2 Vs. If the integrated value of the voltage value of the primary side voltage V1 becomes 0 at time t21, the timing detecting circuit 231 notifies that the timing of switching the ON/OFF state of each switch S has been detected. Then, the switching timing controller 23 switches each of the switch S1 and the switch S4 from the ON state to the OFF state by the control signal CP, and switches each of the switch S2 and the switch S3 from the OFF state to the ON state by the control signal CN. As shown in fig. 6, at time t21, the primary side voltage V1 becomes a negative voltage value lower by a negative voltage value-Va than the negative voltage value-2 Vs according to the supplied current. Therefore, when the switching timing controller 23 switches the respective switches S, the primary side voltage V1 becomes a negative voltage value- (2Vs + Va) that is lower than the negative voltage value according to the supplied current by a negative voltage value-Va.

After that, even in the pulse signal output circuit 20, similarly in the pulse signal output circuit 10, the voltage value of the primary side voltage V1 rises due to oscillation due to series resonance. At this time, the secondary side circuit of the pulse signal output circuit 20 operates similarly to the secondary side circuit of the pulse signal output circuit 10. In other words, when the voltage value of the primary side voltage V1 decreases in the pulse signal output circuit 20, if the secondary side voltage V2 decreases below the forward voltage of some of the diodes D (more specifically, the diode D2 or the diode D3) included in the rectifying section 15 in the secondary side circuit of the pulse signal output circuit 20, the diode D turns off. Then, even in the pulse signal output circuit 20, similarly in the pulse signal output circuit 10, the current value of the rectified current i3 obtained by full-wave rectification by the rectifying section 15 becomes 0A, that is, the value of the rectified current i3 acting between the terminals of the secondary side capacitor 16 and between the terminals of the secondary side resistor 17 becomes zero, and the rectified voltage V3 (the voltage between the gate terminal and the source terminal of the FET 18) according to the rectified current i3 also stops rising. However, even in the pulse signal output circuit 20, similarly to in the pulse signal output circuit 10, even if the rectified current i3 obtained by full-wave rectification of the rectifying section 15 becomes 0A, since the electric charge stored in the secondary side capacitor 16 is discharged through the structure of the secondary side capacitor 16 and the secondary side resistor 17, the ON state of the FET18 is maintained. Therefore, even in the pulse signal output circuit 20, similarly in the pulse signal output circuit 10, the pulse signal to be output is kept at the low level.

As described above, in the pulse signal output circuit 20, after the switching timing controller 23 switches the ON/OFF state of each switch S at time t20, each of the timing controller switching switches the switches S at time t21 at which the timing detection circuit 231 has detected the ON/OFF state of each switch S. Therefore, even in the pulse signal output circuit 20, similarly to the case where the switch is switched when the polarity of the primary side voltage V1 is positive or when the voltage value of the primary side voltage is 0V in the pulse signal output circuit 10, the primary side voltage V1 can be changed to a voltage value having a larger absolute value when the switch S is switched. Therefore, even in the pulse signal output circuit 20, similarly to in the pulse signal output circuit 10, the primary-side current i1 flowing in the primary coil of the pulse transformer 14 and the primary-side capacitor 12 is higher, and the secondary-side voltage V2 induced in the secondary coil of the pulse transformer 14 is also larger. In other words, even in the pulse signal output circuit 20, similarly to in the pulse signal output circuit 10, the power transmission efficiency from the primary coil to the secondary coil of the pulse transformer 14 can be improved. Therefore, even in the pulse signal output circuit 20, similarly to in the pulse signal output circuit 10, the secondary side current i2 flowing due to the secondary side voltage V2 induced in the secondary coil of the pulse transformer 14 and the rectified current i3 obtained by full-wave rectification by the rectifying section 15 are also larger, and the rectified voltage V3 according to the rectified current i3 acting between the terminals of the secondary side capacitor 16, between the terminals of the secondary side resistor 17, and between the gate terminal and the source terminal of the FET is also higher. Therefore, even in the pulse signal output circuit 20, similarly to in the pulse signal output circuit 10, the secondary-side capacitor 16 is charged by the larger amount of the rectified current i3, and a high drive voltage to the gate terminal of the FET18 can be obtained.

In fig. 6, the switching timing controller 23 applies the primary side current i1 to the primary side circuit of the pulse signal output circuit 20 in the order of positive and negative directions, whereby the pulse signal output circuit 20 outputs a pulse signal of a low level. However, even in the pulse signal output circuit 20, similarly to in the pulse signal output circuit 10, even in the case where the primary side current i1 is applied to the primary side circuit of the pulse signal output circuit 20 in the order of negative and positive, a pulse signal of a low level can be output. Switching the operations of the timing controller 23 and the timing detection circuit 231 in this case can be easily derived by inverting the polarity of the waveform of the change in the ON/OFF state of each switch S, the primary side voltage V1 of the primary coil of the pulse transformer 14, and the integrated value of the voltage value of the primary side voltage V1 obtained by the timing detection circuit 231. Therefore, the operation of the pulse signal output circuit 20 in the case where the primary side current i1 is applied to the primary side circuit of the pulse signal output circuit 20 in the order of negative and positive is not specifically described.

As described above, in the pulse signal output circuit 20, the voltage value of the primary side voltage V1 acting ON the primary coil of the pulse transformer 14 is input to the timing detection circuit 231 included in the switching timing controller 23, and based ON the voltage value of the primary side voltage V, the timing detection circuit 231 detects the timing of switching the ON/OFF state of each switch S included in the switch section 11. In this configuration, regardless of the direction in which the primary side current i1 is applied for the first time (the order of the directions in which the primary side currents act), the timing detection circuit 231 detects a timing very close to a timing at which the oscillating waveform of the primary side voltage V1 has a peak of opposite polarity. Further, in the pulse signal output circuit 20, the switching timing controller 23 switches the ON/OFF states of the respective switches S included in the switch section 11 at a timing that has been detected by the timing detection circuit 231 as switching the ON/OFF states of the respective switches S. Therefore, even in the pulse signal output circuit 20, similarly to in the pulse signal output circuit 10, regardless of the direction in which the primary side current i1 is applied for the first time, the power transmission efficiency from the primary coil to the secondary coil of the pulse transformer 14 can be improved, and a high drive voltage to the gate terminal of the FET18 can be obtained.

Further, in the pulse signal output circuit 20, based ON the voltage value of the primary side voltage V1 that is input and monitored, the timing detection circuit 231 included in the switching timing controller 23 can more reliably detect, as the timing to switch the ON/OFF state of each switch S, the timing at which the oscillating waveform of the primary side voltage V1 has a peak value of opposite polarity. Therefore, in the pulse signal output circuit 20, in addition to the same effects as those of the pulse signal output circuit 10, other effects such as improvements in the following can be achieved: constant variations of the respective elements of the pulse signal output circuit 20 due to temperature rises of the elements are resisted, and the influence of constant unevenness of the elements is resisted.

As described above, according to the embodiment of the present invention, the pulse signal output circuit includes the switching timing controller. Further, in the embodiment of the present invention, the switching timing controller switches the ON/OFF state of each switch included in the switch section after the oscillating waveform of the voltage of the primary side circuit is changed to the opposite polarity. Therefore, in the embodiment of the present invention, it is possible to improve the power transmission efficiency from the primary coil to the secondary coil of the pulse transformer included in the pulse signal output circuit, and to obtain a high driving voltage to the gate terminal of the FET provided in the secondary side circuit and configured to be turned on and off in accordance with the voltage applied to the gate terminal, thereby generating the pulse signal and outputting the pulse signal.

Also, in the embodiment of the present invention, the switching timing controller switches the ON/OFF states of the respective switches included in the switch section at the timing when the oscillating waveform of the voltage of the primary side circuit has a peak value of opposite polarity. Therefore, in the embodiment of the present invention, the voltage of the primary side circuit can be changed to a voltage value having the following absolute value when switching the ON/OFF state of each switch: the absolute value of the peak of opposite polarity is higher than the absolute value according to the voltage value of the supplied current. Therefore, in the embodiment of the present invention, it is possible to improve the power transmission efficiency from the primary coil to the secondary coil of the pulse transformer included in the pulse signal output circuit, and it is possible to obtain a high driving voltage to the gate terminal of the FET for generating and outputting the pulse signal.

however, the configuration of the embodiment of the present invention is applicable to the basic configuration of the pulse signal output circuit, that is, the configuration other than the switching timing controller is not limited to the configuration described in the embodiment of the present invention. In other words, the basic structure of the pulse signal output circuit may be configured to include a switching timing controller for switching the ON/OFF state of each switch after the oscillating waveform of the voltage applied to the primary coil of the pulse transformer becomes opposite polarity, and the basic structure of the pulse signal output circuit may be different from that shown in the embodiment of the present invention.

< first modification >

Now, a pulse signal output circuit having another structure including a switching timing controller will be described. Fig. 7 is a configuration diagram showing the configuration of a pulse signal output circuit according to a first modification of the present invention. The pulse signal output circuit 30 includes a switching section 11, a primary side resistor 31, a primary side capacitor 12, a switching timing controller 13, a pulse transformer 14, a rectifying section 15, a secondary side capacitor 16, a secondary side resistor 17, and an FET 18. Fig. 7 also shows the DC power supply PS and the receiver RE connected to the pulse signal output circuit 30. Similarly to the direction indicated by each of the primary side current i1, the secondary side current i2, and the rectified current i3 in the pulse signal output circuit 10 shown in fig. 1, in the pulse signal output circuit 30 shown in fig. 7, the direction indicated by each of the primary side current i1, the secondary side current i2, and the rectified current i3 is the forward direction.

the pulse signal output circuit 30 has the same structure as the pulse signal output circuit 10 of the first embodiment shown in fig. 1 except that it further includes a primary side resistor 31. Other elements of the pulse signal output circuit 30 are the same as those of the pulse signal output circuit 10 of the first embodiment shown in fig. 1. Therefore, in the following description, among the elements of the pulse signal output circuit 30, the same elements as those of the pulse signal output circuit 10 of the first embodiment are denoted by the same reference numerals, and detailed description thereof will not be given.

Similarly to the pulse signal output circuit 10 and the pulse signal output circuit 20, the pulse signal output circuit 30 also switches the action direction of the primary side current i1 supplied from the DC power supply PS connected to the pulse signal output circuit through the switch section 11, thereby generating a pulse signal, and outputs the generated pulse signal to the receiver RE. Similar to pulse signal output circuit 10 and pulse signal output circuit 20, pulse signal output circuit 30 can also be applied to a field device, for example.

The primary side circuit of the pulse signal output circuit 30 is configured by adding a primary side resistor 31 between the switch unit 11 and the primary coil of the pulse transformer 14 to the primary side circuit of the pulse signal output circuit 10. More specifically, in the primary side circuit of the pulse signal output circuit 30, a first terminal of the primary side resistor 31 is connected to a first output terminal of the switch section 11, and a second terminal of the primary side resistor 31 is connected to a first terminal a1 of the primary coil of the pulse transformer 14. However, the primary side resistor 31 is not limited to a single resistor, and a plurality of resistors may be provided. Also, in the primary side circuit of the pulse signal output circuit 30, the primary side resistance 31 may be arranged at an arbitrary position on a path for applying the primary side current i1 from the switching section 11 to the pulse transformer 14. Other connections in the primary side circuit of the pulse signal output circuit 30 (i.e., other connections of the elements constituting the primary side circuit of the pulse signal output circuit 30) are the same as those of the elements of the primary side circuit of the pulse signal output circuit 10.

In the pulse signal output circuit 30, due to the primary side resistance 31, the oscillation of the primary side voltage V1 and the primary side current i1 applied to the primary coil of the pulse transformer 14 due to the series resonance of the primary coil of the pulse transformer 14 and the primary side capacitor 12 can be suppressed compared to the pulse signal output circuit 20 and the pulse signal output circuit 10. In other words, in the pulse signal output circuit 30, the oscillation of the primary side voltage V1 and the primary side current i1 can be quickly suppressed by the primary side resistor 31. More specifically, in the pulse signal output circuit 10 and the pulse signal output circuit 20, the damping degree of the oscillation of the primary side voltage V1 is determined according to the resistance value of each switch S in the ON state included in the switch section 11. In the pulse signal output circuit 30, the damping degree of the oscillation of the primary side voltage V1 is determined based ON the resistance value of each switch S in the ON state and the resistance value of the primary side resistor 31. Therefore, in the pulse signal output circuit 30, in the case where it is desired to quickly suppress the oscillation of the primary side voltage V1 to reduce the additional current consumption of the primary side circuit, the oscillation of the primary side voltage V1 can be easily and quickly suppressed by determining the resistance value of the primary side resistance 31.

Also, even in the pulse signal output circuit 30, similarly in the pulse signal output circuit 10, the switching timing controller 13 switches the ON/OFF states of the respective switches included in the switching section 11 after the oscillating waveform of the primary side voltage V1 becomes opposite polarity. Therefore, even in the pulse signal output circuit 30, similarly to in the pulse signal output circuit 10, when the primary-side voltage has a voltage value of opposite polarity whose absolute value is Va, the ON/OFF state of each switch S is switched. Therefore, when the ON/OFF state of each switch S is switched, the primary side voltage becomes a voltage value whose absolute value is greater than the absolute value of the voltage value according to the supplied current by Va. However, even in the pulse signal output circuit 30, similarly to in the pulse signal output circuit 10, even after switching the ON/OFF states of the respective switches S, the primary side voltage V1 oscillates due to the series resonance of the primary coil of the pulse transformer 14 and the primary side capacitor 12 (see the waveform of the primary side voltage V1 (secondary side voltage V2) in the pulse signal output circuit 10 shown in fig. 3 or fig. 4). The primary side resistor 31 of the pulse signal output circuit 30 helps to converge the oscillation of the primary side voltage V1 more quickly, particularly after the switching timing controller 13 switches the ON/OFF state of each switch S, thereby reducing additional current consumption of the primary side circuit.

Meanwhile, the structure of the secondary side circuit of the pulse signal output circuit 30 is the same as that of the secondary side circuit of the pulse signal output circuit 10. Therefore, the structure and operation of the secondary side circuit of the pulse signal output circuit 30 are not specifically described. Also, the overall operation of the pulse signal output circuit 30 and the timing at which the switching timing controller 13 switches the ON/OFF states of the respective switches S are the same as in the case of the pulse signal output circuit 10, except that the oscillating waveform of the primary side voltage V1 converges quickly. Therefore, the overall operation of the pulse signal output circuit 30 and the timing at which the switching timing controller 13 switches the ON/OFF states of the respective switches S are not specifically described.

As described above, even in the pulse signal output circuit 30, similarly to in the pulse signal output circuit 10, when the oscillation waveform of the primary side voltage V1 has the opposite polarity, the switching timing controller 13 switches the ON/OFF state of each switch S included in the switching section 11. Therefore, even in the pulse signal output circuit 30, the same effect as that of the pulse signal output circuit 10 can be achieved. In other words, even in the pulse signal output circuit 30, similarly to in the pulse signal output circuit 10, the power transmission efficiency from the primary coil to the secondary coil of the pulse transformer 14 can be improved, and a high drive voltage to the gate terminal of the FET18 can be realized. Moreover, in the pulse signal output circuit 30, since the primary side resistor 31 is added to the primary side circuit, it is possible to quickly converge the oscillation of the primary side voltage V1 and the primary side current i1 (particularly the oscillation of the primary side voltage V1 after the switching timing controller 13 switches the ON/OFF state of each switch S), thereby reducing the additional current power consumption of the primary side circuit due to the oscillation of the primary side voltage V1.

< second modification >

Now, a pulse signal output circuit having another structure including a switching timing controller will be described. Fig. 8 is a configuration diagram showing the configuration of a pulse signal output circuit according to a second modification of the present invention. The pulse signal output circuit 40 includes a switching section 11, a primary side capacitor 12, a switching timing controller 13, a pulse transformer 14, a rectifying section 45, a secondary side capacitor 16, a secondary side resistor 17, and an FET 18. Fig. 8 also shows the DC power supply PS and the receiver RE connected to the pulse signal output circuit 40. In the pulse signal output circuit 40 shown in fig. 8, similarly to the direction indicated by each of the primary side current i1, the secondary side current i2, and the rectified current i3 in the pulse signal output circuit 10 shown in fig. 1, the direction indicated by each of the primary side current i1, the secondary side current i2, and the rectified current i3 is a forward direction.

the pulse signal output circuit 40 has the same configuration as that of the pulse signal output circuit 10 of the first embodiment shown in fig. 1, except that it has a rectifying section 45 instead of the rectifying section 15. Other elements of the pulse signal output circuit 40 are the same as those of the pulse signal output circuit 10 of the first embodiment shown in fig. 1. Therefore, in the following description, among the elements of the pulse signal output circuit 40, the same elements as those of the pulse signal output circuit 10 of the first embodiment are denoted by the same reference numerals, and detailed description thereof will not be given.

Similarly to the pulse signal output circuit 10 to the pulse signal output circuit 30, the pulse signal output circuit 40 also switches the action direction of the primary side current i1 supplied from the DC power supply PS connected to the pulse signal output circuit through the switch section 11, thereby generating a pulse signal, and outputs the generated pulse signal to the receiver RE. Similar to the pulse signal output circuit 10 to the pulse signal output circuit 30, the pulse signal output circuit 40 can also be applied to, for example, a field device.

The configuration of the primary-side circuit of the pulse signal output circuit 40 is the same as that of the primary-side circuit of the pulse signal output circuit 10. Therefore, the configuration and operation of the primary side circuit of the pulse signal output circuit 40 will not be specifically described.

The secondary side circuit of the pulse signal output circuit 40 has the same configuration as that of the secondary side circuit of the pulse signal output circuit 10, except that it has a rectifying section 45 instead of the rectifying section 15. More specifically, in the secondary side circuit of the pulse signal output circuit 40, the first terminal a2 of the secondary coil of the pulse transformer 14 is connected to the first input terminal of the rectifying section 45, and the second terminal B2 of the secondary coil of the pulse transformer 14 is connected to the second input terminal of the rectifying section 45. In the secondary side circuit of the pulse signal output circuit 40, a first output terminal of the rectifying unit 45 is connected to the first terminal of the secondary side capacitor 16, the first terminal of the secondary side resistor 17, and the gate terminal of the FET 18. In the secondary side circuit of the pulse signal output circuit 40, the second output terminal of the rectifier 45 is connected to the second terminal of the secondary side capacitor 16, the second terminal of the secondary side resistor 17, and the source terminal (and back gate terminal) of the FET18, and this connection point serves as the second output terminal O2 of the pulse signal output circuit 40. The other connections of the secondary side circuit of the pulse signal output circuit 40 (i.e., the other connections of the elements constituting the secondary side circuit of the pulse signal output circuit 40) are the same as those of the elements of the secondary side circuit of the pulse signal output circuit 10.

The rectifying section 45 rectifies a voltage supplied between the first input terminal and the second input terminal, and supplies the rectified voltage between the first output terminal and the second output terminal. In other words, the rectifying section 45 also supplies a rectified voltage between the gate terminal and the source terminal of the FET18 and between the terminals of each of the secondary-side capacitor 16 and the secondary-side resistor 17, similarly to the rectifying section 15. The rectifying section 45 has a capacitor C1, a diode D5, and a diode D6. The rectifying unit 45 is a voltage doubler rectifier circuit including a capacitor C1, a diode D5, and a diode D6, and rectifies a voltage supplied between the first input terminal and the second input terminal to double the rectified voltage, thereby supplying the double-rectified voltage between the first output terminal and the second output terminal. In the following description, when it is not necessary to distinguish between the diode D5 and the diode D6 included in the rectifying unit 45, they are referred to as a diode D.

In the rectifying section 45, a first terminal of the capacitor C1 serves as a first input terminal of the rectifying section 45, and is connected to a first terminal a2 of the secondary coil of the pulse transformer 14. Further, in the rectifying section 45, the second terminal of the capacitor C1 is connected to the anode terminal of the diode D5 and the cathode terminal of the diode D6. Also, in the rectifying section 45, the cathode terminal of the diode D5 serves as a first output terminal of the rectifying section 45, and is connected to the first terminal of the secondary side capacitor 16, the first terminal of the secondary side resistor 17, and the gate terminal of the FET 18. Also, in the rectifying section 45, the anode terminal of the diode D6 serves as a second input terminal of the rectifying section 45, is connected to the second terminal B2 of the secondary coil of the pulse transformer 14, and serves as a second output terminal of the rectifying section 45, is connected to the second terminal of the secondary-side capacitor 16, the second terminal of the secondary-side resistor 17, and the source terminal of the FET18, and serves as a second output terminal O2 of the pulse signal output circuit 40.

When a negative voltage is supplied between the first output terminal and the second output terminal of the rectifying section 45, the capacitor C1 is charged by the supplied voltage, and when a positive voltage is supplied, the rectifying section commonly outputs the supplied positive voltage and the charged voltage of the capacitor C1, that is, twice the supplied voltage, in a positive direction because the charges stored in the capacitor C1 are discharged. In the secondary side circuit of the pulse signal output circuit 40, when a negative voltage is induced as the secondary side voltage V2 in the secondary coil of the pulse transformer 14, the capacitor C1 included in the rectifying section 45 is charged by the secondary side voltage V2. Also, in the secondary side circuit of the pulse signal output circuit 40, when a positive voltage is induced as the secondary side voltage V2 in the secondary coil of the pulse transformer 14, the positive secondary side voltage V2 and the secondary side voltage V2 of the charged capacitor C1, that is, twice the secondary side voltage V2, act between the gate terminal and the source terminal of the FET18 and between the terminals of each of the secondary side capacitor 16 and the secondary side resistor 17. Thus, in the primary side circuit of the pulse signal output circuit 40, the rectified voltage V3, which is twice the rectified voltage of the pulse signal output circuit 10, acts between the gate terminal and the source terminal of the FET 18.

in the pulse signal output circuit 40, since the rectifying section 45 replaces the rectifying section 15 included in the pulse signal output circuit 10, the number of diodes D is reduced to two despite the addition of the capacitor C1. In other words, in the pulse signal output circuit 40, the number of elements constituting the secondary side circuit is reduced by one due to the reduction in the number of diodes D. Also, generally, the mounting area of the capacitor is smaller than that of the diode. Therefore, in the pulse signal output circuit 40, the rectifying section 45 in place of the rectifying section 15 included in the pulse signal output circuit 10 contributes to realizing the pulse signal output circuit 40 in a smaller size at a lower cost.

In addition, the overall operation of the pulse signal output circuit 40 and the timing at which the switching timing controller 13 switches the ON/OFF states of the respective switches S are the same as in the case of the pulse signal output circuit 10, except that the rectifying section 45 outputs the rectified voltage V3. Therefore, the overall operation of the pulse signal output circuit 40 and the timing at which the switching timing controller 13 switches the ON/OFF states of the respective switches S are not specifically described.

As described above, even in the pulse signal output circuit 40, similarly to in the pulse signal output circuit 10, when the oscillation waveform of the primary side voltage V1 has the opposite polarity, the switching timing controller 13 switches the ON/OFF state of each switch S included in the switching section 11. Therefore, even in the pulse signal output circuit 40, the same effect as that of the pulse signal output circuit 10 can be achieved. In other words, even in the pulse signal output circuit 40, similarly to in the pulse signal output circuit 10, the power transmission efficiency from the primary coil to the secondary coil of the pulse transformer 14 can be improved, and a high drive voltage to the gate terminal of the FET18 can be realized. In the pulse signal output circuit 40, the rectifier 45 is provided in place of the rectifier 15 included in the secondary circuit of the pulse signal output circuit 10. Therefore, the number of elements constituting the secondary side circuit and the mounting area can be reduced, and the pulse signal output circuit 40 can be realized in a smaller size at a lower cost.

< third modification >

Now, a pulse signal output circuit having another structure including a switching timing controller will be described. Fig. 9 is a configuration diagram showing the configuration of a pulse signal output circuit according to a third modification of the present invention. The pulse signal output circuit 50 includes a buffer (output voltage selection circuit) 51, a primary side capacitor 12, a switching timing controller 13, a pulse transformer 14, a rectifying section 15, a secondary side capacitor 16, a secondary side resistor 17, and an FET 18. Fig. 9 also shows the DC power supply PS and the receiver RE connected to the pulse signal output circuit 50. In the pulse signal output circuit 50 shown in fig. 9, similarly to the direction indicated by each of the primary side current i1, the secondary side current i2, and the rectified current i3 in the pulse signal output circuit 10 shown in fig. 1, the direction indicated by each of the primary side current i1, the secondary side current i2, and the rectified current i3 is a forward direction.

The pulse signal output circuit 50 has the same configuration as that of the pulse signal output circuit 10 of the first embodiment shown in fig. 1, except that it has a buffer 51 instead of the switch section 11. Other elements of the pulse signal output circuit 50 are the same as those of the pulse signal output circuit 10 of the first embodiment shown in fig. 1. Therefore, in the following description, among the elements of the pulse signal output circuit 50, the same elements as those of the pulse signal output circuit 10 of the first embodiment are denoted by the same reference numerals, and detailed description thereof will not be given.

Similarly to the pulse signal output circuit 10 to the pulse signal output circuit 40, the pulse signal output circuit 50 also switches the acting direction of the primary side current i1 on the primary coil of the pulse transformer 14, thereby generating a pulse signal, and outputs the generated pulse signal to the receiver RE. In the pulse signal output circuit 10, the switch 11 switches the direction in which the primary side current i1 acts on the primary coil of the pulse transformer 14, whereas in the pulse signal output circuit 50, the buffer 51 switches the direction in which the primary side current acts. Similar to pulse signal output circuit 10 to pulse signal output circuit 40, pulse signal output circuit 50 can also be used for field devices, for example.

The primary-side circuit of the pulse signal output circuit 50 has the same configuration as that of the primary-side circuit of the pulse signal output circuit 10 except that it has a buffer 51 instead of the switch section 11. More specifically, in the primary side circuit of the pulse signal output circuit 50, the power supply terminal of the buffer 51 is connected to the positive terminal of the DC power supply PS. Also, in the primary side circuit of the pulse signal output circuit 50, the buffer 51 has an input terminal to which the control signal CS is applied from the switching timing controller 13. Also, in the primary side circuit of the pulse signal output circuit 50, the buffer 51 has an output terminal connected to the first terminal a1 of the primary coil of the pulse transformer 14. Also, in the primary side circuit of the pulse signal output circuit 50, the buffer 51 has a reference terminal to which a reference voltage is applied and which is connected to the second terminal of the primary side capacitor 12. Other connections of the primary side circuit of the pulse signal output circuit 50 (i.e., other connections of the elements constituting the primary side circuit of the pulse signal output circuit 50) are the same as those of the elements of the primary side circuit of the pulse signal output circuit 10.

The buffer 51 selects one of the voltage Vs supplied from the DC power supply PS connected to the power source terminal and the reference voltage as an output voltage according to the control signal CS input from the switching timing controller 13, and outputs the selected voltage to the output terminal. As shown by the area surrounded by the dotted line in fig. 9, a circuit equivalent to the buffer 51 is a switch for switching the connection of the output terminal between the power source terminal and the reference terminal in accordance with the control signal CS input from the switching timing controller 13. Therefore, the buffer 51 can be said to be a switch portion.

In the primary side circuit of the pulse signal output circuit 50, similarly to the switching section 11 included in the pulse signal output circuit 10, the connection of the output terminal of the buffer 51 is switched between the power supply terminal and the reference terminal, thereby switching the acting direction of the primary side current i1 on the primary coil of the pulse transformer 14. Therefore, in the primary side circuit of the pulse signal output circuit 50, the primary side capacitor 12 functions as an element for storing electric charges according to the voltage Vs output from the buffer 51. In other words, the primary-side capacitor 12 is charged by the voltage Vs. An operation of switching the acting direction of the primary side current i1 on the primary coil of the pulse transformer 14 in the primary side circuit of the pulse signal output circuit 50 will be described later.

The switching timing controller 13 controls switching of connection of the output terminal of the buffer 51. As shown in fig. 9, in the pulse signal output circuit 50, one control signal CS output from the switching timing controller 13 is input to an input terminal of a buffer 51. The control signal CS is a control signal corresponding to a control signal CP output from the switching timing controller 13 included in the pulse signal output circuit 10.

Meanwhile, the structure of the secondary side circuit of the pulse signal output circuit 50 is the same as that of the secondary side circuit of the pulse signal output circuit 10. Therefore, the structure and operation of the secondary side circuit of the pulse signal output circuit 50 will not be specifically described.

Now, the operation of the pulse signal output circuit 50 will be explained. In addition, the overall operation of the pulse signal output circuit 50 and the timing at which the switching timing controller 13 switches the ON/OFF states of the respective switches S are the same as in the case of the pulse signal output circuit 10. Therefore, the overall operation of the pulse signal output circuit 50 and the timing at which the switching timing controller 13 switches the ON/OFF states of the respective switches S will not be specifically described. However, in the pulse signal output circuit 50, the connection of the output terminal of the buffer 51 is switched between the power source terminal and the reference terminal in accordance with the control signal CS output from the switching timing controller 13, thereby switching the acting direction of the primary side current i1 on the primary coil of the pulse transformer 14. Therefore, hereinafter, with respect to the operation of switching the acting direction of the primary side current i1 on the primary coil of the pulse transformer 14 in the pulse signal output circuit 50, the operation of the primary side circuit of the pulse signal output circuit 50 will be explained.

Fig. 10 is a waveform diagram for explaining an example of a timing of switching the direction of action of the primary side current i1 on the primary side circuit in the pulse signal output circuit 50 according to the third modification of the present invention. An example of the timing of switching the acting direction of the primary side current i1 on the primary side circuit shown in fig. 10 is an example corresponding to a period in which the timing controller 13 switches the connection of the output terminal of the buffer 51 so that the pulse signal output circuit 50 outputs a pulse signal of a low level. In other words, similar to the example of the overall operation of the pulse signal output circuit 10 shown in fig. 2, the example of the timing of switching the acting direction of the primary side current i1 on the primary side circuit shown in fig. 10 is an example corresponding to a period in which the switching timing controller 13 alternately switches the control signal CS in the operation of the pulse signal output circuit 50. Fig. 10 schematically shows the waveform (signal) and level of the output of the buffer 51 (buffer output), the primary side voltage V1 of the primary coil of the pulse transformer 14, and the primary side current i1 applied to the primary coil of the pulse transformer 14.

Even in the pulse signal output circuit 50, similarly in the pulse signal output circuit 10, the secondary side voltage V2 based on the primary side voltage V1 is induced in the secondary coil of the pulse transformer 14. Therefore, it can be said that the waveform of the primary-side voltage V1 of the primary coil shown in fig. 10 is the same as the waveform of the secondary-side voltage V2 induced in the secondary coil of the pulse transformer 14, but the voltage values thereof are different. Therefore, in the following description, the waveform of the primary side voltage V1 of the primary coil of the pulse transformer 14 and the waveform of the secondary side voltage V2 of the secondary coil will be appropriately substituted for each other.

in order for the pulse signal output circuit 50 to output a pulse signal of a low level, at time t50, the switching timing controller 13 controls the buffer 51 by the control signal CS so that the output terminal of the buffer is connected to the power source terminal. Accordingly, the buffer 51 outputs the voltage Vs (i.e., + Vs) output from the DC power supply PS connected to the power supply terminal to the output terminal. Then, in the primary side circuit of the pulse signal output circuit 50, a primary side current i1 flows in the forward direction along the primary coil (from the first terminal a1 to the second terminal B1) of the pulse transformer 14 and the primary side capacitor 12. Accordingly, the primary-side capacitor 12 is charged by the primary-side current i1, that is, stores the charge according to the voltage Vs output from the buffer 51. Further, similarly in the pulse signal output circuit 10, the voltage Vs output from the buffer 51 (i.e., the primary side voltage V1 having a voltage value of + Vs) is also applied to the primary coil of the pulse transformer 14. Even in the pulse signal output circuit 50, similarly to in the pulse signal output circuit 10, the waveform of the primary side voltage V1 oscillates due to the series resonance circuit constituted by the inductance component of the primary coil of the pulse transformer 14 and the primary side capacitor 12.

At this time, in the secondary side circuit of the pulse signal output circuit 50, a secondary side voltage V2 based on the primary side voltage V1 of the primary side coil of the pulse transformer 14 is induced in the secondary side coil of the pulse transformer 14. Also, even in the pulse signal output circuit 50, the waveform of the secondary side voltage V2 induced in the secondary coil of the pulse transformer 14 oscillates similarly to in the pulse signal output circuit 10. Therefore, the secondary side circuit of the pulse signal output circuit 50 also operates similarly to the secondary side circuit of the pulse signal output circuit 10. Therefore, even in the pulse signal output circuit 50, similarly to in the pulse signal output circuit 10, the secondary-side capacitor 16 is charged by the rectified current i3, and the FET18 is turned on by the rectified voltage V3 applied between the gate terminal and the source terminal, and transmits the pulse signal of the low level to the receiver RE.

After that, even in the pulse signal output circuit 50, similarly in the pulse signal output circuit 10, the primary side voltage V1 decreases due to oscillation based on series resonance. In addition, even in the pulse signal output circuit 50, similarly in the pulse signal output circuit 10, at the time T50, the switching timing controller 13 starts measuring the preset time (switching time T). Thereafter, at a time T51 when the measurement time reaches the preset time (switching time T), the switching timing controller 13 controls the buffer 51 by the control signal CS so that the output terminal of the buffer is connected to the reference terminal. In other words, in the pulse signal output circuit 50, at the time T51 when the time measured by the switching timing controller 13 reaches the preset time (switching time T), the DC power supply PS is disconnected from the buffer 51. Then, in the pulse signal output circuit 50, the electric charge stored in the secondary-side capacitor 16 by the voltage Vs is discharged. Therefore, the primary side current i1 flows from the second terminal B1 to the first terminal in the primary coil of the pulse transformer 14. In other words, the primary-side current i1 flows in the negative direction in the pulse signal output circuit 50. Thus, the primary side voltage V1 having a voltage value of-Vs is applied to the primary coil of the pulse transformer 14.

In this configuration, as shown in fig. 10, the connection of the output terminal of the buffer is switched at time t51 when the primary side voltage V1 has a negative voltage value-Va. Therefore, in the pulse signal output circuit 50, the electric charge stored in the primary side capacitor 12 by the voltage Vs is discharged, whereby the negative voltage-Vs acts on the primary coil of the pulse transformer 14 in addition to the negative voltage-Va. In other words, similarly in the pulse signal output circuit 10, the primary side voltage becomes a negative voltage having an absolute value of Vs + Va, which is larger than the absolute value of the voltage-Vs by Va. Therefore, the primary-side current i1 flowing in the negative direction in the pulse signal output circuit 50 is higher than the primary-side current i1 flowing in the positive direction in the pulse signal output circuit 50 before the connection of the output terminal of the buffer 51 is switched to the reference terminal by the switching timing controller 13.

After that, even in the pulse signal output circuit 50, similarly in the pulse signal output circuit 10, the voltage value of the primary side voltage V1 rises due to oscillation based on series resonance. At this time, the secondary side circuit of the pulse signal output circuit 20 operates similarly to the secondary side circuit of the pulse signal output circuit 10. Therefore, even in the pulse signal output circuit 50, similarly to in the pulse signal output circuit 10, the electric charge stored in the secondary side capacitor 16 is discharged through the structure of the secondary side capacitor 16 and the secondary side resistor 17, whereby the FET18 is held in the ON state, and the pulse signal to be output is held at the low level.

As described above, in the pulse signal output circuit 50, the buffer 51 outputs the voltage Vs or the reference voltage supplied from the DC power supply PS connected to the input terminal to the output terminal in accordance with the control signal CS input from the switching timing controller 13. Therefore, even in the pulse signal output circuit 50, similarly to the pulse signal output circuit 10 having the switch section 11, the direction in which the primary side current i1 acts on the primary coil of the pulse transformer 14 is switched. As described above, when the primary-side voltage V1 has a voltage value of opposite polarity whose absolute value is Va, the connection of the output terminal of the buffer 51 is switched to the reference terminal. Therefore, even in the pulse signal output circuit 50, similarly to in the pulse signal output circuit 10, when the connection of the output terminal of the buffer 51 is switched to the reference terminal, the primary side voltage V1 changes to a voltage value of the opposite polarity, the absolute value of which is larger than the absolute value of the voltage of the opposite polarity according to the supplied current by Va. Therefore, even in the pulse signal output circuit 50, similarly to in the pulse signal output circuit 10, the secondary-side voltage V2 induced in the secondary coil of the pulse transformer 14 is higher. Therefore, even in the pulse signal output circuit 50, similarly to in the pulse signal output circuit 10, the power transmission efficiency from the primary coil to the secondary coil of the pulse transformer 14 can be improved, and a high driving voltage to the gate terminal of the FET18 can be obtained. Therefore, even in the pulse signal output circuit 50, the same effect as that of the pulse signal output circuit 10 can be achieved.

Also, in the pulse signal output circuit 50, at a time T51 when the time measured by the switching timing controller 13 reaches a preset time (switching time T), the connection of the output terminal of the buffer 51 is switched to the reference terminal by the control signal CS, whereby the DC power supply PS is disconnected from the buffer 51. Therefore, in the pulse signal output circuit 50, the primary-side current i1 flows in the primary-side circuit in the negative direction regardless of the DC power supply PS in the period in which the output terminal of the buffer 51 is connected to the reference terminal. Therefore, in the pulse signal output circuit 50, in the period in which the primary side current i1 flows in the negative direction in the primary side circuit, the current power consumption of the DC power supply PS can be reduced. In other words, in the pulse signal output circuit 50, since the output terminal of the buffer 51 is grounded, the load of the DC power supply PS can be reduced in the period in which the primary side current i1 flows in the negative direction in the primary side circuit. Therefore, in the pulse signal output circuit 50, in the case where the DC power supply PS does not stop supplying power (i.e., in the case where the power supply is not depleted or degraded), even if the DC power supply PS connected to the pulse signal output circuit has a small amount of available current, i.e., has a small amount of available power, it is possible to generate a pulse signal and transmit the generated pulse signal to the receiver RE.

In the pulse signal output circuit 50, the buffer 51 replaces the switch 11 included in the primary-side circuit of the pulse signal output circuit 10. Therefore, the number of elements constituting the primary side circuit and the mounting area can be reduced, and the pulse signal output circuit 50 can be realized in a smaller size at a lower cost.

In the above-described modification, examples in which the primary-side resistor 31 is added (first modification), the rectifying section 45 is used instead of the rectifying section 15 (second modification), and the buffer 51 is used instead of the switching section 11 (third modification) are applied to the pulse signal output circuit 10 shown in fig. 1 have been described, respectively. However, none of the changes of the pulse signal output circuit 10 described in the above modification need to be exclusively applied. In other words, two or more kinds of changes corresponding to the above-described modified examples can be simultaneously applied to the pulse signal output circuit 10. In the pulse signal output circuit configured by applying two or more kinds of changes corresponding to the above-described modification simultaneously to the pulse signal output circuit 10, in addition to the effects achieved in the pulse signal output circuit 10, the effects of the modification corresponding to the applied changes can be achieved.

< fourth modification >

Now, an example of a pulse signal output circuit configured by simultaneously applying two or more kinds of changes corresponding to the modified examples to the pulse signal output circuit 10 will be described. Fig. 11 is a structural diagram showing the structure of a pulse signal output circuit according to a fourth embodiment of the present invention. The pulse signal output circuit 60 includes a buffer 51, a primary side resistor 31, a primary side capacitor 12, a switching timing controller 13, a pulse transformer 14, a rectifying section 45, a secondary side capacitor 16, a secondary side resistor 17, and an FET 18. Fig. 11 also shows the DC power supply PS and the receiver RE connected to the pulse signal output circuit 60. In the pulse signal output circuit 60 shown in fig. 11, similar to the direction shown by each of the primary side current i1, the secondary side current i2, and the rectified current i3 in the pulse signal output circuit 10 shown in fig. 1, the direction shown by each of the primary side current i1, the secondary side current i2, and the rectified current i3 is a forward direction.

The pulse signal output circuit 60 has the same structure as that of the pulse signal output circuit 10 shown in fig. 1 except that it has a buffer 51 and a rectifying portion 45 instead of the switching portion 11 and the rectifying portion 15, respectively, and includes a primary side resistor 31. In other words, the pulse signal output circuit 60 is configured by simultaneously adopting: the primary side resistor 31 described in the first modification is added, the rectifying portion 15 is replaced with the rectifying portion 45 described in the second modification, and the switching portion 11 is replaced with the snubber 51 described in the third modification. Other elements of the pulse signal output circuit 60 are the same as those of the pulse signal output circuit 10 of the first embodiment shown in fig. 1. Therefore, in the following description, among the elements of the pulse signal output circuit 60, the same elements as those of the pulse signal output circuit 10 of the first embodiment are denoted by the same reference numerals, and detailed description thereof will not be given.

similarly to the pulse signal output circuit 10 to the pulse signal output circuit 50, the pulse signal output circuit 60 also switches the flow direction of the primary side current i1 in the primary coil of the pulse transformer 14 when the oscillating waveform of the primary side voltage V1 has a voltage value of opposite polarity, thereby generating a pulse signal, and outputs the generated pulse signal to the receiver RE. Similar to pulse signal output circuit 10 to pulse signal output circuit 50, pulse signal output circuit 60 can also be applied to a field device, for example.

In the pulse signal output circuit 60, in the primary side circuit, the power supply terminal of the buffer 51 is connected to the positive terminal of the DC power supply PS. In the primary-side circuit of the pulse signal output circuit 60, the buffer 51 has an input terminal to which the control signal CS is input from the switch unit 11. Also, in the primary side circuit of the pulse signal output circuit 60, the output terminal of the buffer 51 is connected to the first terminal of the primary side resistor 31, and the second terminal of the primary side resistor 31 is connected to the first terminal a1 of the primary coil of the pulse transformer 14. Further, in the primary side circuit of the pulse signal output circuit 60, a reference voltage is applied to the reference terminal of the buffer 51, which is connected to the second terminal of the primary side capacitor 12. Other connections of the primary side circuit of the pulse signal output circuit 60 (i.e., other connections of the elements constituting the primary side circuit of the pulse signal output circuit 60) are the same as those of the elements of the primary side circuit of the pulse signal output circuit 10.

also, in the secondary side circuit of the pulse signal output circuit 60, the first terminal a2 of the secondary coil of the pulse transformer 14 is connected to the first input terminal of the rectifying section 45, and the second terminal B2 of the secondary coil of the pulse transformer 14 is connected to the second input terminal of the rectifying section 45. In the secondary side circuit of the pulse signal output circuit 60, the first output terminal of the rectifying unit 45 is connected to the first terminal of the secondary side capacitor 16, the first terminal of the secondary side resistor 17, and the gate terminal of the FET 18. Further, in the secondary side circuit of the pulse signal output circuit 60, the second output terminal of the rectifying section 45 is connected to the second terminal of the secondary side capacitor 16, the second terminal of the secondary side resistance 17, and the source terminal (and back gate terminal) of the FET18, and this connection point serves as the second output terminal O2 of the pulse signal output circuit 60. The other connections in the secondary side circuit of the pulse signal output circuit 60 (i.e., the other connections of the elements constituting the primary side circuit of the pulse signal output circuit 60) are the same as those of the elements of the secondary side circuit of the pulse signal output circuit 10.

The overall operation of the pulse signal output circuit 60 and the operation of switching the acting direction of the primary side current on the primary coil of the pulse transformer 14 in the primary side circuit can be easily derived from the operation of the pulse signal output circuit 10 of the first embodiment and the pulse signal output circuits 30 of the first modification to the pulse signal output circuit 50 of the third modification. Therefore, the overall operation of the pulse signal output circuit 60 and the operation of switching the direction of action of the primary side current on the primary coil of the pulse transformer 14 in the primary side circuit will not be specifically described.

in the pulse signal output circuit 60, in addition to the effects achieved in the pulse signal output circuit 10 of the first embodiment, the effects of the above-described modified example corresponding to the applied change can be achieved. More specifically, in the pulse signal output circuit 60, since the primary side resistance 31 is added corresponding to the first modification, the oscillation based on the series resonance of the primary coil of the pulse transformer 14 and the primary side capacitor 12, which acts on the primary side voltage V1 and the primary side current i1 of the primary coil of the pulse transformer 14, can be easily and quickly converged, whereby the additional current power consumption of the primary side circuit can be reduced. In the pulse signal output circuit 60, since the rectifying unit 15 is replaced with the rectifying unit 45 according to the second modification, the number of elements constituting the secondary side circuit can be reduced by one due to the reduction in the number of diodes D. Further, in the pulse signal output circuit 60, since the buffer 51 corresponding to the third modification is used in place of the switch section 11, it is possible to reduce the current power consumption of the DC power supply PS in a period in which the primary side current i1 flows in the negative direction in the primary side circuit.

According to this structure, in the pulse signal output circuit 60, similarly to in the pulse signal output circuit 10, when the oscillation waveform of the primary side voltage V1 has the opposite polarity, the acting direction of the primary side current to the primary coil of the pulse transformer 14 is switched. Therefore, the power transmission efficiency from the primary coil to the secondary coil of the pulse transformer 14 can be improved, and a high driving voltage to the gate terminal of the FET18 can be achieved. Moreover, in the pulse signal output circuit 60, due to the changes of the pulse signal output circuit 30 corresponding to the first modification to the pulse signal output circuit 50 corresponding to the third modification, the pulse signal output circuit 60 can be realized in a smaller size at a lower cost to reduce power consumption.

In the first to fourth modifications described above, an example in which elements of at least one of the primary side circuit and the secondary side circuit of the pulse signal output circuit 10 shown in fig. 1 are changed has been described. However, the changes of the elements as described in the above modification are not limited to being applied to the pulse signal output circuit 10 having the structure including the switching timing controller 13. In other words, the changes of the elements as described in the above modification can also be applied to the pulse signal output circuit 20 having the switching timing controller 23 instead of the switching timing controller 13. In the pulse signal output circuit configured by applying the change of the element described in the above-described modification to the pulse signal output circuit 20, the effect of the modification corresponding to the applied change can be achieved in addition to the effect achieved in the pulse signal output circuit 20.

As described above, according to the embodiment and the modified examples of the embodiment of the present invention, the pulse signal output circuit includes the switching timing controller. Further, in the embodiment and the modification of the embodiment of the invention, the switching timing controller switches the acting direction of the primary side current to the primary coil of the pulse transformer included in the pulse signal output circuit when the oscillating waveform of the voltage of the primary side circuit has the opposite polarity. Therefore, in the embodiments and the modifications of the embodiments of the present invention, it is possible to improve the power transmission efficiency from the primary coil to the secondary coil of the pulse transformer included in the primary side circuit, and to realize a high driving voltage to the gate terminal of the FET provided in the secondary side circuit to turn on and off the FET in accordance with the voltage acting on the gate terminal, thereby generating and outputting the pulse signal.

Further, in the embodiment and the modification of the embodiment of the invention, the switching timing controller switches the direction of action of the primary side current on the primary coil of the pulse transformer included in the pulse signal output circuit at the timing when the oscillating waveform of the voltage of the primary side circuit has the peak value of the opposite polarity. In this way, in the embodiment and the modification of the embodiment of the invention, when the voltage of the primary side has a voltage value of an opposite polarity, it is possible to switch the direction of action of the primary side current of the pulse transformer so that the voltage of the primary side circuit becomes a voltage value of an opposite polarity whose absolute value is larger than the absolute value of the voltage value of an opposite polarity according to the supplied current by the absolute value of the voltage value of an opposite polarity just before the switching. Therefore, in the embodiments and the modifications of the embodiments of the present invention, the power transmission efficiency from the primary coil to the secondary coil of the pulse transformer included in the pulse signal output circuit can be further improved, and a high driving voltage to the gate terminal of the FET provided in the secondary side circuit and configured to generate and output the pulse signal can be realized.

In each pulse signal output circuit, the power transmission efficiency to the secondary side of the pulse transformer is affected by a drive voltage or the like applied to the gate terminal of the FET for generating the pulse signal in the pulse signal output circuit. Therefore, the power transmission efficiency depends on the selection of elements of the secondary side circuit of the pulse transformer. According to the pulse signal output circuit of the embodiment and the modification of the embodiment of the invention, as described above, the power transmission efficiency from the primary side to the secondary side of the pulse transformer can be improved, thereby increasing the energy available in the secondary side circuit of the pulse transformer, and therefore, a high driving voltage to the gate terminal of the FET can be realized. Therefore, according to the pulse signal output circuit of the embodiment and the modification of the embodiment of the invention, for example, the restrictions of the threshold voltage of the gate terminal of the FET and the forward voltage of each diode can be alleviated, and the elements of the secondary side circuit of the pulse transformer can be easily selected. Further, according to the pulse signal output circuit of the embodiment and the modified example of the embodiment of the invention, as described above, when the voltage of the primary side circuit has the voltage value of the opposite polarity, the acting direction of the primary side current of the pulse transformer may be switched so that the voltage of the primary side circuit becomes the voltage value of the opposite polarity, the absolute value of which is larger than the absolute value of the voltage value of the opposite polarity according to the supplied current by the absolute value of the voltage value of the opposite polarity just before the switching. In other words, according to the pulse signal output circuit of the embodiment and the modification of the embodiment of the invention, since the switching timing controller controls the timing of switching the acting direction of the current in the primary coil of the pulse transformer included in the pulse signal output circuit, it is possible to prevent a voltage value from being lowered due to oscillation (so-called ringing) based on the inductance component of the primary side of the pulse transformer and the series resonance of the primary side capacitor. Therefore, according to the pulse signal output circuit of the embodiment and the modified example of the embodiment of the invention, it is possible to easily select elements necessary for configuring the secondary side circuit of the pulse transformer without being subject to some restrictions of element selection, for example, a restriction that the rectifying section should be provided with an FET having a low gate terminal threshold voltage and a diode having a low forward voltage, or the like.

In the embodiments and the modifications of the embodiments of the present invention, the field device has been regarded as an example of a device to which each pulse signal output circuit can be practically applied. However, the device to which each pulse signal output circuit can be practically applied is not limited to the field device. In other words, the pulse signal output circuit of the embodiment and the modification of the embodiment of the present invention can also be used for any device that performs processing using a pulse signal output from the pulse signal output circuit.

Also, in the embodiment and the modification of the embodiment of the present invention, the FET18 is configured to generate a pulse signal. However, any other element for generating a pulse signal may be used instead of the FET 18. For example, a bipolar transistor may be used as an element for generating a pulse signal. In this case, in the pulse signal output circuits of the embodiment and the modified example of the embodiment of the present invention, the terminals of the bipolar transistors are connected instead of the terminals of the FETs corresponding to the terminals of the bipolar transistors, respectively, so that the FETs 18 can be easily replaced with the bipolar transistors. More specifically, in the pulse signal output circuits of the embodiment and the modified example of the embodiment of the invention, the FET18 can be easily replaced with a bipolar transistor by connecting the base terminal of the bipolar transistor, the emitter terminal of the bipolar transistor, and the collector terminal of the bipolar transistor in place of the gate terminal of the FET18, the source terminal of the FET18, and the drain terminal of the FET18, respectively.

Although the embodiments of the present invention have been described above, the specific structure is not limited to these embodiments, and various modifications are also included in the scope of the present invention.