阅读说明：本技术 多snn芯片互联的相对寻址方法、装置、设备和介质 (Relative addressing method, device, equipment and medium for interconnection of multiple SNN chips ) 是由 陈克林 张华秋 吕正祥 杨力邝 袁抗 陈旭 朱文俊 梁龙飞 于 2021-07-23 设计创作，主要内容包括：本申请提供的一种多SNN芯片互联的相对寻址方法、装置、设备和介质,通过判断源芯片到目标芯片的寻址信息是否超出预设范围；若未超出预设范围,则发送一包含寻址信息低位部分的数据包；若超出预设范围,则发送两次数据包。本申请在片内数据包的基础上加上2*M比特实现片间寻址,大大降低了开销,并且每片芯片不需要知道自己的绝对坐标,不需要通过额外的编程告知芯片坐标信息。(According to the relative addressing method, device, equipment and medium for interconnection of the multiple SNN chips, whether addressing information from a source chip to a target chip exceeds a preset range is judged; if the address information does not exceed the preset range, sending a data packet containing the lower part of the addressing information; and if the data packet exceeds the preset range, transmitting the data packet twice. According to the method, 2M bits are added on the basis of the data packet in the chip to realize addressing between the chips, so that the overhead is greatly reduced, each chip does not need to know the absolute coordinate of the chip, and the coordinate information of the chip does not need to be informed through extra programming.)

1. A method for relative addressing of interconnection of multiple SNN chips, the method comprising:

judging whether the addressing information from the source chip to the target chip exceeds a preset range or not;

if the address information does not exceed the preset range, sending a data packet containing the lower part of the addressing information; and if the data packet exceeds the preset range, transmitting the data packet twice.

2. The method of claim 1, wherein the predetermined range is 2 sides according to the current coordinates of the source chip^M-1 square; wherein M is a predetermined value, 1<＝M<＝10。

3. The method of claim 1 or 2, wherein the determining whether the addressing information from the source chip to the target chip exceeds a preset range comprises:

when-2^(M-1)<＝X<＝2^(M-1)-1 and-2^(M-1)<＝Y<＝2^(M-1)When the address information is within the preset range, judging that the address information is not beyond the preset range;

when X is present<-2^(M-1)Or X>2^(M-1)-1 or Y<-2^(M-1)Or Y>2^(M-1)When the address information is within the preset range, judging that the address information is beyond the preset range;

wherein M is a preset value; x and Y are relative coordinates of addressing information, respectively.

4. The method of claim 3, wherein if the predetermined range is not exceeded, sending a packet containing a lower portion of addressing information:

addressing information in the data packet is (X [ M-1:0], Y [ M-1:0 ]); wherein the addressing information is represented by the lower 2 x M bit width of the complete addressing information.

5. The method of claim 1, wherein sending the data packet twice if the predetermined range is exceeded comprises:

the first time data is sent, wherein the first time data contains complete addressing information, and the control information in the data packet indicates that the data packet is not finished;

the second data sent contains valid data to be transmitted and the control information in the data packet indicates the end of the data packet.

6. The method of claim 3, further comprising:

after the chip receives the data packet from the port, the chip adds 1 or subtracts 1 to X or Y in the addressing information, and judges whether the sum of the positive and negative of X and Y in the addressing information after the 1 adding or subtracting operation is 0, so as to determine which port of the chip the data packet is sent out from.

7. The method of claim 6, further comprising:

and when X and Y in the addressing information after the 1 adding or 1 subtracting operation are both 0, determining that the chip is the target chip, and consuming the data packet by the chip.

8. An apparatus for relative addressing of interconnection of multiple SNN chips, the apparatus comprising:

the judging module is used for judging whether the addressing information from the source chip to the target chip exceeds a preset range;

the processing module is used for sending a data packet containing the lower part of the addressing information if the data packet does not exceed the preset range; and if the data packet exceeds the preset range, transmitting the data packet twice.

9. A computer device, the device comprising: a memory, and a processor; the memory is to store computer instructions; the processor executes computer instructions to implement the method of any one of claims 1 to 7.

10. A computer-readable storage medium having stored thereon computer instructions which, when executed, perform the method of any one of claims 1 to 7.

Technical Field

The invention relates to the technical field of inter-chip addressing, in particular to a relative addressing method, a relative addressing device, relative addressing equipment and relative addressing medium for interconnection of multiple SNN chips.

Background

Deep Neural Network (DNN) research has gained rapid development and initial application in recent years. However, implementing such algorithms typically requires a significant amount of computational effort. AlexNet, which is a classical deep convolutional network (CNN) model, requires at least 7.2 hundred million multiplications. The large amount of computation results in large power consumption, typically around 10 to 100 watts.

On the other hand, the impulse neural network (SNN) has attracted attention in academia and industry in recent years with its low power consumption and closer proximity to the human brain. In a spiking neural network, an axon is a unit that receives a pulse, a neuron is a unit that transmits a pulse, one neuron is connected to a plurality of axons through a dendrite, and the connection point of the dendrite and the axon is called a synapse. After the axon receives the pulse, all dendrites synapse with the axon receive the pulse, and then the neuron downstream of the dendrite is affected. The neuron accumulates pulses from multiple axons and sends a pulse downstream if the value exceeds a threshold. 1-bit pulse is transmitted in the pulse neural network, the activation frequency of the pulse is low, and only addition and subtraction operation is needed without multiplication operation. Compared with a neural network based on deep learning, the impulse neural network has lower power consumption.

The number of neurons in the human brain is greater than 800 hundred million, assuming that 8 thousands of neurons are implemented per SNN chip, 100 thousands of SNN chips are required to implement simulation of the human brain. The chip identification of each chip needs to be at least 20 bits wide to represent.

The bit width of a data packet communicated inside the single chip is assumed to be N bits, and the data packet comprises an on-chip address, a control signal, data and the like. In order to realize interconnection between chips, N bits need to be expanded to N +20 bits. When N is 60, the inter-chip addressing overhead is 20/60-33%. This will increase the chip area, the pin count of the chip and the power consumption of the chip.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, it is an object of the present application to provide a relative addressing method, apparatus, device and medium for interconnection of multiple SNN chips to solve the problems in the prior art.

To achieve the above and other related objects, the present application provides a relative addressing method for interconnection of multiple SNN chips, the method comprising: judging whether the addressing information from the source chip to the target chip exceeds a preset range or not; if the address information does not exceed the preset range, sending a data packet containing the lower part of the addressing information; and if the data packet exceeds the preset range, transmitting the data packet twice.

In an embodiment of the present application, the predetermined range is a side length of 2 according to the current coordinate of the source chip^M-1 square; wherein M is a predetermined value, 1<＝M<＝10。

In an embodiment of the present application, the determining whether the addressing information from the source chip to the target chip exceeds a preset range includes: when-2^(M-1)<＝X<＝2^(M-1)-1 and-2^(M-1)<＝Y<＝2^(M-1)When the address information is within the preset range, judging that the address information is not beyond the preset range; when X is present<-2^(M-1)Or X>2^(M-1)-1 or Y<-2^(M-1)Or Y>2^(M-1)When the address information is within the preset range, judging that the address information is beyond the preset range; wherein M is a preset value; x and Y are relative coordinates of addressing information, respectively.

In an embodiment of the present application, if the predetermined range is not exceeded, a data packet including a lower portion of the addressing information is sent: addressing information in the data packet is (X [ M-1:0], Y [ M-1:0 ]); wherein the addressing information is represented by a low 2 x M bit width.

In an embodiment of the present application, if the predetermined range is exceeded, the sending the data packet twice includes: the first time data is sent, wherein the first time data contains complete addressing information, and the control information in the data packet indicates that the data packet is not finished; the second data sent contains valid data to be transmitted and the control information in the data packet indicates the end of the data packet.

In an embodiment of the present application, the method further includes: after the chip receives the data packet from the port, the chip adds 1 or subtracts 1 to X or Y in the addressing information, and judges whether X and Y in the addressing information after adding 1 or subtracting 1 are 0 and positive or negative thereof, so as to determine which direction port the data packet is sent from the chip.

In an embodiment of the present application, the method further includes: and when X and Y in the addressing information after the 1 adding or 1 subtracting operation are both 0, determining that the chip is the target chip, and consuming the data packet by the chip.

To achieve the above and other related objects, the present application provides a relative addressing apparatus for interconnection of multiple SNN chips, the apparatus comprising: the judging module is used for judging whether the addressing information from the source chip to the target chip exceeds a preset range; the processing module is used for sending a data packet containing the lower part of the addressing information if the data packet does not exceed the preset range; and if the data packet exceeds the preset range, transmitting the data packet twice.

To achieve the above and other related objects, the present application provides a computer apparatus, comprising: a memory, and a processor; the memory is to store computer instructions; the processor executes computer instructions to implement the method as described above.

To achieve the above and other related objects, the present application provides a computer readable storage medium storing computer instructions which, when executed, perform the method as described above.

In summary, the method, the device, the equipment and the medium for relative addressing of interconnection of multiple SNN chips in the present application determine whether addressing information from a source chip to a target chip exceeds a preset range; if the address information does not exceed the preset range, sending a data packet containing the lower part of the addressing information; and if the data packet exceeds the preset range, transmitting the data packet twice.

Has the following beneficial effects:

according to the method, 2M bits are added on the basis of the data packet in the chip to realize addressing between the chips, so that the overhead is greatly reduced, each chip does not need to know the absolute coordinate of the chip, and the coordinate information of the chip does not need to be informed through extra programming.

Drawings

Fig. 1 is a schematic diagram of an array of 6X6 multiple SNN chips according to an embodiment of the present invention.

Fig. 2 is a schematic flow chart illustrating a relative addressing method for interconnection of multiple SNN chips according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating a scenario of a target chip corresponding to a predetermined range according to an embodiment of the present application.

Fig. 4 is a block diagram of a relative addressing device for interconnection of multiple SNN chips according to an embodiment of the present invention.

Fig. 5 is a schematic structural diagram of a computer device according to an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application is provided by way of specific examples, and other advantages and effects of the present application will be readily apparent to those skilled in the art from the disclosure herein. The present application is capable of other and different embodiments and its several details are capable of modifications and/or changes in various respects, all without departing from the spirit of the present application. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.

It should be noted that the drawings provided in the following embodiments are only schematic and illustrate the basic idea of the present application, and although the drawings only show the components related to the present application and are not drawn according to the number, shape and size of the components in actual implementation, the type, quantity and proportion of the components in actual implementation may be changed at will, and the layout of the components may be more complex.

Throughout the specification, when a part is referred to as being "connected" to another part, this includes not only a case of being "directly connected" but also a case of being "indirectly connected" with another element interposed therebetween. In addition, when a certain part is referred to as "including" a certain component, unless otherwise stated, other components are not excluded, but it means that other components may be included.

The terms first, second, third, etc. are used herein to describe various elements, components, regions, layers and/or sections, but are not limited thereto. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the scope of the present application.

Also, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," and/or "comprising," when used in this specification, specify the presence of stated features, operations, elements, components, items, species, and/or groups, but do not preclude the presence, or addition of one or more other features, operations, elements, components, items, species, and/or groups thereof. The terms "or" and/or "as used herein are to be construed as inclusive or meaning any one or any combination. Thus, "A, B or C" or "A, B and/or C" means "any of the following: a; b; c; a and B; a and C; b and C; A. b and C ". An exception to this definition will occur only when a combination of elements, functions or operations are inherently mutually exclusive in some way.

The relative addressing method of multi-SNN chip interconnection is used for a pulse neural network (SNN). In a Spiking Neural Network (SNN), an axon is a unit that receives a pulse, a neuron is a unit that transmits a pulse, one neuron is connected to a plurality of axons through a dendrite, and a connection point of the dendrite and the axon is called a synapse. After the axon receives the pulse, all dendrites synapse with the axon receive the pulse, and then the neuron downstream of the dendrite is affected. The downstream neuron accumulates pulses from multiple axons and sends a pulse downstream if the value exceeds a threshold. 1-bit pulse is transmitted in the pulse neural network, the activation frequency of the pulse is low, and only addition and subtraction operation is needed without multiplication operation. Compared with a neural network based on deep learning, the impulse neural network has lower power consumption.

As shown in fig. 1, a schematic of an array of multiple SNN chips is shown as 6X 6. The chip identification of each chip is the coordinates of the chip, which is indicated by (Y, X). A unit in one source chip (Ysource, Xsource) sends a data packet to a unit in the other chip (Ydest, Xdest), and the data packet needs to carry an identifier (Ydest, Xdest) of a target chip. To support emulation of the neuron size in the brain, (typically Ydest, Xdest) is wider than 20 bits, such as may be 32 bits wide.

The application finds that the data transmission inside each chip is the most, the data packet transmission to the nearby chip is the second time, and the data packet transmission to the farther chip is the least. Based on this finding, through reasonable neuron mapping, communication between far chips can be reduced, thereby reducing power consumption of communication. Therefore, the application provides a relative addressing method for interconnection of multiple SNN chips, so as to solve the problem of high addressing overhead among the chips.

Fig. 2 is a schematic flow chart of a relative addressing method for interconnection of multiple SNN chips according to an embodiment of the present application. As shown, the method comprises:

step S201: judging whether the addressing information from the source chip to the target chip exceeds a preset range or not;

the addressing information carried in the transmitted data packet is (Ydest-source, Xdest-Xsource), that is, the identifier of the target chip is subtracted from the representation of the source chip.

In an embodiment of the present application, the predetermined range is a side length of 2 according to the current coordinate of the source chip^M1 square.

Specifically, when-2^(M-1)<＝X<＝2^(M-1)-1 and-2^(M-1)<＝Y<＝2^(M-1)When the address information is within the preset range, judging that the address information is not beyond the preset range; when X is present<-2^(M-1)Or X>2^(M-1)-1 or Y<-2^(M-1)Or Y>2^(M-1)When-1, then judgeAnd determining that the addressing information exceeds a preset range.

For example, as shown in fig. 3, assuming that the source chip (source, Xsource) is currently represented by (0,0), and assuming that M is 2, the side length of a square formed by the current coordinates of the source chip is equal to 2²-1-3, the square enclosing a range, X or Y being minimum to-2, maximum to 1.

It should be noted that the squares formed in this application are normally of equal length at both ends of the range, i.e. X>＝-2^(M-1)Should also have X<＝2^(M-1)Just right, but in the present application does X<＝2^(M-1)-1. This is done because the two's complement has this problem because the sign bit of 0 is 0 and the sign bit of a positive number is also 0, so the positive number representation range is 1 less than the negative number representation range.

In the present application, M is a predetermined value, 1 ═ M ═ 10. For example, Ydiff, Xdiff may be 32 bits wide, and the predetermined value M is determined at the chip design stage.

Step S202: if the address information does not exceed the preset range, sending a data packet containing the lower part of the addressing information; and if the data packet exceeds the preset range, transmitting the data packet twice.

In an embodiment of the present application, the determining whether the addressing information from the source chip to the target chip exceeds a preset range includes:

A. when-2^(M-1)<＝X<＝2^(M-1)-1 and-2^(M-1)<＝Y<＝2^(M-1)And 1, if the addressing information is judged not to exceed the preset range, sending a data packet containing the lower part of the addressing information.

Addressing information in the data packet is (X [ M-1:0], Y [ M-1:0 ]); wherein the addressing information is represented by a low 2 x M bit width. It should be noted that the upper part of the complete addressing information is not carried in the data packet because it is a sign extension in this case and does not carry meaningful information. Specifically, (X [ M-1:0], Y [ M-1:0]) indicates that, if X [ M-1] ═ 0 or Y [ M-1] ═ 0, all upper parts are sign extended with 0; x [ M-1] ═ 1 or Y [ M-1] ═ 1, then the upper part is all sign extended with 1.

B. When X is present<-2^(M-1)Or X>2^(M-1)-1 or Y<-2^(M-1)Or Y>2^(M-1)And 1, if the addressing information is judged to be beyond the preset range, transmitting the data packet twice.

Wherein, the first data sent contains complete addressing information, and the control information in the data packet indicates that the data packet is not finished; the second data sent contains valid data to be transmitted and the control information in the data packet indicates the end of the data packet.

For example, assuming that M is 2, the chip (1,2) in fig. 1 sends data to the chip (2,0), and since (Ydiff, Xdiff) ═ 1, -2< ═ Ydiff < (1), and-2 < ═ Xdiff < (1), only one piece of data needs to be sent, the addressing information contained in the packet is signed (1, -2), and it can be represented by 2 data bits with 2 bit width. If the chip (1,2) in fig. 1 sends data to the chip (2,4), since (Ydiff, Xdiff) ═ 1,2, Xdiff ═ 2>1, two data streams need to be sent, the first data stream contains 20 bits of complete addressing information (Ydiff, Xdiff), and the second data stream contains valid data that needs to be transferred.

It should be noted that, assuming that M is 2, the bit width of a data packet communicated inside a chip is N60, and the addressing overhead between chips is 4/60 6.7%, the overhead is greatly reduced; when the two chips are far away from each other, an extra data packet containing the addressing information of the whole chip needs to be sent. This reduces the effective data bandwidth between the slices. Since this is very rare, the impact of the effective bandwidth reduction is very small.

In an embodiment of the present application, the relative addressing routing includes: after the chip receives the data packet from the port, the chip adds 1 or subtracts 1 to X or Y in the addressing information, and judges whether X and Y in the addressing information after adding 1 or subtracting 1 are 0 and positive or negative thereof, so as to determine which direction port the data packet is sent from the source chip. And when X and Y in the addressing information after the operation of adding 1 or subtracting 1 are both 0, determining that the chip is the target chip, and consuming the data packet by the chip.

It should be noted that, here, adding 1 or subtracting 1 to X or Y in the addressing information is operated according to which port of the four ports of east, south, west and north of the chip the data packet enters.

For example, if a packet enters from the north port (or above) of the chip, the yidiff data field of the packet is decremented by 1, as shown in fig. 1 or 3; if the data packet enters from the south port (or the lower part) of the chip, adding 1 to the data field Ydiff of the data packet; if the data packet enters from the west (or left direction) of the chip, subtracting 1 from the Xdiff data field of the data packet; if the packet is coming from the east (or right direction) of the chip, the packet Xdiff data field is incremented by 1.

If the adjusted Xdiff is greater than 0, the data packet is sent out from the east port of the chip, for example, corresponding to FIG. 3, when the chip (0,0) sends the packet to the chip (1,1), the data packet is sent out from the east port of the chip (0, 0); if the adjusted Xdiff is <0, a data packet is sent out from the West of the chip. If the adjusted Xdiff is 0 and Ydiff is 0, the data packet is sent out from the south port of the chip; if the adjusted Xdiff is 0 and Ydiff is less than 0, the data packet is sent out from the north port of the chip; if the adjusted Xdiff is 0 and Ydiff is 0, the chip is the target chip and the packet is consumed by the chip.

If the chip (1,2) in fig. 1 sends a data packet to the chip (1,4), the addressing information of the data packet sent by the source chip is (0, 2). The data packets of the chips (1,2) enter the west ports of the chips (1,3) through the east ports, and the chips (1,3) adjust the addressing information to (0,1) according to the routing rule; then the data packet enters the west port of the chip (1,4) through the east port of the chip (1,3), and the addressing information is adjusted to (0,0) after the data packet enters the chip (1, 4). And finishing the data packet forwarding.

In summary, the inter-chip addressing is realized by adding 2 × M bits (or M bits) on the basis of the in-chip data packet, so that the overhead is greatly reduced, and each chip does not need to know the absolute coordinate of the chip and does not need to inform the coordinate information of the chip through additional programming.

Fig. 4 is a block diagram of a relative addressing device for interconnection of multiple SNN chips according to an embodiment of the present invention. As shown, the apparatus 400 includes:

the determining module 401 is configured to determine whether addressing information from the source chip to the target chip exceeds a preset range;

a processing module 402, configured to send a data packet including a lower portion of the addressing information if the predetermined range is not exceeded; and if the data packet exceeds the preset range, transmitting the data packet twice.

It should be noted that, because the contents of information interaction, execution process, and the like between the modules/units of the apparatus are based on the same concept as the method embodiment described in the present application, the technical effect brought by the contents is the same as the method embodiment of the present application, and specific contents may refer to the description in the foregoing method embodiment of the present application, and are not described herein again.

It should be further noted that the division of the modules of the above apparatus is only a logical division, and the actual implementation may be wholly or partially integrated into one physical entity, or may be physically separated. And these units can be implemented entirely in software, invoked by a processing element; or may be implemented entirely in hardware; and part of the modules can be realized in the form of calling software by the processing element, and part of the modules can be realized in the form of hardware. For example, the processing module 402 may be a separate processing element, or may be integrated into a chip of the apparatus, or may be stored in a memory of the apparatus in the form of program code, and a processing element of the apparatus calls and executes the functions of the processing module 402. Other modules are implemented similarly. In addition, all or part of the modules can be integrated together or can be independently realized. The processing element described herein may be an integrated circuit having signal processing capabilities. In implementation, each step of the above method or each module above may be implemented by an integrated logic circuit of hardware in a processor element or an instruction in the form of software.

For example, the above modules may be one or more integrated circuits configured to implement the above methods, such as: one or more Application Specific Integrated Circuits (ASICs), or one or more microprocessors (DSPs), or one or more Field Programmable Gate Arrays (FPGAs), among others. For another example, when one of the above modules is implemented in the form of a Processing element scheduler code, the Processing element may be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).

Fig. 5 is a schematic structural diagram of a computer device according to an embodiment of the present application. As shown, the computer device 500 includes: a memory 501 and a processor 502; the memory 501 is used for storing computer instructions; the processor 502 executes computer instructions to implement the method described in fig. 2.

In some embodiments, the number of the memory 501 in the computer device 500 may be one or more, the number of the processor 502 may be one or more, and fig. 5 is taken as an example.

In an embodiment of the present application, the processor 502 in the computer device 500 loads one or more instructions corresponding to the processes of the application program into the memory 501 according to the steps described in fig. 2, and the processor 502 executes the application program stored in the memory 502, thereby implementing the method described in fig. 2.

The memory 501 may include a Random Access Memory (RAM), or may also include a non-volatile memory (non-volatile memory), such as at least one disk memory. The memory 501 stores an operating system and operating instructions, executable modules or data structures, or a subset thereof, or an expanded set thereof, wherein the operating instructions may include various operating instructions for implementing various operations. The operating system may include various system programs for implementing various basic services and for handling hardware-based tasks.

The Processor 502 may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; the Integrated Circuit may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, a discrete Gate or transistor logic device, or a discrete hardware component.

In some specific applications, the various components of the computer device 500 are coupled together by a bus system that may include a power bus, a control bus, a status signal bus, etc., in addition to a data bus. But for clarity of explanation the various busses are shown in fig. 5 as a bus system.

In an embodiment of the present application, a computer-readable storage medium is provided, on which a computer program is stored, which when executed by a processor implements the method described in fig. 2.

The present application may be embodied as systems, methods, and/or computer program products, in any combination of technical details. The computer program product may include a computer-readable storage medium having computer-readable program instructions embodied thereon for causing a processor to implement various aspects of the present application.

The computer readable storage medium may be a tangible device that can hold and store the instructions for use by the instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic memory device, a magnetic memory device, an optical memory device, an electromagnetic memory device, a semiconductor memory device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a Static Random Access Memory (SRAM), a portable compact disc read-only memory (CD-ROM), a Digital Versatile Disc (DVD), a memory stick, a floppy disk, a mechanical coding device, such as punch cards or in-groove projection structures having instructions stored thereon, and any suitable combination of the foregoing. Computer-readable storage media as used herein is not to be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., optical pulses through a fiber optic cable), or electrical signals transmitted through electrical wires.

The computer-readable programs described herein may be downloaded from a computer-readable storage medium to a variety of computing/processing devices, or to an external computer or external storage device via a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. The network adapter card or network interface in each computing/processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in the respective computing/processing device. The computer program instructions for carrying out operations of the present application may be assembly instructions, Instruction Set Architecture (ISA) instructions, machine related instructions, microcode, firmware instructions, state setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C + + or the like and procedural programming languages, such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, the electronic circuitry can execute computer-readable program instructions to implement aspects of the present application by utilizing state information of the computer-readable program instructions to personalize the electronic circuitry, such as a programmable logic circuit, a Field Programmable Gate Array (FPGA), or a Programmable Logic Array (PLA). .

In summary, the method, the device, the equipment and the medium for relative addressing of interconnection of multiple SNN chips provided by the present application determine whether addressing information from a source chip to a target chip exceeds a preset range; if the address information does not exceed the preset range, sending a data packet containing the addressing information; and if the data packet exceeds the preset range, transmitting the data packet twice. The application effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles and utilities of the present application and are not intended to limit the invention. Any person skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present application. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present application.