阅读说明：本技术 一种自密封的微纳流控芯片加工方法 (Self-sealing micro-nano fluidic chip processing method ) 是由 张琬皎 于 2019-08-27 设计创作，主要内容包括：本发明公开了一种自密封的微纳流控芯片加工方法。在玻璃或硅晶圆的基板上用纳米压印的方法制作由压印胶组成的微纳流道及其上的残余层,微纳流道上还包含有残余层；用反应离子刻蚀的方法去掉压印胶的残余层；用原子层沉积的方法,在基板和微纳流道上沉积一层二氧化硅SiO<Sub>2</Sub>或二氧化钛TiO<Sub>2</Sub>的沉积层；在微纳流道的两端部打孔分别作为液体试样的进口和出口；将基板放入高温加热炉中加热,使压印胶气化挥发,待压印胶完全挥发,将基板拿出获得芯片。本发明使得二氧化硅或二氧化钛与玻璃或硅基底紧密的结合在一起,实现极好的密封性,可以实现微米级、甚至纳米级高精度结构的加工,可以避免玻璃的高温变形及结构坍塌现象。(the invention discloses a method for processing a self-sealing micro-nano fluidic chip. Manufacturing a micro-nano flow channel consisting of imprinting glue and a residual layer on the micro-nano flow channel by using a nano imprinting method on a substrate of a glass or silicon wafer, wherein the micro-nano flow channel also comprises the residual layer; removing the residual layer of the imprinting glue by a reactive ion etching method; depositing a layer of silicon dioxide SiO on the substrate and the micro-nano flow channel by using an atomic layer deposition method 2 Or titanium oxide TiO 2 The deposited layer of (a); punching holes at two end parts of the micro-nano flow channel to be respectively used as an inlet and an outlet of a liquid sample; and (3) putting the substrate into a high-temperature heating furnace for heating, so that the imprinting glue is gasified and volatilized, and taking out the substrate to obtain the chip after the imprinting glue is completely volatilized. The invention leads the silicon dioxide or titanium dioxide and the glass or silicon substrate to be tightly combined together, realizes excellent sealing property, can realize the processing of micron-level or even nanometer-level high-precision structures, and can avoid the phenomena of high-temperature deformation and structure collapse of the glass.)

1. A self-sealing micro-nano fluidic chip processing method is characterized in that:

S1, manufacturing a micro-nano flow channel (2) consisting of stamping glue and a residual layer (3) on the micro-nano flow channel by a nano-stamping method on a substrate (1) of glass or a silicon wafer, wherein the micro-nano flow channel also comprises the residual layer (3);

S2, removing the residual layer (3) of the stamping glue by a Reactive Ion Etching (RIE) method;

S3, depositing a layer of silicon dioxide SiO on the substrate (1) and the micro-nano flow channel (2) by using an Atomic Layer Deposition (ALD) method₂Or titanium oxide TiO₂A deposition layer (4);

S4, punching holes (5) at two end parts of the micro-nano flow channel (2) to be respectively used as an inlet and an outlet of a liquid sample;

s5, putting the substrate (1) into a high-temperature heating furnace for heating, so that the imprinting glue is vaporized and volatilized, and taking out the substrate (1) to obtain the chip after the imprinting glue is completely volatilized.

2. The method for processing the self-sealing micro-nano fluidic chip according to claim 1, wherein the method comprises the following steps: in the step S5, the heating temperature is 300-600 ℃.

3. The method for processing the self-sealing micro-nano fluidic chip according to claim 1, wherein the method comprises the following steps: the nanoimprinting in step S1 is replaced with a photolithography plus development method.

4. The method for processing the self-sealing micro-nano fluidic chip according to claim 1, wherein the method comprises the following steps: the reactive ion etching in the step S2 is replaced by an inductively coupled plasma etching or plasma photoresist removing method.

5. The method for processing the self-sealing micro-nano fluidic chip according to claim 1, wherein the method comprises the following steps: the atomic layer deposition in step S3 is replaced by a method of plasma enhanced chemical vapor deposition.

6. the method for processing the self-sealing micro-nano fluidic chip according to claim 1, wherein the method comprises the following steps: two through holes (6) are formed in the deposition layer (4) through punching (5) at two end parts of the micro-nano flow channel (2), the two through holes (6) are respectively communicated with the two end parts of the micro-nano flow channel (2), and the two through holes (6) are respectively used as a liquid inlet and a liquid outlet of the micro-nano flow channel (2).

Technical Field

The invention relates to the field of micro-nano fluidic chips, in particular to a self-sealing micro-nano fluidic chip processing method.

Background

The micro-nano flow control chip technology integrates basic operations of sample preparation, reaction, separation, detection and the like in the processes of biological, chemical and medical analysis into a chip with a micro-scale or nano-scale flow channel to automatically complete analysis. With the breakthrough progress of material science and micro-nano processing technology in recent years, the micro-nano fluidic chip is rapidly developed and is more and more widely applied. At present, the micro-nanofluidic chip is applied to a plurality of fields such as gene and protein sequencing, disease diagnosis, drug screening and the like, and gradually becomes an important technical basis of system biology, particularly system genetics.

The micro-nanofluidic chip uses a small amount of liquid samples, and the liquid samples must be well sealed inside the chip to complete the whole detection process. Therefore, the degree of sealing (the degree of preventing the liquid sample from volatilizing) becomes an important parameter for evaluating the quality of the microfluidic chip. The common method for manufacturing the sealed micro-nanofluidic chip is to bond the substrate with the micro-nanofluidic channel and the glass cover plate together by a thermal bonding or anodic bonding method. The thermal bonding needs to be completed in a high-temperature environment, not only energy consumption is achieved, but also efficiency is low, and particularly, the surface smoothness of the glass substrate is damaged in the high-temperature pressure bonding process, the microstructure is likely to collapse, and the yield is low. Thermal bonding is less applicable to chips containing temperature sensitive agents, electrodes and waveguides.

Anodic bonding is also called electrostatic bonding, has higher requirements on glass materials, and is not suitable for wide popularization. The invention adopts a brand new method to manufacture the micro-nano flow control chip, directly manufactures the chip with the self-closed micro-nano flow channel, and does not need to bond with a glass cover plate after the micro-nano flow channel is manufactured. The micro-nano flow channel chip manufactured by the method has good sealing performance and high structural precision, and does not deform at high temperature.

Disclosure of Invention

In order to solve the problems in the background technology, the invention provides a method for processing a self-sealing micro-nano flow control chip, which solves the problems of poor sealing performance and unstable structure of a liquid sample used by the micro-nano flow control chip.

The technical scheme adopted by the invention is as follows:

S1, as shown in fig. 1, fabricating a micro/nano flow channel composed of imprint glue and a residual layer thereon on a substrate of a glass or silicon wafer by a nanoimprint method, the micro/nano flow channel further including a residual layer thereon;

And other structures with liquid inlets and outlets are reserved on the micro-nano flow channels.

s2, as shown in fig. 2, removing the residual layer of the imprint resist by Reactive Ion Etching (RIE);

S3, as shown in FIG. 3, depositing a layer of silicon dioxide SiO on the substrate and the micro-nano flow channel by using an Atomic Layer Deposition (ALD) method₂or titanium oxide TiO₂The deposited layer of (a);

S4, as shown in figure 4, punching holes at two end parts of the micro-nano flow channel to be respectively used as an inlet and an outlet of a liquid sample;

and S5, as shown in figure 5, putting the substrate into a high-temperature heating furnace for heating, so that the imprinting glue is vaporized and volatilized, and taking out the substrate to obtain the chip after the imprinting glue is completely volatilized.

In the step S5, the heating temperature is 300-600 ℃.

The nanoimprinting in step S1 may be replaced by a photolithography plus development method. After photoetching and developing, a micro-nano flow channel consisting of photoresist and other required structures (such as a liquid sample inlet and a liquid sample outlet) are formed.

The reactive ion etching in step S2 may be replaced by Inductively Coupled Plasma (ICP) or Plasma stripping (Plasma stripping).

The atomic layer Deposition in step S3 can also be replaced by a Plasma Enhanced Chemical Vapor Deposition (PECVD) method.

The two end parts of the micro-nano flow channel are punched, namely two through holes are manufactured in the deposition layer, the two through holes are respectively communicated with the two end parts of the micro-nano flow channel, and the two through holes are respectively used as a liquid inlet and a liquid outlet of the micro-nano flow channel.

The invention has the advantages and beneficial effects that:

1. The sealing performance is good. Silicon dioxide or titanium dioxide can be tightly combined with a glass or silicon substrate by an atomic layer deposition or plasma enhanced chemical vapor deposition method, and excellent sealability is achieved.

2. The structure precision is high. The processes (including nano-imprinting, photoetching, atomic layer deposition, plasma enhanced chemical vapor deposition, reactive ion etching, inductively coupled plasma or plasma photoresist removal) used by the invention are standard processes in the semiconductor industry, and can realize the processing of micron-level and even nano-level high-precision structures.

3. There is no high temperature deformation. Compared with the most common thermal bonding process, all process temperatures used in the invention are lower than the softening temperature of the glass, so that the phenomena of high-temperature deformation and structural collapse of the glass can be avoided.

drawings

FIG. 1 is a schematic diagram of the implementation of step S1 of the method of the present invention;

FIG. 2 is a schematic diagram of the implementation of step S2 of the method of the present invention;

FIG. 3 is a schematic diagram of an implementation of step S3 of the method of the present invention;

FIG. 4 is a schematic diagram of an implementation of step S4 of the method of the present invention;

FIG. 5 is a schematic diagram of the implementation of step S5 of the method of the present invention.

in the figure: the device comprises a substrate 1, a micro-nano flow channel 2, a residual layer 3, a deposition layer 4, a punch 5 and a through hole 6.

Detailed Description

The invention is further illustrated by the following figures and examples.

The examples of the invention are as follows: