阅读说明：本技术 一种基于大规模光开关拓扑阵列的芯片架构 (Chip architecture based on large-scale optical switch topology array ) 是由 杨建义 郭晓晴 王曰海 余辉 于 2019-07-24 设计创作，主要内容包括：本发明公开了一种基于大规模光开关拓扑阵列的芯片架构。其设计方法如下：首先,对将光开关拓扑阵列进行划分,包括以下两种情况：①根据最小规模光交换网络端口数a×b和最大光交换网络端口数c×d将光开关拓扑阵列进行划分,a≥2,b≥2,c和d均大于a和b；以a×b光交换网络构成的光交换阵列作为最小单元位于一个芯片上；②所述的光开关拓扑阵列具有不同的光开关单元级数,除去①所述的光交换阵列,根据开关单元级数将光交换拓扑阵列划分为交换模块和与其相连的交叉波导阵列模块,每个模块位于一个芯片上；然后,将以上三种芯片按照拓扑规则进行连接,即得到基于大规模光开关拓扑阵列的芯片架构。本发明的芯片架构有较强的扩展性,且灵活性强。(The invention discloses a chip architecture based on a large-scale optical switch topological array. The design method comprises the following steps: firstly, the optical switch topology array is divided into the following two cases: dividing an optical switch topology array according to the number a multiplied by b of ports of a minimum-scale optical switching network and the number c multiplied by d of ports of a maximum optical switching network, wherein a is more than or equal to 2, b is more than or equal to 2, and c and d are both more than a and b; an optical switching array formed by a x b optical switching network is used as a minimum unit and is positioned on a chip; the optical switch topological array has different optical switch unit series, the optical switch array is removed, the optical switch topological array is divided into switching modules and cross waveguide array modules connected with the switching modules according to the switch unit series, and each module is positioned on one chip; and then, connecting the three chips according to a topological rule to obtain a chip framework based on the large-scale optical switch topological array. The chip architecture of the invention has strong expansibility and flexibility.)

1. A chip architecture based on a large-scale optical switch topological array is characterized in that the design method is as follows:

Firstly, the optical switch topology array is divided, including the following two cases: dividing an optical switch topology array according to the number a multiplied by b of ports of a minimum-scale optical switching network and the number c multiplied by d of ports of a maximum optical switching network, wherein a is more than or equal to 2, b is more than or equal to 2, and c and d are both more than a and b; an optical switching array formed by a x b optical switching network is used as a minimum unit to be positioned on a chip to obtain an optical switching array chip; the optical switch topological array has different optical switch unit series, after the optical switch array is removed, the optical switch topological array is divided into a switch module and a cross waveguide array module connected with the switch module according to the optical switch unit series, and each module is positioned on one chip to obtain a switch chip and a cross waveguide array chip;

Then, the three chips are connected according to a topological rule, and a chip framework based on a large-scale optical switch topological array can be obtained;

In the first step, the a × b optical switching network is designed by an optical switch unit according to a topology rule of an optical switch topology array, and the number of the a × b optical switching networks required by the optical switch array is c/a or d/b;

in the second step, the switching module is composed of 1 column of optical switch unit arrays, and when the optical switch units are n × m, the number of the optical switch units is c/n or d/m; the cross waveguide array chip is formed by a cross waveguide array, and the cross waveguide array is obtained by mutually connecting adjacent optical switch units in a topological array.

2. The scalable large scale optical switch topology array-based chip architecture of claim 1, wherein: the chip comprises optical switch units of the same level.

3. The scalable large scale optical switch topology array-based chip architecture of claim 1, wherein: the cross waveguide array chip is designed in a multilayer film deposition mode to realize a coupling waveguide array, isolation media are arranged among the films, and the refractive index of the isolation media is smaller than that of the films.

4. The scalable large scale optical switch topology array-based chip architecture of claim 1, wherein: and end face coupling or vertical coupling is adopted for packaging the chips.

5. The scalable large scale optical switch topology array-based chip architecture of claim 1, wherein: the input and output of the chip are coupled to the standard optical fiber array by end face coupling or vertical coupling.

6. The scalable large scale optical switch topology array-based chip architecture of claim 1, wherein: the switch unit is of an n multiplied by m structure, and m and n are positive integers.

Technical Field

The invention relates to a chip architecture based on a large-scale optical switch topological array, which aims to be applied to information exchange of a high-performance computer and a data center.

background

With the explosive growth of information, the drawbacks of electrical interconnection networks are increasingly prominent, and the electrical interconnection networks have small bandwidths, low transmission speeds, susceptibility to interference and large crosstalk, which all make the electrical-based transmission networks suffer from bottlenecks. Optical transmission has the advantages of incomparable electric transmission, such as high transmission speed, strong anti-interference capability and large bandwidth. Optical switching is one of the important components in optical interconnection and plays an important role in high-performance computers and data centers, but at present, commercial optical switches mainly perform data interconnection based on an optical fiber network and are large in size, while silicon-based devices are compatible with a CMOS (complementary metal oxide semiconductor) process, have the advantages of high integration level and low loss, are easy to integrate on a large scale and are relatively low in cost. Therefore, the silicon-based optical switching network gradually leaves the corner open and is deeply concerned by researchers. The silicon-based optical switching network can control the switching unit through the carrier dispersion effect or the thermo-optic effect of silicon, the network gradually increases from the initial 2-port and 4-port network to the 16-port and 32-port network, and the network topology is also gradually optimized. The current networks are mainly Spanke-Benes, Butterfly, Benes. The Spanke-Benes is characterized by no cross node, Butterfly is a strict non-blocking structure, and Benes is the slowest structure of the optical switch unit in the reconfigurable non-blocking switching network along with the increase of the number of ports. The largest scale optical switching network today is a 64-port network based on Benes architecture, with regulation by thermo-optic. As the number of ports continues to increase, the switching cells and crossed waveguides increase logarithmically or exponentially, resulting in higher losses and crosstalk, which also degrades the performance of the optical switching network. Meanwhile, the existing silicon-based optical switching network is integrated on one chip and cannot be expanded after being manufactured, so that the large-scale expansion of the optical switching network is greatly limited in the aspects of area and control.

Disclosure of Invention

In order to overcome the defects, the invention provides a chip architecture based on a large-scale optical switch topological array. By adopting the method, the manufactured chip can be expanded in a large scale.

The technical scheme adopted by the invention is as follows:

a chip architecture based on a large-scale optical switch topological array is designed by the following method: firstly, the optical switch topology array is divided into the following two cases: dividing an optical switch topology array according to the number a multiplied by b of ports of a minimum-scale optical switching network and the number c multiplied by d of ports of a maximum optical switching network, wherein a is more than or equal to 2, b is more than or equal to 2, and c and d are both more than a and b; an optical switching array formed by a x b optical switching network is used as a minimum unit to be positioned on a chip to obtain an optical switching array chip; the optical switch topological array has different optical switch unit series, after the optical switch array is removed, the optical switch topological array is divided into a switch module and a cross waveguide array module connected with the switch module according to the optical switch unit series, and each module is positioned on one chip to obtain a switch chip and a cross waveguide array chip; then, connecting the three chips obtained after division according to a topological rule to obtain a scalable topological array chip architecture based on the large-scale optical switch;

In the first step, the a × b optical switching network is obtained by connecting the optical switch units according to the topology rules of the optical switch topology array, because the topology rules of a topology structure are determined, when the number of required ports is determined to be a × b, the a × b optical switching network based on the topology rules can be obtained inevitably; the number of a x b optical switching networks required by the optical switching array is c/a or d/b;

In the second step, the switching module is composed of 1 column of optical switch unit arrays, and when the optical switch units are n × m, the number of the optical switch units is c/n or d/m; the crossed waveguide array module is composed of crossed waveguide arrays, and the crossed waveguide arrays are obtained by mutually connecting adjacent optical switch units in a topological array.

In the above technical solution, further, the chip includes optical switch units of the same number of stages.

Furthermore, the crossed waveguide array chip is obtained by adopting a multilayer film deposition mode, isolation media are arranged among the films, and the refractive index of the isolation media is smaller than that of the films.

Furthermore, end face coupling or vertical coupling is adopted for packaging among the chips.

furthermore, the input and the output of the chip are coupled to the standard optical fiber array in an end face coupling or vertical coupling mode.

The switch unit has a structure of n × m, and m and n are positive integers.

The invention relates to a chip architecture based on a large-scale optical switch topological array, which is designed based on a network topological structure, and is divided alternately according to a switch unit array and a crossed waveguide array to obtain an optical switch array, a switch module and a crossed waveguide array module, wherein each part is respectively positioned on one chip. The optical switch topology array chip architecture of any scale can be obtained by splicing the chips.

The invention has the beneficial effects that:

1. The chip architecture based on the large-scale optical switching topological array has strong expansibility, and the existing optical switching network is maximally expanded through the minimum design, so that the flexibility is strong.

2. The chip architecture based on the large-scale optical switching topological array can be used for designing a super-large-scale optical switching chip and providing sufficient area budget in a multi-chip coupling mode.

Drawings

FIG. 1 is a schematic diagram of an optical switch unit;

FIG. 2 is a schematic diagram of an optical switch topology array chip partitioning;

Fig. 3 is a schematic diagram of an optical switching network of 32 x 32 ports applied to a Benes architecture;

Fig. 4 is a schematic diagram of the optical switch network expanded from fig. 2 to 64 x 64 ports;

FIG. 5 is a schematic diagram of an optical switching network with 16 x 16 ports applied to a double-layer architecture; wherein 1A represents a switching chip, 2A represents a cross waveguide array chip, 1S represents an optical switching array chip, and 3 and 6 represent chip coupling.

Detailed Description

a chip architecture based on a large-scale optical switch topological array is designed by the following method: firstly, the optical switch topology array is divided into the following two cases: dividing an optical switch topology array according to the number a multiplied by b of ports of a minimum-scale optical switching network and the number c multiplied by d of ports of a maximum optical switching network, wherein a is more than or equal to 2, b is more than or equal to 2, and c and d are both more than a and b; an optical switching array formed by a x b optical switching network is used as a minimum unit to be positioned on a chip to obtain an optical switching array chip; the optical switch topological array has different optical switch unit series, after the optical switch array is removed, the optical switch topological array is divided into a switch module and a cross waveguide array module connected with the switch module according to the optical switch unit series, and each module is positioned on one chip to obtain a switch chip and a cross waveguide array chip; then, connecting the three chips obtained after division according to a topological rule to obtain a scalable topological array chip architecture based on the large-scale optical switch;

In the first step, the a × b optical switching network is obtained by connecting the optical switch units according to the topology rules of the optical switch topology array, because the topology rules of a topology structure are determined, when the number of required ports is determined to be a × b, the a × b optical switching network based on the topology rules can be obtained inevitably; the number of a x b optical switching networks required by the optical switching array is c/a or d/b;

in the second step, the switching module is composed of 1 column of optical switch unit arrays, and when the optical switch units are n × m, the number of the optical switch units is c/n or d/m; the crossed waveguide array module is composed of crossed waveguide arrays, and the crossed waveguide arrays are obtained by mutually connecting adjacent optical switch units in a topological array.

the chip comprises optical switch units of the same level. The crossed waveguide array chip is obtained by adopting a multilayer film deposition mode, isolation media are arranged among the films, and the refractive index of the isolation media is smaller than that of the films. And end face coupling or vertical coupling is adopted for packaging the chips. The input and output of the chip are coupled to the standard optical fiber array by end face coupling or vertical coupling. The switch unit is of an n multiplied by m structure, and m and n are positive integers.

The invention is further illustrated with reference to the following figures and examples.

FIG. 1 is a basic optical switch cell device with two inputs of I₁，I₂two outputs are O₁And O₂. The illustration does not imply that only 2 x 2 switch cells are used in a large-scale optical switch array. The number of basic switch unit ports depends on the topology array and the requirements.

Fig. 2 is a schematic diagram of optical switch topology array chip division. The topological array has obvious switch unit series. 1A, 1B … 1T,1U,1V (except 1S) are exchange chips, 1S is an optical exchange array chip, 2A, 2B … 2S … 2T,2U are crossed waveguide array chips, and the number of the chips is set according to requirements. The first layer of exchange chip 1A is coupled with the cross waveguide array chip 2A, and the cross waveguide array chip 2A is coupled with the exchange chip 1B; the exchange chip 1B and the cross waveguide array chip 2B are coupled and connected …, the exchange chip 1R and the cross waveguide array chip 2R are coupled and connected, and the cross waveguide array chip 2R and the optical exchange array chip 1S are coupled and connected. And connecting the modules according to the sequence until the optical switching chip architecture design is completed. The reference numbers in the figures do not represent actual module numbers.

fig. 3 is a schematic diagram of an optical switching network applied to Benes architecture, where 4 × 4 is the minimum-scale optical switching network and 32 × 32 is the maximum optical switching network, and the switching unit is a 2 × 2 switching unit. An optical switch array consisting of 8 (32/4)4 × 4 optical switch networks is located on the chip 4D. Except for 4D, the rest part is divided into a switching module and a crossed waveguide array module. The switching module is composed of 16(32/2) 2 multiplied by 2 switch units, and the cross waveguide array module is used for connecting the upper-stage cross module and the lower-stage cross module according to the topological rule. Each module is located on a chip, and chip communication is coupled and communicated by a chip coupling 6. Due to the strong symmetry of Benes structure, 4S switch chips are identical (S ═ a, B, C, E, … G). The optical switch array chip 4D is connected with the cross waveguide array chips 5C and 5D, respectively, and the cross waveguide array chips 5C and 5D are formed by four groups of cross waveguide arrays with 8 ports. The crossed waveguide array chips 5C and 5D are coupled to the switching chips 4C and 4E, respectively. The switching chips 4C, 4E are connected to the crossing waveguide array chips 5B, 5E, respectively. The crossed waveguide array chips 5B, 5E are composed of two sets of 16 × 16 port crossed waveguide arrays. The cross waveguide array chips 5B and 5E are connected to the switch chips 4B and 4F, respectively, and then connected to the cross waveguide array chips 5A and 5F, respectively, and the cross waveguide array chips 5A and 5F are composed of 1 group of 32 × 32 port cross waveguide arrays. And finally, the optical arrays are respectively connected with the switching chips 4A and 4G to realize 32 × 32 large-scale optical arrays.

Fig. 4 is a schematic diagram of a 64 × 64 large-scale optical switch array based on Benes structure expanded on the basis of fig. 3. Compared with the 32 × 32 optical switching network, only the cross waveguide array chips 12A (12H) are added, and the remaining chip types are the same as those in fig. 3, except that the number of chips used is different. The 64 × 64 large-scale optical switch array uses two optical switch array chips 11E (13E), 16 switch chips 11A, two crossed waveguide array chips 12A, and 4 crossed waveguide array chips 12B, 12C, 12D, respectively.

fig. 5 is a slicing scheme of a 16 × 16 port optical switching network based on a double-layer structure, in which a 1 × 2 switch unit and a 2 × 2 switch unit are used in a mixed manner, and the maximum number of ports existing in a topology array is 64 × 64. Since double-layer symmetry is inferior to Benes, the switched chips 15A and 15E after slicing are identical, and an array is formed by 16 1 × 2 switch units. The switch chips 15B and 15D are the same, and are formed of 32 1 × 2 switch cells in an array. The intersecting waveguide array chips are all different. The cross waveguide array chip 16A includes two sets of 16 × 16 port cross waveguide arrays, the cross waveguide array chip 16B includes 8 sets of 8 × 8 port cross waveguide arrays, the cross waveguide array chip 16C includes four sets of 16 × 16 port cross waveguide arrays, and the cross waveguide array chip 16D includes 1 set of 32 × 32 port cross waveguide arrays. The optical switch array chip 15C is constituted by 16 groups of 4 × 4 optical switch networks.