阅读说明：本技术 马达驱动电路 (Motor driving circuit ) 是由 杨家泰 陈昆民 于 2018-06-21 设计创作，主要内容包括：本发明公开一种马达驱动电路,包括驱动级电路、系统控制电路、控制信号产生电路与多个电流零点侦测器。驱动级电路包括多个反相器。系统控制电路提供占空周期信号。控制信号产生电路根据占空周期信号产生脉宽调制信号来控制各反相器中上臂晶体管与下臂晶体管的导通与关断,以提供驱动电流来驱动马达。电流零点侦测器侦测流经各反相器中上臂晶体管与下臂晶体管之间一节点的电流,并产生电流侦测信号。控制信号产生电路根据电流侦测信号调整脉宽调制信号,避免驱动级电路的等效占空周期缩短,以维持驱动电流的波形的完整性,使驱动电流的波形不会失真。(The invention discloses a motor driving circuit, which comprises a driving stage circuit, a system control circuit, a control signal generating circuit and a plurality of current zero detectors. The driving stage circuit includes a plurality of inverters. The system control circuit provides a duty cycle signal. The control signal generating circuit generates a pulse width modulation signal according to the duty cycle signal to control the on and off of the upper arm transistor and the lower arm transistor in each inverter so as to provide a driving current to drive the motor. The current zero detector detects a current flowing through a node between the upper arm transistor and the lower arm transistor in each inverter and generates a current detection signal. The control signal generating circuit adjusts the pulse width modulation signal according to the current detection signal, so that the equivalent duty cycle of the driving stage circuit is prevented from being shortened, the integrity of the waveform of the driving current is maintained, and the waveform of the driving current is not distorted.)

1. A motor driving circuit for providing a driving current to drive a motor, comprising:

a driver stage circuit comprising a plurality of inverters connected in parallel, wherein each of the plurality of inverters comprises an upper arm transistor and a lower arm transistor;

A system control circuit for providing a duty cycle signal;

A control signal generating circuit connected between the system control circuit and the driving stage circuit, the control signal generating circuit being configured to generate a plurality of pulse width modulation signals according to the duty cycle signal to control the on and off of the upper arm transistor and the lower arm transistor in each of the inverters, so as to provide the driving current to drive the motor; and

A plurality of current zero detectors connected between the driving stage circuit and the control signal generating circuit, respectively, the plurality of current zero detectors being configured to detect a current flowing through a node between the upper arm transistor and the lower arm transistor of each of the inverters, respectively, and generate a current detection signal;

The control signal generating circuit adjusts the pulse width modulation signals generated by the control signal generating circuit according to the current detection signals, so that the equivalent duty cycle of the driving stage circuit is not related to the dead time of the motor driving circuit.

2. The motor driving circuit as claimed in claim 1, wherein if the current detection signal generated by one of the current zero-point detectors indicates that the current flows out of the node in the inverter corresponding to the current zero-point detector, the control signal generating circuit advances an upper edge of the pwm signal provided to the upper arm transistor and a lower edge of the pwm signal provided to the lower arm transistor in the inverter by a time period, and the time period is equal to a dead time of the motor driving circuit.

3. The motor driving circuit according to claim 1, wherein if the current detection signal generated by one of the current zero-point detectors indicates that the current flows into the node in the inverter corresponding to the current zero-point detector, the control signal generating circuit advances a lower edge of the pwm signal provided to the upper arm transistor and an upper edge of the pwm signal provided to the lower arm transistor in the inverter by a time period, and the time period is equal to a dead time of the motor driving circuit.

4. The motor driving circuit as claimed in claim 1, wherein each of the pwm signals is generated according to the duty cycle signal and a default triangular wave.

5. The motor driving circuit as claimed in claim 4, wherein when the current detection signal generated by one of the current zero detectors indicates that the current flows out of the node in the inverter corresponding to the current zero detector, the control signal generating circuit generates the pulse width modulation signal according to the duty cycle signal and the adjusted predetermined triangular wave after adjusting the default triangular wave downward by a predetermined level.

6. The motor driving circuit according to claim 4, wherein when the current detection signal generated by one of the current zero detectors indicates that the current flows into the node in the inverter corresponding to the current zero detector, the control signal generating circuit generates the pulse width modulation signal according to the duty cycle signal and the adjusted predetermined triangular wave after adjusting the default triangular wave upward by a predetermined level.

7. a motor driver circuit according to claim 5 or claim 6 wherein the predetermined level is related to a dead time of the motor driver circuit.

8. The motor drive circuit according to claim 1, wherein the motor driven by the motor drive circuit is a single-phase motor or a three-phase motor.

9. the motor drive circuit according to claim 5, wherein when the motor driven by the motor drive circuit is a single-phase motor, the control signal generation circuit generates four pulse width modulation signals to control two inverters.

10. The motor drive circuit according to claim 5, wherein when the motor driven by the motor drive circuit is a three-phase motor, the control signal generation circuit generates six pulse width modulation signals to control three inverters.

Technical Field

The present invention relates to a motor driving circuit, and more particularly, to a motor driving circuit capable of compensating for Dead Time.

Background

Conventionally, in a motor driving circuit, a system control circuit generates a duty cycle signal PWM (usually, a pulse width modulation signal), and then a control signal generating circuit generates a control signal (usually, a pulse width modulation signal) according to the pulse width modulation signal to control the on/off of upper and lower arm transistors in each inverter in a driving stage circuit.

Referring to fig. 1, fig. 1 can be regarded as two inverters in a driving stage circuit of a single-phase motor or two inverters in a driving stage circuit of a three-phase motor. Considering that there is a transition time from on to off or from off to on, in order to avoid the circuit burnout caused by large current due to simultaneous on of the upper and lower arm transistors U, X and V, Y in each inverter of fig. 1, the control signal generating circuit generates the pwm signals for controlling the plurality of transistors U, X and V, Y, such that the pwm signals provided to the upper and lower arm transistors U, V and X, Y are complementary signals, and the transition edges of the pwm signals of the upper and lower arm transistors U, V and X, Y are delayed for a period of time. Generally, this delay Time is called Dead Time.

Referring to fig. 2A and 2B, fig. 2A and 2B are waveform diagrams of the upper and lower arm transistors U, X in one of the inverters in fig. 1 when the motor is driven. In fig. 2A and 2B, the pwm signals U and X are pwm signals provided to the upper arm transistor U and the lower arm transistor X, respectively.

as shown in fig. 2A and 2B, the pwm signals U and X provided to the upper arm transistor U and the lower arm transistor X are delayed by a dead time Td at the upper edges thereof, so as to turn on the upper arm transistor U and the lower arm transistor X in turn. When the motor is driven, a voltage VUO of the node UO is shown in fig. 2A during a period in which a current flows from the node UO to the coil, and a voltage VUO of the node UO is shown in fig. 2B during a period in which a current flows from the coil to the node UO. It should be noted that Vd in fig. 2A is the turn-on voltage of the body diode of the lower arm transistor X, Vd in fig. 2B is the turn-on voltage of the body diode of the upper arm transistor U, and VDD in fig. 2A and 2B is the supply voltage of the inverters, which is not described herein.

Assuming that the duty cycle signal PWM generated by the system control circuit has a period T and an on-time Ton, as can be seen from the voltage VUO at the node UO in fig. 2A, when the motor is driven, the equivalent duty cycle of the driving stage circuit is (Ton-Td)/T during the period when the current flows from the node UO to the coil; as can be seen from the voltage VUO at the node UO in fig. 2B, when the motor is driven, the equivalent duty cycle of the driver stage circuit is (Ton + Td)/T while the current flows from the coil to the node UO.

For example, in fig. 1, assuming that the current flows from node UO to the coil and flows through the coil to node VO, and the duty cycle of node UO is D1% and the duty cycle of node VO is D2%, the coil current is generated according to the equivalent duty cycle (D1-D2)%. In this case, if the equivalent duty cycle caused by the dead time Td is Td%, the equivalent duty cycle of the driving stage circuit generating the coil current is (D1% -Td%) - [ D2% + Td% ], i.e., [ (D1-D2) -2Td ]%, when the motor is driven.

Therefore, although the method of delaying the transition edges of the pwm signals of the upper and lower transistors by a dead time avoids the simultaneous conduction of the upper and lower transistors in each inverter, the equivalent duty cycle of the driving stage circuit is different from the designed value due to the dead time, and the waveform of the driving current is distorted.

Disclosure of Invention

In order to avoid that the upper and lower arm transistors in the driving stage circuit are conducted simultaneously and the integrity of the waveform of the driving current is maintained, so that the waveform of the driving current is not distorted, the invention provides a motor driving circuit which can ensure that the equivalent duty cycle of the driving stage circuit is not shortened due to dead time.

The motor driving circuit provided by the invention is used for providing a driving current to drive a motor. The motor driving circuit comprises a driving stage circuit, a system control circuit, a control signal generating circuit and a plurality of current zero detectors. The driving stage circuit includes a plurality of inverters connected in parallel, and the plurality of inverters respectively include an upper arm transistor and a lower arm transistor. The system control circuit is configured to provide a duty cycle signal. The control signal generating circuit is connected between the system control circuit and the driving stage circuit and used for generating a plurality of pulse width modulation signals according to the duty cycle signals to control the on and off of the upper arm transistor and the lower arm transistor in each inverter so as to provide driving current to drive the motor. The current zero detectors are respectively connected between the driving stage circuit and the control signal generating circuit, and are used for respectively detecting the current flowing through a node between the upper arm transistor and the lower arm transistor of each inverter, and accordingly generating current detection signals.

In an embodiment of the motor driving circuit provided by the present invention, if the current detection signal generated by one of the plurality of current zero detectors indicates that the current in the inverter corresponding to the current zero detector flows out of the node between the upper arm transistor and the lower arm transistor thereof, the control signal generating circuit advances the upper edge of the pwm signal provided to the upper arm transistor and the lower edge of the pwm signal provided to the lower arm transistor in the inverter by a time period. On the other hand, if the current detection signal generated by one of the plurality of current zero detectors indicates that the current in the inverter corresponding to the current zero detector flows into the node between the upper arm transistor and the lower arm transistor thereof, the control signal generation circuit advances the lower edge of the pulse width modulation signal supplied to the upper arm transistor and the upper edge of the pulse width modulation signal supplied to the lower arm transistor in the inverter by a time period.

in summary, the main feature of the motor driving circuit provided by the present invention is that the control signal generating circuit adjusts the plurality of pwm signals generated by the control signal generating circuit according to the plurality of current detecting signals, so that the equivalent duty cycle of the driving stage circuit is not shortened due to the dead time of the motor driving circuit, thereby maintaining the integrity of the waveform of the driving current and preventing the waveform of the driving current from being distorted.

For a better understanding of the nature and technical content of the present invention, reference should be made to the following detailed description of the invention, taken in conjunction with the accompanying drawings, which are included to illustrate, but are not to be construed as limiting the scope of the invention.

Drawings

Fig. 1 is a schematic diagram of a driving stage circuit of a general motor driving circuit.

Fig. 2A and 2B are waveform diagrams of the upper and lower arm transistors U, X in one of the inverters in the driving stage circuit of fig. 1 when the motor is driven.

Fig. 3 is a block diagram of a motor driving circuit according to an exemplary embodiment of the invention.

Fig. 4A and 4B are waveform diagrams of the upper and lower arm transistors U, X in one of the inverters in the motor driving circuit of fig. 3 when the motor is driven.

Fig. 5A and 5B show how the control signal generating circuit in the motor driving circuit of fig. 3 adjusts the upper and lower edges of the pwm signal generated by the control signal generating circuit according to the current detecting signal.

Fig. 6 is a waveform diagram illustrating the operation of the motor driving circuit according to an exemplary embodiment of the invention.

Fig. 7A is a simulation result of the current IUO and the current detection signal Iu when the motor driving circuit operates according to a general motor driving circuit, and fig. 7B is a simulation result of the current IUO and the current detection signal Iu when the motor driving circuit operates according to an exemplary embodiment of the present invention.

Detailed Description

Generally speaking, the motor driving circuit provided by the present invention is characterized in that while the Dead Time (Dead Time) is utilized to prevent the upper and lower transistors in the driving stage circuit from being turned on simultaneously, the equivalent duty cycle of the driving stage circuit is not shortened due to the Dead Time to maintain the integrity of the waveform of the driving current, so that the waveform of the driving current is not distorted.

Various exemplary embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some exemplary embodiments are shown. The inventive concept may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are disclosed so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. In the drawings, like numerals refer to like elements throughout.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various components or elements, these components or elements should not be limited by these terms. These terms are only used to distinguish one element or component from another element or component. Thus, a first component or element discussed below could be termed a second component or element without departing from the teachings of the present invention.

Referring to fig. 3, fig. 3 is a block diagram illustrating a motor driving circuit according to an exemplary embodiment of the invention.

As shown in fig. 3, the motor driving circuit provided in the present embodiment includes a driving stage circuit 12, a system control circuit 14, a control signal generating circuit 16, and a plurality of current zero detectors 18a and 18 b. The driver stage circuit 12 includes a plurality of inverters INV1 and INV2 connected in parallel, the inverter INV1 is composed of an upper arm transistor U and a lower arm transistor X, and the inverter INV2 is composed of an upper arm transistor V and a lower arm transistor Y. The system control circuit 14 is configured to provide a duty cycle signal PWM. The control signal generating circuit 16 is connected between the system control circuit 14 and the driving stage circuit 12, and is configured to generate a plurality of pulse width modulation signals U, X, V and Y according to the duty cycle signal PWM to control on and off of the upper arm transistor U and the lower arm transistor X in the inverter INV1 and on and off of the upper arm transistor V and the lower arm transistor Y in the inverter INV2, so as to provide a driving current to the coil to drive the motor.

It should be noted that the motor driving circuit provided in the present embodiment can be used for a single-phase motor or a three-phase motor. Therefore, although the driving stage 12 in fig. 3 only has two inverters INV1 and INV2, the present invention is not limited to be applied to a single-phase motor. For convenience of understanding, in the present embodiment, the motor driven by the motor driving circuit is a single-phase motor as an example, so the control signal generating circuit 16 generates four pwm signals u, x, v and y to control the two inverters INV1 and INV 2. In other embodiments, the motor driven by the motor driving circuit may also be a three-phase motor, in which case the control signal generating circuit 16 generates six pwm signals to control the three inverters.

The operation principle of the motor drive circuit provided in the present embodiment is substantially as follows.

The current zero detectors 18a and 18b are respectively connected between the driving stage circuit 12 and the control signal generating circuit 16, and are used for respectively detecting the currents IUO and IVO flowing through a node between the upper arm transistor U, V and the lower arm transistor X, Y in the inverters INV1 and INV2, and accordingly generating the current detection signals Iu and Iv. For the inverter INV1, when the current IUO detected by the current zero detector 18a is positive, it indicates that the current IUO in the inverter INV1 corresponding to the current zero detector 18a flows out of the node UO at this time, and the current zero detector 18a generates the current detection signal Iu with low potential. Conversely, when the current IUO detected by the current zero detector 18a is negative, it indicates that the current IUO flows into the node UO in the inverter INV1 corresponding to the current zero detector 18a, and the current zero detector 18a generates the high-level current detection signal Iu.

Then, the control signal generating circuit 16 adjusts the generated pulse width modulation signals u and x according to the current detection signal Iu. The purpose of the control signal generating circuit 16 adjusting the generated pwm signals u and x according to the current detecting signal Iu is to prevent the equivalent duty cycle of the driving stage circuit 12 from being shortened due to the dead time, so as to maintain the integrity of the driving current waveform and prevent the driving current waveform from being distorted.

In the following description, it will be further explained how the control signal generating circuit 16 adjusts the pwm signal generated by the motor driving circuit according to the current detecting signal, so that the equivalent duty cycle of the driving stage circuit 12 is not shortened due to the dead time. For convenience of illustration, only the inverter INV1 will be described in the following description, and those skilled in the art should understand the operation of other inverters during the operation of the motor.

Fig. 4A and 4B are waveform diagrams of the upper and lower arm transistors U, X in one of the inverters in the motor driving circuit of fig. 3 when the motor is driven.

Please refer to fig. 2A and fig. 4A simultaneously. In the present embodiment, when the current zero-point detector 18a generates the low-level current detection signal Iu, which indicates that the current IUO flows out of the node UO in the inverter INV1 at this time, in order to improve the situation that the equivalent duty cycle of the driving stage circuit in fig. 2A is (Ton-Td)/T, as shown in fig. 4A, the control signal generating circuit 16 advances the upper edge of the pwm signal U provided to the upper arm transistor U in the inverter INV1 and the lower edge of the pwm signal X of the lower arm transistor X by a time period, respectively (i.e., the upper edge of the pwm signal U of the upper arm transistor U and the lower edge of the pwm signal X of the lower arm transistor X in fig. 4A are advanced by a time period compared to fig. 2A). Thus, the time period in which the node UO is at the high level is equal to the on-time Ton of the duty cycle signal PWM, so the equivalent duty cycle of the driving stage circuit 12 is equal to Ton/T instead of (Ton-Td)/T.

On the other hand, when the current zero-point detector 18a generates the high-level current detection signal Iu, which indicates that the current IUO flows into the node UO in the inverter INV1 at this time, in order to improve the situation that the equivalent duty cycle of the driving stage circuit in fig. 2B is (Ton + Td)/T, as shown in fig. 4B, the control signal generating circuit 16 advances the lower edge of the pwm signal U provided to the upper arm transistor U in the inverter INV1 and the upper edge of the pwm signal X of the lower arm transistor X by a time period (i.e., the lower edge of the pwm signal U of the upper arm transistor U and the upper edge of the pwm signal X of the lower arm transistor X in fig. 4B are advanced by a time period compared to fig. 2B). Thus, the time period in which the node UO is at the high level is equal to the on-time Ton of the duty cycle signal PWM, so the equivalent duty cycle of the driving stage circuit 12 is equal to Ton/T, rather than (Ton + Td)/T.

In other words, through the foregoing adjustment of the pwm signals u and x, for the motor driving circuit provided in the present embodiment, the equivalent duty cycle of the driving stage circuit 12 has no relation with the dead time Td of the motor driving circuit, and the equivalent duty cycle of the driving stage circuit 12 is not shortened by the dead time Td.

It should be noted that, in the present embodiment, when the current zero-point detector 18a generates the current detection signal Iu with a low potential, the period of time in which the upper edge of the pwm signal U of the upper arm transistor U and the lower edge of the pwm signal X of the lower arm transistor X in the inverter INV1 are advanced is designed to be equal to the dead time Td of the motor driving circuit. In addition, when the current zero-point detector 18a generates the current detection signal Iu of high potential, a period in which the lower edge of the pulse width modulation signal U of the upper arm transistor U and the upper edge of the pulse width modulation signal X of the lower arm transistor X in the inverter INV1 are advanced is designed to be equal to the dead time Td of the motor drive circuit. In this way, the influence of the dead time Td on the equivalent duty cycle of the driving stage circuit 12 can be effectively eliminated.

Next, how the control signal generating circuit 16 in the motor driving circuit provided in this embodiment adjusts the upper and lower edges of the generated pwm signal according to the current detecting signal will be described.

In the present embodiment, the PWM signal provided to each inverter by the control signal generating circuit 16 is generated by a default triangular wave according to the duty cycle signal PWM provided by the system control circuit 14.

Referring to fig. 5A, when the current zero-point detector 18a generates the current detection signal Iu at the current outflow node UO of the inverter INV1, the control signal generating circuit 16 adjusts the default triangular wave Tri downward by a predetermined level to generate an adjusted predetermined triangular wave TriL in order to advance the upper edge of the pwm signal U provided to the upper arm transistor U of the inverter INV1 and the lower edge of the pwm signal X provided to the lower arm transistor X by a dead time Td. In fig. 5A, the PWM signal u generated according to the duty cycle signal PWM and the default triangle wave Tri is the PWM signal u shown in fig. 4A, and the PWM signal x generated according to the duty cycle signal PWM and the adjusted preset triangle wave Tri is the PWM signal x shown in fig. 4A. In this way, the upper edge of the pwm signal U provided to the upper arm transistor U of the inverter INV1 and the lower edge of the pwm signal X provided to the lower arm transistor X are advanced by a dead time Td, so that the equivalent duty cycle of the driver stage circuit 12 is equal to Ton/T and not equal to (Ton-Td)/T.

On the other hand, referring to fig. 5B, when the current zero-point detector 18a generates the current detection signal Iu indicating the current flowing into the node UO in the inverter INV1, in order to advance the lower edge of the pwm signal U provided to the upper arm transistor U in the inverter INV1 and the upper edge of the pwm signal X of the lower arm transistor X by a dead time Td, the control signal generating circuit 16 adjusts the default triangular wave Tri upward by a predetermined level to generate an adjusted predetermined triangular wave Tri h. In fig. 5B, the PWM signal x generated according to the duty cycle signal PWM and the default triangle wave Tri is the PWM signal x shown in fig. 4B, and the PWM signal u generated according to the duty cycle signal PWM and the adjusted preset triangle wave Tri is the PWM signal u shown in fig. 4B. In this way, the lower edge of the pwm signal U provided to the upper arm transistor U in the inverter INV1 and the upper edge of the pwm signal X provided to the lower arm transistor X are advanced by a dead time Td, so that the equivalent duty cycle of the driving stage circuit 12 is equal to Ton/T and not equal to (Ton + Td)/T.

It should be noted that, in the aforementioned adjusting mechanism for the preset triangular wave, the preset level is related to the dead time Td of the motor driving circuit, so as to effectively eliminate the influence of the dead time Td on the equivalent duty cycle of the driving stage circuit 12.

Generally, the operation mechanism of the motor driving circuit provided in the present embodiment can refer to fig. 6, and fig. 6 is a waveform diagram of the motor driving circuit according to an exemplary embodiment of the invention when operating. As can be summarized from fig. 6, when the current IUO detected by the current zero-point detector 18a is positive, the control signal generating circuit 16 adjusts the default triangular wave Tri downward by a predetermined level to obtain an adjusted predetermined triangular wave TriL. Then, pulse width modulation signals U and X provided to the upper arm transistor U and the lower arm transistor X of the inverter INV1 are generated according to the duty cycle signal PWM, the default triangular wave Tri, and the adjusted preset triangular wave TriL, respectively. On the other hand, when the current IUO detected by the zero-current detector 18a is negative, the control signal generating circuit 16 adjusts the default triangle wave Tri upward by a predetermined level to obtain an adjusted predetermined triangle wave Tri h. Then, pulse width modulation signals U and X provided to the upper arm transistor U and the lower arm transistor X of the inverter INV1 are generated according to the duty cycle signal PWM, the default triangular wave Tri, and the adjusted preset triangular wave Tri h, respectively.

[ possible effects of examples ]

As described above, in the motor driving circuit of the present invention, the control signal generating circuit adjusts the pulse width modulation signals to be provided to the driving stage circuit according to the current detection signal, so as to prevent the equivalent duty cycle of the driving stage circuit 12 from being shortened due to the dead time. Therefore, the integrity of the waveform of the driving current can be maintained, and the waveform of the driving current cannot be distorted.

Since the equivalent duty cycle of the driver stage circuit 12 is not shortened by the dead time in the present invention, the waveform of the driving current (e.g., current IUO) supplied to the coil is not distorted.

Referring to fig. 7A and 7B, fig. 7A is a simulation result of the current IUO and the current detection signal Iu when the motor driving circuit operates according to the general motor driving circuit, and fig. 7B is a simulation result of the current IUO and the current detection signal Iu when the motor driving circuit operates according to an exemplary embodiment of the invention. As shown in fig. 7B, since the motor driving circuit provided by the present invention has a mechanism for adjusting the pwm signals to be provided to the driving stage circuit according to the current detection signal, the integrity of the waveform of the current IUO can be maintained at the zero crossing point of the current IUO (i.e., when the current detection signal changes from positive to negative or from negative to positive) when the motor driving circuit provided by the present invention is operated. In contrast, as shown in fig. 7A, since the conventional motor driving circuit does not have a mechanism for adjusting the pwm signals to be provided to the driving stage circuit according to the current detection signal, the integrity of the waveform of the current IUO cannot be achieved at the zero crossing point of the current IUO (i.e., when the current detection signal changes from positive to negative or from negative to positive).

It should also be noted that while in the foregoing specification, the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the present inventive concept as defined by the following claims.