阅读说明：本技术 一种用于实现时间同步的修正方法及装置 (correction method and device for realizing time synchronization ) 是由 余建国 单飞龙 王志方 董均国 常鑫 俞正 于 2019-09-10 设计创作，主要内容包括：本发明实施例公开了一种用于实现时间同步的修正方法及装置,方法包括：在接收主时钟发送的不携带数据的预报文,从预报文中获得预报文保存的第一时间戳和从主时钟TCP/IP协议栈到从时钟TCP/IP协议栈的网络延时,并利用第一时间戳、第二时间戳和所述网络延时,修正所述从时钟TCP/IP协议栈的时间。本发明实施例考虑了基站间传输时延存在不对称问题,利用预报文记录从主时钟TCP/IP协议栈到从时钟TCP/IP协议栈的网络延时,进而应用本发明实施例提供的方法能够提高基站间的时间同步精度。(The embodiment of the invention discloses a correction method and a correction device for realizing time synchronization, wherein the method comprises the following steps: and after receiving a forecast message which is sent by a master clock and does not carry data, obtaining a first time stamp stored in the forecast message and network delay from a master clock TCP/IP protocol stack to a slave clock TCP/IP protocol stack from the forecast message, and correcting the time of the slave clock TCP/IP protocol stack by using the first time stamp, the second time stamp and the network delay. The embodiment of the invention considers the problem of asymmetry of transmission time delay among base stations, and records the network time delay from a master clock TCP/IP protocol stack to a slave clock TCP/IP protocol stack by using the forecast message, so that the method provided by the embodiment of the invention can improve the time synchronization precision among the base stations.)

1. A correction method for achieving time synchronization, applied to a slave clock, the method comprising:

Receiving a pre-message which is sent by a main clock and does not carry data;

Obtaining a first timestamp stored in the pre-message and network delay from a master clock TCP/IP protocol stack to a slave clock TCP/IP protocol stack from the forecast message, wherein the first timestamp is as follows: when the master clock sends a pre-message, the time stamp of the TCP/IP protocol stack of the master clock;

Correcting the time of the slave clock TCP/IP protocol stack by using the first timestamp, the second timestamp and the network delay, wherein the second timestamp is as follows: and when the slave clock receives the pre-message, the slave clock is the time stamp of the TCP/IP protocol stack.

2. the method of claim 1, wherein the first timestamp is: the timestamp of the lowest physical layer in the master clock TCP/IP protocol stack is as follows: and the time stamp of the lowest physical layer in the slave clock TCP/IP protocol stack.

3. The method of claim 2, wherein said correcting the time of the slave clock TCP/IP protocol stack using the first timestamp, the second timestamp, and the network delay comprises:

Correcting the time of the slave clock TCP/IP protocol stack according to the following expression by utilizing the first time stamp, the second time stamp and the network delay;

The expression is: t is t₂-t_offset，t_offset＝t₂-t₁-d；

Wherein, t₁Is a first time stamp, t₂Is the first timestamp, d is the network delay, t_offsetand t is the time deviation from the time of the slave clock TCP/IP protocol stack to the time of the master clock TCP/IP protocol stack, and the corrected time of the slave clock TCP/IP protocol stack.

4. The method according to any one of claims 1 to 3, wherein the pre-message is obtained and stored according to a weighted average algorithm, a delay decomposition algorithm or a transparent clock from a master clock TCP/IP protocol stack to a slave clock TCP/IP protocol stack.

5. A correction device for achieving time synchronization, applied to a slave clock, the device comprising:

the receiving module is used for receiving a pre-message which is sent by a main clock and does not carry data;

A time obtaining module, configured to obtain, from the precursor message, a first timestamp stored in the precursor message and a network delay from a master clock TCP/IP protocol stack to a slave clock TCP/IP protocol stack, where the first timestamp is: when the master clock sends a pre-message, the time stamp of the TCP/IP protocol stack of the master clock;

A delay correction module, configured to correct the time of the slave clock TCP/IP protocol stack by using the first timestamp, the second timestamp, and the network delay, where the second timestamp is: and when the slave clock receives the pre-message, the slave clock is the time stamp of the TCP/IP protocol stack.

6. The apparatus of claim 5, wherein the first timestamp is: the timestamp of the lowest physical layer in the master clock TCP/IP protocol stack is as follows: and the time stamp of the lowest physical layer in the slave clock TCP/IP protocol stack.

7. The apparatus of claim 6, wherein the delay modification module comprises:

the time delay correction submodule is used for correcting the time of the main clock TCP/IP protocol stack according to the following expression by utilizing the first time stamp, the second time stamp and the network time delay;

the expression is: t is t₂-t_offset，t_offset＝t₂-t₁-d；

Wherein, t₁Is a first time stamp, t₂Is the first timestamp, d is the network delay, t_offsetAnd t is the time deviation from the time of the slave clock TCP/IP protocol stack to the time of the master clock TCP/IP protocol stack, and the corrected time of the slave clock TCP/IP protocol stack.

8. The device according to any one of claims 5 to 7, wherein the pre-message is stored after obtaining the network delay from the master clock TCP/IP protocol stack to the slave clock TCP/IP protocol stack according to a weighted average algorithm, a delay decomposition algorithm or a transparent clock.

9. An electronic device is characterized by comprising a processor, a communication interface, a memory and a communication bus, wherein the processor and the communication interface are used for realizing mutual communication by the memory through the communication bus;

A memory for storing a computer program;

A processor for implementing the method steps of any one of claims 1 to 5 when executing a program stored in the memory.

10. A computer-readable storage medium, characterized in that a computer program is stored in the computer-readable storage medium, which computer program, when being executed by a processor, carries out the method steps of any one of the claims 1-5.

Technical Field

The present invention relates to the field of network technologies, and in particular, to a correction method and apparatus for achieving time synchronization.

background

With the continuous development of the current social industrial control field, the aerospace field and the fifth generation mobile communication technology, the requirement on the time synchronization precision among the base stations is higher and higher. The IEEE1588 protocol is widely used because it can achieve sub-microsecond or even nanosecond level time synchronization.

IEEE15888 Protocol, PTP Protocol (Precision Time Protocol) for short, which is a Protocol called "Precision Time synchronization Protocol standard of network measurement and control system" in chinese, was drafted by the network Precision clock synchronization committee in 2002 as the first edition, and published in 2008 as IEEE1588 Protocol, IEEE1588v2, the second edition. The IEEE1588 protocol is a set of precise time synchronization technology used in a network measurement and control system, realizes precise synchronization of frequency and phase of time between base stations, and the time synchronization precision can reach the level of submicroseconds.

The establishment of the IEEE1588 protocol is based primarily on two ideal assumptions: the symmetry of the transmission link and the master and slave clock frequencies are stable. However, in an actual communication link, the transmission delay of the master clock and the slave clock has an asymmetric problem, so that the accuracy of time synchronization between base stations of the IEEE1588 protocol in the prior art is low.

Disclosure of Invention

the embodiment of the invention aims to provide a correction method and a correction device for realizing time synchronization so as to improve the time synchronization precision between base stations.

In order to achieve the above object, an embodiment of the present invention discloses a correction method for implementing time synchronization, including:

Receiving a pre-message which is sent by a main clock and does not carry data;

Obtaining a first timestamp stored in the pre-message and network delay from a master clock TCP/IP protocol stack to a slave clock TCP/IP protocol stack from the forecast message, wherein the first timestamp is as follows: when the master clock sends a pre-message, the time stamp of the TCP/IP protocol stack of the master clock;

And correcting the time of the slave clock TCP/IP protocol stack by utilizing the first time stamp, the second time stamp and the network delay, wherein the second time stamp is as follows: and when the slave clock receives the pre-message, the slave clock is the time stamp of the TCP/IP protocol stack.

Further, the first timestamp is: the timestamp of the lowest physical layer in the master clock TCP/IP protocol stack is as follows: and the time stamp of the lowest physical layer in the slave clock TCP/IP protocol stack.

further, the correcting the time of the slave clock TCP/IP protocol stack by using the first timestamp, the second timestamp, and the network delay includes:

Correcting the time of the TCP/IP protocol stack of the main clock according to the following expression by utilizing the first time stamp, the second time stamp and the network delay;

The expression is: t is t₂-t_offset，t_offset＝t₂-t₁-d；

Wherein, t₁Is a first time stamp, t₂Is the first timestamp, d is the network delay, t_offsetAnd t is the time deviation from the time of the slave clock TCP/IP protocol stack to the time of the master clock TCP/IP protocol stack, and the corrected time of the slave clock TCP/IP protocol stack.

Further, the pre-message obtains and stores the network delay from the master clock TCP/IP protocol stack to the slave clock TCP/IP protocol stack according to a weighted average algorithm, a delay decomposition algorithm or a transparent clock.

A correction apparatus for achieving time synchronization, applied to a slave clock, the apparatus comprising:

the receiving module is used for receiving a pre-message which is sent by a main clock and does not carry data;

a time obtaining module, configured to obtain, from the precursor message, a first timestamp stored in the precursor message and a network delay from a master clock TCP/IP protocol stack to a slave clock TCP/IP protocol stack, where the first timestamp is: when the master clock sends a pre-message, the time stamp of the TCP/IP protocol stack of the master clock;

a delay correction module, configured to correct the time of the slave clock TCP/IP protocol stack by using the first timestamp, the second timestamp, and the network delay, where the second timestamp is: and when the slave clock receives the pre-message, the slave clock is the time stamp of the TCP/IP protocol stack.

Further, the first timestamp is: the timestamp of the lowest physical layer in the master clock TCP/IP protocol stack is as follows: and the time stamp of the lowest physical layer in the slave clock TCP/IP protocol stack.

further, the delay correction module includes:

The time delay correction submodule is used for correcting the time of the main clock TCP/IP protocol stack according to the following expression by utilizing the first time stamp, the second time stamp and the network time delay;

the expression is: t is t₂-t_offset，t_offset＝t₂-t₁-d；

Wherein, t₁Is a first time stamp, t₂Is the first timestamp, d is the network delay, t_offsetAnd t is the time deviation from the time of the slave clock TCP/IP protocol stack to the time of the master clock TCP/IP protocol stack, and the corrected time of the slave clock TCP/IP protocol stack.

Further, the pre-message obtains and stores the network delay from the master clock TCP/IP protocol stack to the slave clock TCP/IP protocol stack according to a weighted average algorithm, a delay decomposition algorithm or a transparent clock.

In another aspect of the present invention, there is also provided an electronic device, including a processor, a communication interface, a memory and a communication bus, where the processor, the communication interface, and the memory complete communication with each other through the communication bus;

A memory for storing a computer program;

and the processor is used for enabling the computer to execute any one of the correction methods for realizing time synchronization when the processor executes the program stored in the memory.

In another aspect of the present invention, the embodiment of the present invention further provides a computer program stored in a computer-readable storage medium, which, when run on a computer, causes the computer to execute any one of the above-mentioned correction methods for achieving time synchronization.

in another aspect of the present invention, the present invention also provides a computer program product containing instructions, which when run on a computer, causes the computer to execute any one of the above-mentioned correction methods for achieving time synchronization.

the method receives a forecast message which is sent by a master clock and does not carry data, obtains a first time stamp stored in a pre-message and network delay from a master clock TCP/IP protocol stack to a slave clock TCP/IP protocol stack from the forecast message, and corrects the time of the slave clock TCP/IP protocol stack by using the first time stamp, the second time stamp and the network delay. Compared with the prior art, the embodiment of the invention considers the problem of asymmetry of transmission delay among base stations, and records the network delay from a master clock TCP/IP protocol stack to a slave clock TCP/IP protocol stack by using the forecast message, thereby improving the time synchronization precision among the base stations. Of course, it is not necessary for any product or method of practicing the invention to achieve all of the above-described advantages at the same time.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic flowchart of an IEEE1588 latency request response mechanism according to an embodiment of the present invention;

Fig. 2 is a schematic flowchart of a correction method for implementing time synchronization according to an embodiment of the present invention;

Fig. 3 is a schematic diagram of a message transmission between base stations according to an embodiment of the present invention;

Fig. 4 is a schematic diagram of a frame structure of a Pre _ sync message or a Pre _ delay message provided in the embodiment of the present invention;

Fig. 5 is a schematic structural diagram of synchronization of master and slave clocks based on PHY layer stamping and pre-packet according to an embodiment of the present invention;

Fig. 6 is a schematic structural diagram of an IEEE1588 protocol network model according to an embodiment of the present invention.

Fig. 7 is a schematic structural diagram of a correction apparatus for implementing time synchronization according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In order to understand the embodiments of the present invention more thoroughly, the working principle of IEEE1588 protocol is described and analyzed in detail, specifically:

The IEEE1588 protocol defines two mechanisms for delay measurement: the other two mechanisms are realized on the premise that the communication link is symmetrical. The scheme for sending the forecast text adopted in the embodiment of the invention does not relate to a transparent clock, so that the first measurement mechanism is mainly analyzed. The implementation process of the delay request measurement mechanism of the 1588 protocol is shown in fig. 1:

IEEE1588 clock synchronization is based on time stamps, which are stamped at the entry or exit of a particular event message. As shown in fig. 1, the master clock sends periodic synchronization information sync to each slave clock in the distributed network, and the time when the information is sent is recorded as t 1. The slave clock obtains the timestamp t2 when the sync message arrives. The master clock may already contain its own egress timestamp t1 in the synchronization message sync, or may transmit the timestamp to the slave clock using a subsequent follow message flow _ up.

similarly, the Delay request message Delay _ req is sent from the clock and the exit timestamp t3 is obtained. The master clock receives this message at time t4 and submits a delayed response request message Delay _ resq with a time stamp of t4 back to the slave clock. When the master and slave clocks have approximately the same clock rate, only the initial clock offset exists due to the different boot times. Wherein d is_ms，d_smThe total delay from the master clock to the slave clock link and the total delay from the slave clock to the master clock link, respectively. From the above process, the master-slave time offset can be obtained:

d_ms＝t2-t1-offset1；

d_sm＝t4-t3+offset2；

delay＝(d_ms-d_sm)/2；

In the above equation, the offsets 1 and 2 represent the master-slave clock deviations of the uplink and downlink in the network, respectively, the offsets represent the master-slave clock deviations in the whole network, and the delay represents the average delay of the synchronous network between the master clock and the slave clock. In the first version of IEEE1588 protocol, assuming link symmetry (delay ═ 0), the master-slave time offset is obtained through t1-t 4. And an asymmetry field is introduced in IEEE1588v2 to compensate for the known asymmetry. The clock synchronization in IEEE1588 is not limited to any particular communication medium, but can be used on any medium that allows paired message exchange. Common media, such as switched ethernet or wireless networks, impose different delays on the receive and transmit paths, resulting in asymmetry.

from the description of the above principle, it can be known that the network delay of transmission has a serious influence on the accuracy of IEEE1588 time synchronization. The line delay generated by the physical network is generally stable, and the protocol stack and the storage and forwarding can generate larger jitter due to the influence of uncertain factors in the running process, which has larger influence on the synchronization precision. However, in the actual measurement control network, if the network link is merely assumed to be symmetrical, the actual time synchronization accuracy and the simulation accuracy may be greatly different.

Based on the above description, the present invention will be explained in detail below by way of specific examples.

Referring to fig. 2, fig. 2 is a schematic flowchart of a correction method for implementing time synchronization according to an embodiment of the present invention, applied to a slave clock, including the following steps:

S101: and receiving a pre-message which is sent by a main clock and does not carry data.

The master clock and the slave clock belong to different base stations, the slave clock can be regarded as a receiving party, and the master clock can be regarded as a sending party.

And sending a pre-message from a master clock, namely a sending end, wherein the destination address of the pre-message is a slave clock, namely a receiving end.

The IEEE1588 protocol defines five event messages and seven general messages. The event information is to be stamped with an accurate time stamp such as a synchronization message Sync, a Delay request message Delay _ req, a point Delay request message Pdelay _ req, and a point Delay response message Pdelay _ resp at the time of transmission and reception. The general messages do not need to be time stamped, such as notification message Announce, Follow message Follow _ up, delayed response message Delay _ resp, point Delay Follow message Pdelay _ resp _ Follow _ up, Management message Management, and signal message Signaling. In the delayed request response mechanism, the timestamp information is acquired and transmitted by a common clock and a boundary clock by using a synchronous message Sync, a delayed request message Delay _ req, a Follow _ up and a Delay _ resp.

the Pre-message of the embodiment of the invention is a Pre-message Pre _ sync sent by a master clock and a forecast message Pre _ delay sent by a slave clock. The Pre _ sync is a forecast message which is sent by a master clock before sending a data message and is destined to a slave clock, and mainly has the functions of measuring the network delay from the master clock to an uplink of the slave clock and writing the data into a correction Field of the Pre _ sync for recording so as to be used for extracting and using a subsequent real data packet. When the Pre _ sync is received from the slave clock, Pre _ delay is sent in order to confirm the reception of the precursor Pre _ sync of the master clock from the slave clock and to measure the downlink network delay. That is, the Pre _ delay message is sent only when the slave clock receives the Pre _ sync sent by the master clock. Pre _ delay represents the prediction from the slave clock back to the master clock, whose main role is to measure the network delay of the downlink from the slave clock to the master clock, also writing this data into the correction Field of Pre _ delay. The frame structures of the Pre _ sync and Pre _ delay messages are shown in fig. 3, and specifically include: event message payload, modification field, network protocol header and preamble.

In fig. 3, the frame structures of two Pre-messages Pre _ sync and Pre _ delay are identical to the message structure in IEEE1588, the only difference is that the Pre-message does not carry data information, and IEEE1588 needs to carry data information for data transmission, the frame structures of the two Pre-messages are identical to facilitate unified management and processing of the message, the prediction message is a message sent in advance before the master clock sends a data packet to the slave clock, and is mainly used for calculating the network delay between the master clock and the slave clock in real time, writing the network delay into the correction domain for standby, and when the master clock sends a data packet to the slave clock again, the network delay in the current period can be estimated by using the network delay in the correction domain of the prediction message, so that high-precision time synchronization of the master clock and the slave clock can be realized.

Generally, a base station where a clock with the most stable clock crystal oscillator is located is selected as a master clock base station in a local area network, that is, the time of the master clock base station is the most accurate, that is, the most stable clock is selected in the local area network and an optimal master clock algorithm BMC is adopted; the other base stations are more or less time-skewed, i.e. only the clock of the base station interacting with the master base station, i.e. the slave clock, is corrected, the clock of the master clock base station, i.e. the master clock, is assumed to be the ideal clock, i.e. the master clock is already the exact clock, and no correction is needed.

S102: obtaining a first timestamp stored in the pre-message and a network delay from a master clock TCP/IP (Transmission Control Protocol/Internet Protocol) Protocol stack to a slave clock TCP/IP Protocol stack from the forecast message, wherein the first timestamp is as follows: and when the master clock sends the pre-message, the master clock is the time stamp of the TCP/IP protocol stack.

The following details are described taking IEEE1588 protocol as an example, and specifically include:

The IEEE1588 time synchronization system often uses a TCP/IP protocol stack, as shown in fig. 4, which is, from top to bottom: an application layer, a MII (Media Independent Interface), a MAC (Media access control) layer, and a physical layer. The IEEE1588 Protocol marks a message transmission or reception timestamp in an application layer Protocol, encapsulates timestamp information synchronized by PTP (Precision Time Protocol) to be transmitted in a local Protocol stack of a transmitting end, i.e., a master clock, to form a message having a certain format, processes data in the message by using a network interface chip in a physical layer, and finally converts the data into a level signal suitable for transmission on a physical medium. Because most of the TCP/IP protocol stack is realized by software, the time spent each time from generation to sending out of the message is uncertain and different, and therefore the residence time delay in the TCP/IP protocol stack has certain influence on the time synchronization precision of IEEE 1588.

Software and hardware time stamping based on residence time in a TCP/IP protocol stack can be roughly divided into A, B, C, D four time stamping modes as shown in fig. 4, wherein the four time stamping modes are respectively: stamping at the application layer, stamping at the MAC layer, stamping at the MII between the MAC and the physical layer, stamping at the physical layer.

In fig. 4, a represents the residence time delay in the TCP/IP protocol stack, b represents the network switching device delay, and c represents the transmission path delay in the IEEE1588 time synchronization packet slave master clock. During the process of constructing and sending messages to the application layer of the slave clock, the messages are generally specified by a preamble specified by a physical layer protocol, then a header specified by other protocols, and finally user data. Regardless of the transmission mechanism, IEEE1588 specifies a specific point (usually at the beginning of a data frame) in the timing message as a detection point, which is called a timestamp point. A timestamp is generated when a timestamp point of a message passes this detection point.

The function of the pre-message is to record the network delay from the master clock TCP/IP protocol stack to the slave clock TCP/IP protocol stack.

in one embodiment of the present invention, the forecasted text can be calculated according to a weighted average algorithm, a delay decomposition algorithm, or a TC clock: and the transparent clock obtains and stores the network delay from the master clock TCP/IP protocol stack to the slave clock TCP/IP protocol stack.

The scheme provided by the embodiment of the invention proves that the high-precision time synchronization precision of the sub-microsecond level can be realized, and the requirement of a distributed network on the time synchronization precision is met.

therefore, the network delay from the master clock TCP/IP protocol stack to the slave clock TCP/IP protocol stack obtained by the embodiment of the invention can correct the slave clock, so that the slave clock can quickly catch up with the master clock, and the high-precision time synchronization of the master clock and the slave clock is realized.

The network delay from the master clock TCP/IP protocol stack to the slave clock TCP/IP protocol stack may be: the difference value between the starting time stamp of the master clock TCP/IP protocol stack and the terminating time stamp of the slave clock TCP/IP protocol stack is as follows: selecting a target for detecting a timestamp from an application layer, a network layer MAC, an MII and a physical layer in a TCP/IP protocol stack of a master clock, wherein the timestamp of the target is a starting timestamp; the termination timestamp is a timestamp of a target selected from an application layer, a network layer MAC, an MII and a physical layer in a clock TCP/IP protocol stack and corresponding to the starting timestamp.

for example, MII is selected from the master clock TCP/IP protocol stack as a target for detecting the timestamp, the start timestamp is the timestamp of MII, a target corresponding to the start timestamp is selected from the slave clock TCP/IP protocol stack, that is, the MII in the slave clock TCP/IP protocol stack, and the end timestamp is the timestamp of MII.

the first timestamp stored in the pre-message and the network time can be extracted and used for the message carrying the real data. That is, when the master clock sends the message carrying the data again, the network delay of the current time period of the slave clock can be estimated by using the network delay stored in the forecast message, so as to realize high-precision time synchronization between the base stations.

S103, correcting the time of the slave clock TCP/IP protocol stack by using the first time stamp, the second time stamp and the network delay, wherein the second time stamp is as follows: and when the slave clock receives the pre-message, the slave clock is the time stamp of the TCP/IP protocol stack.

Based on the above analysis of time stamping, the time delay caused by different time stamping positions is different, and the time delay is smaller when the time delay is closer to the bottom layer position. It can be seen that to eliminate such delay, the timestamp of PTP data packet transmission or reception is marked at the lowest possible protocol layer, so as to avoid the influence caused by the fluctuation of the higher layer protocol.

Based on the above analysis, in view of the fact that the positions of the respective selected target timestamps in the master clock TCP/IP protocol stack and the slave clock TCP/IP protocol stack are different, and thus the caused delay is also different, but the closer the selected target is to the bottom layer, the smaller the network delay is, based on this, in an embodiment of the present invention, the first timestamp is: the timestamp of the lowest physical layer in the master clock TCP/IP protocol stack is as follows: and the time stamp of the lowest physical layer in the slave clock TCP/IP protocol stack.

therefore, the first time stamp is the time stamp of the bottommost physical layer in the master clock TCP/IP protocol stack, and the second time stamp is the time stamp of the bottommost physical layer in the slave clock TCP/IP protocol stack, so that the network delay can be further reduced, and the time synchronization precision between base stations can be further improved.

In an embodiment of the present invention, a specific implementation manner of implementing S103 may include the following steps:

Correcting the time of the slave clock TCP/IP protocol stack according to the following expression by utilizing the first time stamp, the second time stamp and the network delay;

the above-mentionedThe expression is as follows: t is t₂-t_offset，t_offset＝t₂-t₁-d；

Wherein, t₁Is a first time stamp, t₂Is the second timestamp, d is the network delay, t_offsetand t is the time deviation from the time of the slave clock TCP/IP protocol stack to the time of the master clock TCP/IP protocol stack, and the corrected time of the slave clock TCP/IP protocol stack.

The time of the corrected slave clock TCP/IP protocol stack is synchronous with the time of the master clock TCP/IP protocol stack, namely equivalent. That is, the time of the master clock TCP/IP protocol stack is the same as the time of the slave clock TCP/IP protocol stack.

To facilitate a clearer understanding, an example is given for illustration, specifically: setting a time stamp, namely a first time stamp, of the bottommost layer of a TCP/IP protocol stack of a master clock as 12:00, at this moment, the timestamp of the bottommost layer of the slave clock TCP/IP protocol stack is 12:01, the master clock sends a pre-message, and records the first timestamp 12:00 in a forecast message, the network delay from the physical layer of the bottommost layer of the master clock TCP/IP protocol stack to the physical layer of the bottommost layer of the slave clock TCP/IP protocol stack of the pre-message is 4S, at this moment, when the slave clock receives the pre-message, the timestamp of the slave clock TCP/IP protocol stack, namely the second timestamp, is 12:05, at this moment, the timestamp of the bottommost layer of the master clock TCP/IP protocol stack is 12:04, the first timestamp 12:00, the second timestamp 12:05 and the network delay 4S are respectively substituted into the formula to obtain t 12:04, and the second timestamp is corrected to be 12: 04.

therefore, the embodiment of the invention corrects the time of the slave clock TCP/IP protocol stack according to the expression above by using the first time stamp, the second time stamp and the network delay.

Monitoring the target file T which is in the allowed browsing state at present, and switching the state of the T into the browsing prohibition state after monitoring that the T meets the preset locking condition. The time of the slave clock TCP/IP protocol stack can be corrected quickly and accurately.

therefore, in the method provided by the embodiment of the invention, the forecast message which is sent by the master clock and does not carry data is received, the first timestamp stored in the pre-message and the network delay from the master clock TCP/IP protocol stack to the slave clock TCP/IP protocol stack are obtained from the forecast message, and the time of the slave clock TCP/IP protocol stack is corrected by using the first timestamp, the second timestamp and the network delay. Compared with the prior art, the embodiment of the invention considers the problem of asymmetry of transmission delay among base stations, and records the network delay from a master clock TCP/IP protocol stack to a slave clock TCP/IP protocol stack by using the forecast message, thereby improving the time synchronization precision among the base stations.

based on the above description, a detailed embodiment is now provided, as shown in fig. 5, specifically:

In the IEEE1588 time synchronization system based on physical layer timestamp and Pre-message, when a master clock is to send a data packet to a slave clock, the master clock in the IEEE1588 system preferentially sends a Pre-message Pre _ sync (not carrying data information), a Pre _ sync message data link layer is generated in the form of ethernet, then hardware-assisted timestamp is performed in the physical layer, and a message departure time d1 is recorded, because the hardware timestamp is in the physical layer, a delay generated in a message processing process in a protocol stack has no influence on time synchronization, and then the delay is sent in an uplink (i.e. a one-way real arrow in the figure) of the communication system, passes through a plurality of links and a plurality of network switches, then is received in the physical layer of the slave clock, and is stamped with a timestamp d2, so that a total delay d in the uplink in the IEEE1588 system can be obtained_msthe total delay in the uplink is stored in the correction field of the message d2-d 1.

After the slave clock receives the forecast message Pre _ sync sent from the master clock, it will also generate the forecast message Pre _ delay and send it back to the master clock. Before the Pre-message Pre _ delay leaves the slave clock, the Pre-message is stamped with a timestamp d3 at the physical layer of the slave clock, passes through the downlink of the system, namely a single-direction dotted arrow in fig. 5, is received by the master clock, and is stamped with a timestamp d4 at the physical layer, so that the total time delay d from the slave clock to the downlink of the master clock is obtained_smSimilarly, the total delay of the master clock downlink is stored in the message's modified field, d4-d 3.

Then, the master clock sends a sync message carrying data information to the slave clock, and the master clock sends the sync message to the slave clockA physical layer of the clock stamps a time stamp t1, then the time stamp is sent to the slave clock through an uplink, and a physical layer of the slave clock stamps a time stamp t2 again, wherein the t2 time stamp is carried by a Follow _ up message and is combined with the total delay d of the uplink in a Pre _ Sync message correction domain of a previous Pre-message_msaccording to the formula d_mst2-t1-offset1, the time offset, offset1, from the master clock to the slave clock is obtained: offset 1-t 2-t1-d_ms。

The master-slave time offset is written into the correction field. After receiving a sync message and a Follow _ up message sent by a master clock, the slave clock sends a Delay _ req message with a timestamp of t3 on a PHY layer to the master clock, then sends the Delay _ req message to the master clock through a downlink of a network system, the master clock receives the Delay _ req message and stamps a timestamp of t4 on a PHY (Physical layer), after receiving the Delay _ req message, the master clock sends the Delay _ req message to the slave clock, and then the Delay _ req message and the d _ req message in a Pre _ Delay message are combined_smAccording to the formula d_smT4-t3+ offset2, the time offset, offset2, from clock to master clock can be found: offset2 ═ d_sm-t3-t4。

The slave clock is time-corrected by using the obtained master-slave time offset1 and slave-master clock offset2, so that high-precision time synchronization of the master clock and the slave clock can be realized, and nanosecond-level time synchronization of an IEEE1588 protocol is realized.

Based on the description of the above embodiments, the embodiments of the present invention further provide experimental simulation and result analysis, specifically:

The OPNET Modeler is network simulation software, and has the characteristics of a hierarchical simulation method, a simple and concise method, a finite state machine, support of various protocol programming, point-to-point link, imaging, dynamic simulation and the like, so that the OPNET Modeler has wide acceptance in the fields of communication, national defense and computer networks.

an IEEE1588 protocol simulator is designed based on OPNET Modelr discrete time simulation, and the simulation of time synchronization of a master clock and a slave clock in a communication network can be realized under the condition of background traffic. The simulator needs hardware assistance, namely, the combination of the timestamp on the physical layer, the network switch and the background flow generator which are provided by the embodiment of the invention are all standard node models, the switch can simulate the delay of a message passing through the switch, the background flow generator intermittently fixes the message, and a link model between the modules is a system standard model and can simulate the delay generated by the transmission length.

In order to verify the scheme provided by the embodiment of the invention, a network model, a node model and a process model can be respectively established in the modeling process according to a three-layer modeling mechanism of an OPNET Modeler.

the specific network model configuration is shown in FIG. 6 below:

In fig. 6, the master clock generates a clock signal at a fixed period and provides time synchronization correction for the slave clocks in the IEEE1588 network. The slave clock exchanges synchronous messages with the master clock in the network to calculate network delay and time offset, and keeps synchronization with the master clock by continuously adjusting the clock of the slave clock. The synchronous message passes through two network switches and a background flow generator, and can send a fixed-length message with a fixed synchronous gap.

corresponding to the correction method for realizing time synchronization provided above, an embodiment of the present invention provides a correction apparatus for realizing time synchronization.

Referring to fig. 7, fig. 7 is a correction apparatus for implementing time synchronization according to an embodiment of the present invention, applied to a slave clock, where the apparatus includes:

a receiving module 201, configured to receive a pre-message that is sent by a master clock and does not carry data;

A time obtaining module 202, configured to obtain, from the precursor message, a first timestamp stored in the precursor message and a network delay from a master clock TCP/IP protocol stack to a slave clock TCP/IP protocol stack, where the first timestamp is: when the master clock sends a pre-message, the time stamp of the TCP/IP protocol stack of the master clock;

A delay correction module 203, configured to correct the time of the slave clock TCP/IP protocol stack by using the first timestamp, the second timestamp, and the network delay, where the second timestamp is: and when the slave clock receives the pre-message, the slave clock is the time stamp of the TCP/IP protocol stack.

Optionally, the first timestamp may be: the timestamp of the lowest physical layer in the master clock TCP/IP protocol stack, and the second timestamp may be: and the time stamp of the lowest physical layer in the slave clock TCP/IP protocol stack.

Optionally, the delay modification module 203 may include:

the time delay correction submodule is used for correcting the time of the main clock TCP/IP protocol stack according to the following expression by utilizing the first time stamp, the second time stamp and the network time delay;

The expression is: t is t₂-t_offset，t_offset＝t₂-t₁-d；

Wherein, t₁Is a first time stamp, t₂is the first timestamp, d is the network delay, t_offsetAnd t is the time deviation from the time of the slave clock TCP/IP protocol stack to the time of the master clock TCP/IP protocol stack, and the corrected time of the slave clock TCP/IP protocol stack.

Optionally, the pre-packet obtains and stores the network delay from the master clock TCP/IP protocol stack to the slave clock TCP/IP protocol stack according to a weighted average algorithm, a delay decomposition algorithm, or a transparent clock.

Therefore, when the device provided by the embodiment of the invention receives the forecast message which is sent by the master clock and does not carry data, the first timestamp stored in the pre-message and the network delay from the master clock TCP/IP protocol stack to the slave clock TCP/IP protocol stack are obtained from the forecast message, and the time of the slave clock TCP/IP protocol stack is corrected by using the first timestamp, the second timestamp and the network delay. Compared with the prior art, the embodiment of the invention considers the problem of asymmetry of transmission delay among base stations, and records the network delay from a master clock TCP/IP protocol stack to a slave clock TCP/IP protocol stack by using the forecast message, thereby improving the time synchronization precision among the base stations.

An embodiment of the present invention further provides an electronic device, as shown in fig. 8, including a processor 301, a communication interface 302, a memory 303, and a communication bus 304, where the processor 301, the communication interface 302, and the memory 303 complete mutual communication through the communication bus 304,

A memory 303 for storing a computer program;

the processor 301 is configured to implement a correction method for implementing time synchronization according to an embodiment of the present invention when executing the program stored in the memory 303.

Specifically, the correction method for implementing time synchronization includes:

receiving a pre-message which is sent by a main clock and does not carry data;

obtaining a first timestamp stored in the pre-message and network delay from a master clock TCP/IP protocol stack to a slave clock TCP/IP protocol stack from the forecast message, wherein the first timestamp is as follows: when the master clock sends a pre-message, the time stamp of the TCP/IP protocol stack of the master clock;

Correcting the time of the slave clock TCP/IP protocol stack by using the first timestamp, the second timestamp and the network delay, wherein the second timestamp is as follows: and when the slave clock receives the pre-message, the slave clock is the time stamp of the TCP/IP protocol stack.

Therefore, when the electronic device provided by the embodiment is executed, the first timestamp stored in the pre-message and the network delay from the master clock TCP/IP protocol stack to the slave clock TCP/IP protocol stack are obtained from the forecast message by receiving the forecast message which is sent by the master clock and does not carry data, and the time of the slave clock TCP/IP protocol stack is corrected by using the first timestamp, the second timestamp and the network delay. Compared with the prior art, the embodiment of the invention considers the problem of asymmetry of transmission delay among base stations, and records the network delay from a master clock TCP/IP protocol stack to a slave clock TCP/IP protocol stack by using the forecast message, thereby improving the time synchronization precision among the base stations.

the implementation of the related content delay correction method is the same as the delay correction method provided in the foregoing method embodiment, and is not described here again.

the communication bus mentioned in the electronic device may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown, but this does not mean that there is only one bus or one type of bus.

The communication interface is used for communication between the electronic equipment and other equipment.

The Memory may include a Random Access Memory (RAM) or a Non-Volatile Memory (NVM), such as at least one disk Memory. Optionally, the memory may also be at least one memory device located remotely from the processor.

The Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component.

In another embodiment of the present invention, a computer-readable storage medium is further provided, which stores instructions that, when executed on a computer, cause the computer to execute the correction method for time synchronization described in any of the above embodiments.

In yet another aspect of the present invention, there is also provided a computer program product containing instructions which, when run on a computer, cause the computer to perform any of the above-described correction methods for achieving time synchronization.

in the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the invention to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website site, computer, server, or data center to another website site, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.

it is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

the embodiments in the present disclosure are described in a related manner, and the same and similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the method, apparatus, electronic device and computer-readable storage medium embodiments, the description is relatively simple because they are substantially similar to the method embodiments, and reference may be made to some descriptions of the method embodiments for relevant points.

the above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.