阅读说明：本技术 用于拼接器的同步装置、拼接处理系统 (synchronization device for splicer and splicing processing system ) 是由 王洋 董学明 刘雨 姚维久 董志松 王雅超 李厚鹏 于 2019-07-17 设计创作，主要内容包括：本发明涉及拼接器技术领域,具体涉及一种用于拼接器的同步装置、拼接处理系统。本发明的同步装置包括：视频信号解析模块、控制模块、同步信号处理模块和时钟处理模块。视频信号解析模块对视频信号进行解析得到第一像素时钟和同步信号,对第一像素时钟进行二分频得到第二像素时钟；控制模块根据第二像素时钟查表得到对应的倍频数值和分频数值；时钟处理模块根据第二像素时钟、倍频数值和分频数值,计算第三像素时钟；同步信号处理模块将第三像素时钟作为同步时钟,并向一个或多个拼接器发送同步指令,以使同步装置与拼接器实现同步运行；本发明解决了当视频分辨率变化时、当刷新频率存在误差时,拼接器输入与输出的同步问题,同时实现了设备扩展。(the invention relates to the technical field of splicers, in particular to a synchronization device and a splicing processing system for splicers. The synchronization device of the present invention includes: the device comprises a video signal analysis module, a control module, a synchronous signal processing module and a clock processing module. The video signal analysis module analyzes the video signal to obtain a first pixel clock and a synchronous signal, and performs frequency division on the first pixel clock to obtain a second pixel clock; the control module looks up a table according to the second pixel clock to obtain a corresponding frequency multiplication value and a corresponding frequency division value; the clock processing module calculates a third pixel clock according to the second pixel clock, the frequency multiplication value and the frequency division value; the synchronous signal processing module takes the third pixel clock as a synchronous clock and sends a synchronous instruction to one or more splicers so as to enable the synchronous device and the splicers to synchronously run; the invention solves the problem of synchronization of the input and the output of the splicer when the video resolution is changed and the refreshing frequency has errors, and simultaneously realizes the equipment expansion.)

1. A synchronization device for a splicer, the synchronization device comprising: the device comprises a video signal analysis module, a control module, a synchronous signal processing module and a clock processing module;

The video signal parsing module is configured to: receiving a video signal, and analyzing the video signal to obtain a first pixel clock and a synchronous signal; performing frequency division on the first pixel clock to obtain a second pixel clock; transmitting the second pixel clock to the control module and transmitting the synchronization signal to the synchronization signal processing module;

The control module is configured to: obtaining a frequency multiplication numerical value and a frequency division numerical value corresponding to the second pixel clock according to the second pixel clock and a preset pixel clock-frequency multiplication numerical value-frequency division numerical value relation table; sending the second pixel clock, the frequency multiplication value and the frequency division value to the clock processing module;

The clock processing module is configured to: calculating a product of the second pixel clock and the frequency multiplication value, and dividing the product by the frequency division value to obtain a third pixel clock; sending the third pixel clock, the frequency multiplication value and the frequency division value to the synchronous signal processing module;

the synchronization signal processing module is configured to: determining that the working mode is an external video mode, taking the third pixel clock as a synchronous clock, and sending a synchronous instruction to one or more splicers to enable the synchronous device and the splicers to synchronously run;

Wherein the content of the first and second substances,

the synchronization instructions include: the synchronous clock, the synchronous signal, the frequency multiplication value and the frequency division value.

2. The synchronization device for splicers according to claim 1,

The synchronization device further comprises a crystal oscillator for generating a fourth pixel clock;

the control module is further configured to: sending a working mode control instruction to the synchronous signal processing module; wherein the operating modes include: an external video mode or a local mode;

the synchronization signal processing module is further configured to: determining the working mode to be an external video mode or a local mode according to the working mode control instruction; and when the working mode is a local mode, selecting the fourth pixel clock as the synchronous clock, and enabling the frequency multiplication value and the frequency division value to be zero.

3. The synchronization device for splicers according to claim 2,

the operating mode further includes: a cascade mode;

the synchronization signal processing module is further configured to: when the working mode is a local mode or an external video mode, sending the synchronization instruction to one or more other synchronization devices to realize the cascade connection of the plurality of synchronization devices; and when the working mode is a cascade mode, receiving the synchronous instruction sent by the other synchronous device, and sending the received synchronous instruction to one or more splicers.

4. the synchronization device for splicers according to claim 3,

the operating mode further includes: an intelligent mode;

the synchronization signal processing module is further configured to: and when the working mode is the intelligent mode, sequentially detecting whether the clock corresponding to each working mode exists according to a preset sequence, selecting the current working mode according to the detection result, and further selecting the corresponding synchronous clock.

5. The synchronization apparatus for a splicer according to any one of claims 1-4, wherein the video signal parsing module is further configured to: outputting the video signal to the splicer using a loop-out interface.

6. The synchronization device for splicers according to any of claims 1-5, wherein the control module is further configured to: receiving a management instruction sent by the splicer, and sending the management instruction to the synchronous signal processing module;

Wherein the content of the first and second substances,

The management instruction comprises: parameter setting instructions and/or status query instructions.

7. The synchronization device for splicers according to any one of claims 1 to 5, wherein the synchronization signal comprises: a field sync and/or a line sync and/or a valid data signal and/or a parity field signal.

8. the synchronization device for splicers according to any one of claims 6,

The synchronization signal processing module is further configured to: sending corresponding state information to the control module according to the state query instruction;

the control module is further configured to: and receiving the state information and sending the state information to the splicer.

9. a stitching processing system, comprising: the synchronization device for splicers of any one of claims 1-8, and one or more splicers;

the splicer is configured to:

Receiving the synchronization instruction sent by the synchronization device;

when the frequency division value and the frequency multiplication value are not zero, multiplying the synchronous clock by 2, multiplying the synchronous clock by the frequency division value to obtain a product, and dividing the product by the frequency multiplication value to obtain a recovery value of the first pixel clock; using the recovery value of the first pixel clock as the pixel clock of the splicer;

When the frequency division value and the frequency multiplication value are both zero, taking the synchronous clock as a pixel clock of the splicer;

and synchronizing a plurality of output ports of the splicer to the same frame of image to start outputting by using the synchronization signal.

10. a splice processing system, the system comprising: a plurality of the splice processing systems of claim 9;

The synchronization device in one of the splicing processing systems is used as a master device, and the synchronization devices in the other splicing processing systems are used as slave devices;

the working mode of the master device is set to a local mode, an external video mode or an intelligent mode, and the working mode of the slave device is set to a cascade mode.

Technical Field

The invention relates to the technical field of splicers, in particular to a synchronization device and a splicing processing system for splicers.

background

the main function of the splicer is to divide a video signal into a plurality of display units, output the divided display unit signals to a plurality of display screens, and splice the display screens to form a complete image.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a synchronization device and a splicing processing system for a splicer, which solve the problem of synchronization between an input signal source and the output of the splicer and realize the expansion of equipment.

In one aspect of the present invention, a synchronization device for a splicer is provided, the synchronization device comprising: the device comprises a video signal analysis module, a control module, a synchronous signal processing module and a clock processing module;

the video signal parsing module is configured to: receiving a video signal, and analyzing the video signal to obtain a first pixel clock and a synchronous signal; performing frequency division on the first pixel clock to obtain a second pixel clock; transmitting the second pixel clock to the control module and transmitting the synchronization signal to the synchronization signal processing module;

the control module is configured to: obtaining a frequency multiplication numerical value and a frequency division numerical value corresponding to the second pixel clock according to the second pixel clock and a preset pixel clock-frequency multiplication numerical value-frequency division numerical value relation table; sending the second pixel clock, the frequency multiplication value and the frequency division value to the clock processing module;

The clock processing module is configured to: calculating a product of the second pixel clock and the frequency multiplication value, and dividing the product by the frequency division value to obtain a third pixel clock; sending the third pixel clock, the frequency multiplication value and the frequency division value to the synchronous signal processing module;

The synchronization signal processing module is configured to: determining that the working mode is an external video mode, taking the third pixel clock as a synchronous clock, and sending a synchronous instruction to one or more splicers to enable the synchronous device and the splicers to synchronously run;

wherein the content of the first and second substances,

The synchronization instructions include: the synchronous clock, the synchronous signal, the frequency multiplication value and the frequency division value.

preferably, the synchronization device further comprises a crystal oscillator for generating a fourth pixel clock;

the control module is further configured to: sending a working mode control instruction to the synchronous signal processing module; wherein the operating modes include: an external video mode or a local mode;

The synchronization signal processing module is further configured to: determining the working mode to be an external video mode or a local mode according to the working mode control instruction; and when the working mode is a local mode, selecting the fourth pixel clock as the synchronous clock, and enabling the frequency multiplication value and the frequency division value to be zero.

Preferably, the operation mode further includes: a cascade mode;

The synchronization signal processing module is further configured to: when the working mode is a local mode or an external video mode, sending the synchronization instruction to one or more other synchronization devices to realize the cascade connection of the plurality of synchronization devices; and when the working mode is a cascade mode, receiving the synchronous instruction sent by the other synchronous device, and sending the received synchronous instruction to one or more splicers.

preferably, the operation mode further includes: an intelligent mode;

The synchronization signal processing module is further configured to: and when the working mode is the intelligent mode, sequentially detecting whether the clock corresponding to each working mode exists according to a preset sequence, selecting the current working mode according to the detection result, and further selecting the corresponding synchronous clock.

Preferably, the video signal parsing module is further configured to: outputting the video signal to the splicer using a loop-out interface.

preferably, the control module is further configured to: receiving a management instruction sent by the splicer, and sending the management instruction to the synchronous signal processing module;

wherein the content of the first and second substances,

the management instruction comprises: parameter setting instructions and/or status query instructions.

Preferably, the synchronization signal includes: a field sync and/or a line sync and/or a valid data signal and/or a parity field signal.

preferably, the synchronization signal processing module is further configured to: sending corresponding state information to the control module according to the state query instruction;

The control module is further configured to: and receiving the state information and sending the state information to the splicer.

in the second aspect of the present invention, a splicing processing system is further provided, where the splicing processing system includes: the above-described synchronization device for splices, and one or more splices;

the splicer is configured to:

Receiving the synchronization instruction sent by the synchronization device;

When the frequency division value and the frequency multiplication value are not zero, multiplying the synchronous clock by 2, multiplying the synchronous clock by the frequency division value to obtain a product, and dividing the product by the frequency multiplication value to obtain a recovery value of the first pixel clock; using the recovery value of the first pixel clock as the pixel clock of the splicer;

when the frequency division value and the frequency multiplication value are both zero, taking the synchronous clock as a pixel clock of the splicer;

And synchronizing a plurality of output ports of the splicer to the same frame of image to start outputting by using the synchronization signal.

in a third aspect of the present invention, another splicing processing system is further provided, where the system includes: a plurality of the above described stitching processing systems;

the synchronization device in one of the splicing processing systems is used as a master device, and the synchronization devices in the other splicing processing systems are used as slave devices;

the working mode of the master device is set to a local mode, an external video mode or an intelligent mode, and the working mode of the slave device is set to a cascade mode.

Compared with the closest prior art, the invention has the following beneficial effects:

(1) the problem of when the resolution ratio of the input signal source of splicer changes, unable synchronization between input and the output is solved: in the invention, the video resolution of an input signal source is sent to the splicer by the synchronization device, so that the splicer can adjust the resolution of an output video in real time;

(2) The problem of when having the error in the input signal refresh rate of splicer, input and output are asynchronous is solved: when there is an error in the refresh rate of the input signal, such as setting the video card output to [email protected], the refresh rate actually output by the video card may be 59.999hz or 60.001hz, not exactly 60 hz. In this case, errors are accumulated in the prior art, and when more than one frame of image, it is observed that the output is out of synchronization with the input image. In the invention, when the synchronous device works in an external video mode, the output of the splicer and the input signal source adopt the same pixel clock source, so the problem does not exist;

(3) the problem that the equipment can not be expanded is solved: in the invention, a plurality of synchronizing devices can be applied in a cascade way, and each synchronizing device can also send a synchronizing instruction to a plurality of splicers, so that a splicing processing system can be well expanded;

(4) the problem that the synchronous signals cannot be transmitted in a long distance is solved: when the synchronization device operates in the external video mode, the pixel clock of the video source obtained by parsing is usually high and cannot be transmitted over a long distance, such as 1920 × [email protected] resolution, and the pixel clock is 148.5 Mhz. In the invention, the low-frequency clock is transmitted after the pixel clock obtained by analysis is subjected to frequency multiplication and frequency division, so that the pixel clock can be transmitted in a long distance;

(5) the problem that the synchronization device cannot be managed is solved: the invention can manage the synchronous device by sending the management instruction through the splicer.

Drawings

FIG. 1 is a schematic diagram of the main components of an embodiment of the synchronization device for splicers of the present invention;

FIG. 2 is a schematic diagram of the main components of an embodiment of a stitching processing system of the present invention;

Fig. 3 is a schematic view of the main structure of another embodiment of the splicing processing system of the present invention.

Detailed Description

Preferred embodiments of the present invention are described below with reference to the accompanying drawings. It should be understood by those skilled in the art that these embodiments are only for explaining the technical principle of the present invention, and are not intended to limit the scope of the present invention.

it should be noted that the terms "first", "second" and "third" in the description of the present invention are used for convenience of description only and do not indicate or imply relative importance of the devices, elements or parameters, and therefore should not be construed as limiting the present invention.

Fig. 1 is a main configuration diagram of an embodiment of a synchronization device for splicers of the present invention. As shown in fig. 1, the synchronization device 100 of the present embodiment includes: a video signal parsing module 110, a control module 120, a synchronous signal processing module 130 and a clock processing module 140.

Wherein the video signal parsing module 110 is configured to: receiving a video signal, and analyzing the video signal to obtain a first pixel clock CLK1 and a synchronous signal VS; dividing the first pixel clock CLK1 by two to obtain a second pixel clock CLK 2; the second pixel clock CLK2 is transmitted to the control block 120, and the sync signal VS is transmitted to the sync signal processing block 130; the control module 120 is configured to: obtaining a frequency multiplication value M and a frequency division value N corresponding to the second pixel clock CLK2 according to the second pixel clock CLK2 and a preset pixel clock-frequency multiplication value-frequency division value relation table, and sending the second pixel clock CLK2, the frequency multiplication value M and the frequency division value N to the clock processing module 140; the clock processing module 140 is configured to: calculating a product of the second pixel clock CLK2 and the multiplied value M, and dividing the product by the divided value N to obtain a third pixel clock CLK 3; sending the third pixel clock CLK3, the frequency multiplication value M, and the frequency division value N to the synchronization signal processing module 130; the synchronization signal processing module 130 is configured to: determining the operation mode as the external video mode, using the third pixel clock CLK3 as the synchronous clock CLK, and sending a synchronous instruction to one or more splicers 200 to enable the synchronous device 100 and the splicers 200 to operate synchronously.

In this embodiment, the synchronization instruction includes: a synchronous clock CLK, a synchronous signal VS, a multiplication value M and a division value N.

in this embodiment, the maximum resolution supported by the synchronization apparatus is [email protected] (i.e. 4K), and if a picture with 4K resolution is to be played, the pixel clock needs to be 297Mhz, so that the input range of the clock processing module 140 is 25Mhz to 300Mhz, which can meet the current resolution requirement. As shown in table 1 below, the values of M and N (columns 3-4 from the left) may be obtained in the control block 120 by table lookup according to the range of the second pixel clock CLK2 (columns 1-2 from the left); after the CLK2, M, N is inputted to the clock processing module 140, the second pixel clock CLK2 is first multiplied by M to a larger value and then divided by N to obtain an output clock, i.e., the third pixel clock CLK3 (from the left, columns 5-6) is around 25 Mhz.

table 1:

The method for calculating the third pixel clock in the clock processing module 140 is shown in formula (1):

since the video signal analyzer 110 divides the first pixel clock CLK1 by two to obtain the second pixel clock CLK2, it can be seen that the relationship between CLK3 and CLK1 is shown in formula (2):

As shown in fig. 1, the synchronization signal processing module 130 may have a plurality of synchronization outputs for outputting synchronization commands to a plurality of splicers 200. In the splicer 200, the first pixel clock CLK1 is recovered according to the CLK3 and M, N values and the relationship therebetween, as shown in equation (3):

In this embodiment, a crystal oscillator 150 may be further disposed inside the synchronization device, and the crystal oscillator is configured to generate the fourth pixel clock CLK4 (e.g., 25 MHz); the control module 120 may be further configured to: sending an operation mode control instruction to the synchronization signal processing module 130, wherein the operation mode includes an external video mode or a local mode; the synchronization signal processing module 130 may be further configured to: determining the working mode to be an external video mode or a local mode according to the working mode control instruction; when the working mode is the local mode, selecting a fourth pixel clock CLK4 as a synchronous clock CLK, and enabling the frequency multiplication value and the frequency division value to be zero; when the operation mode is the external video mode, the third pixel clock CLK3 is selected as the synchronous clock CLK, and the frequency multiplication value M and the frequency division value N are values obtained by the control module 120 through table lookup.

in this embodiment, the working mode may further include: a cascade mode. The synchronization signal processing module 130 may be further configured to: when the working mode is the local mode or the external video mode, sending a synchronization instruction to one or more other synchronization devices 100 to realize the cascade connection of the plurality of synchronization devices 100; when the operation mode is the cascade mode, the synchronization instruction transmitted from another synchronization apparatus 100 is received, and the received synchronization instruction is transmitted to one or more splicers 200.

in this embodiment, the working mode may further include: and (4) an intelligent mode. The synchronization signal processing module 130 may be further configured to: and when the working mode is the intelligent mode, sequentially detecting whether the clock corresponding to each working mode exists according to a preset sequence, selecting the current working mode according to the detection result, and further selecting the corresponding synchronous clock. For example, if the predetermined sequence is: a local mode, an external video mode and a cascade mode, and then the clocks corresponding to the three working modes are detected in sequence, namely (1) the CLK4 generated by a crystal oscillator inside the synchronization device; (2) CLK3 sent by the clock processing module; (3) CLK received from the sync input port. If the (1) th clock exists, selecting the (1) th clock as a synchronous clock; if the (1) th clock is found to be absent but the (2) th clock is present, selecting the (2) th clock as a synchronous clock; if the first two are found to be absent but the (3) th is present, the (3) th is selected as the synchronous clock.

in this embodiment, the video signal parsing module 110 may be further configured to: the video signal is output to the splicer 200 by using the loop-out interface, thereby avoiding the reduction of the video signal source interface caused by accessing the synchronization device of the invention.

In this embodiment, the control module 120 may be further configured to: receiving a management instruction sent by the splicer 200, and sending the management instruction to the synchronization signal processing module 130; the synchronization signal processing module 130 is further configured to: sending corresponding state information to the control module according to the state query instruction; the control module is further configured to: and receiving the state information and sending the state information to the splicer. Wherein the management instructions include: parameter setting instructions and/or status query instructions. The parameter setting instruction includes: setting a working mode of the synchronization device, and setting an output resolution parameter when the working mode is a local mode; the state query instruction comprises: the working mode of the synchronizer, which synchronous output port of the synchronizer is connected, resolution parameters of input and output of the synchronizer, a clock frequency multiplication value, a frequency division value and the like.

in this embodiment, the synchronization signal includes: a field sync and/or a line sync and/or a valid data signal and/or a parity field signal. These signals are analyzed by the video signal analyzing module 110, and field synchronization or line synchronization may be used for synchronization. The odd and even field signal is used when the signal source is an interlaced signal, indicating that it is an odd or even field of a frame of image at present.

In practical application, an RJ45 interface and a network cable can be adopted, the RJ45 has 8 pins, 2 of the pins are used for transmitting management instructions and state information according to an RS485 protocol, 1 pin transmits a synchronous signal, and 1 pin transmits a clock signal. The video signal analysis module 110 may be implemented by an ITE6802 chip, the control module 120 may be implemented by an STM32 chip, the synchronization signal processing module 130 may be implemented by an FPGA chip, and the clock processing module 140 may be implemented by an IDT5901 chip. Here, examples are given, and other transmission lines and chips may be used.

The synchronization device can realize the output synchronization of a plurality of output signals and input signals of the splicer. When the resolution of the input video signal source is changed, the synchronizer informs the new resolution to the splicer, and the splicer can automatically change the output resolution to be the same as the resolution of the input video signal source, so that the output and signal source are kept synchronous.

Fig. 2 is a schematic diagram of a main configuration of an embodiment of a splicing processing system of the present invention. As shown in fig. 2, the splicing processing system of the present embodiment includes: the synchronization device 100 for splices described above, and one or more splices 200.

Wherein the splicer 200 is configured to: receiving a synchronous instruction sent by a synchronous device (the synchronous instruction comprises a synchronous clock CLK, a synchronous signal VS, a frequency multiplication numerical value M and a frequency division numerical value N); judging whether the frequency division value N and the frequency multiplication value M are zero, multiplying the synchronous clock CLK by 2 when the frequency division value N and the frequency multiplication value M are not zero, multiplying the product by the frequency division value N to obtain a product, dividing the product by the frequency multiplication value M to obtain a recovery value of the first pixel clock CLK1, and using the recovery value of the first pixel clock CLK1 as a pixel clock of the splicer 200; when the frequency division value and the frequency multiplication value are both zero, the synchronous clock CLK is used as the pixel clock of the splicer 200; and synchronizing a plurality of output ports of the splicer to the same frame of image starting output by using a synchronizing signal VS. The splicer receives m video input signals from the main player 300 and controls n video outputs according to the synchronization command from the synchronizer.

Fig. 3 is a schematic view of the main structure of another embodiment of the splicing processing system of the present invention. As shown in fig. 3, the splicing processing system of the present embodiment includes: a plurality of stitching processing systems as shown in figure 2.

The synchronization device 100 in one of the splicing processing systems serves as a master device, and the synchronization devices 100 in the other splicing processing systems 1 serve as slave devices; the working mode of the master device is set to a local mode, an external video mode or an intelligent mode, and the working mode of the slave device is set to a cascade mode. In fig. 3, the first upper synchronization device is a master device, and the other synchronization devices are slave devices. Because each synchronizer can provide synchronous instructions for one or more splicers, synchronous control of more splicers can be realized through the cascade connection of a plurality of synchronizers.

Those of skill in the art will appreciate that the method steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, computer software, or combinations of both, and that the components and steps of the examples have been described above generally in terms of their functionality in order to clearly illustrate the interchangeability of electronic hardware and software. Whether such functionality is implemented as electronic hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

so far, the technical solutions of the present invention have been described in connection with the preferred embodiments shown in the drawings, but it is easily understood by those skilled in the art that the scope of the present invention is obviously not limited to these specific embodiments. Equivalent changes or substitutions of related technical features can be made by those skilled in the art without departing from the principle of the invention, and the technical scheme after the changes or substitutions can fall into the protection scope of the invention.