阅读说明：本技术 利用晶体硅对太阳能电池光接收表面进行钝化 (Passivation of solar cell light-receiving surface using crystalline silicon ) 是由 迈克尔·C·约翰逊 基兰·马克·特雷西 普林斯·卡尔米·托马达 戴维·D·史密斯 林承笵 于 2015-06-25 设计创作，主要内容包括：本发明描述了利用晶体硅将太阳能电池的光接收表面钝化的方法以及所得的太阳能电池。在一个示例中,太阳能电池包括具有光接收表面的硅基板。在所述硅基板的所述光接收表面上方设置有本征硅层。在所述本征硅层上设置有N型硅层。所述本征硅层和所述N型硅层中的一者或两者是微晶或多晶硅层。在另一个示例中,太阳能电池包括具有光接收表面的硅基板。在所述硅基板的所述光接收表面上设置有钝化介电层。在所述钝化介电层上设置有N型微晶或多晶硅层。(Methods of passivating a light-receiving surface of a solar cell with crystalline silicon and the resulting solar cell are described. In one example, a solar cell includes a silicon substrate having a light-receiving surface. An intrinsic silicon layer is disposed over the light-receiving surface of the silicon substrate. An N-type silicon layer is disposed on the intrinsic silicon layer. One or both of the intrinsic silicon layer and the N-type silicon layer is a microcrystalline or polycrystalline silicon layer. In another example, a solar cell includes a silicon substrate having a light-receiving surface. A passivating dielectric layer is disposed on the light-receiving surface of the silicon substrate. And an N-type microcrystalline or polycrystalline silicon layer is arranged on the passivation dielectric layer.)

1. A solar cell, comprising:

a silicon substrate having a light-receiving surface;

a passivation dielectric layer of a passivation oxide layer disposed on the light-receiving surface of the silicon substrate;

an intrinsic silicon layer disposed on the passivation dielectric layer, the intrinsic silicon layer having a thickness in a range of 1 to 5 nanometers; and

an N-type silicon layer disposed on the intrinsic silicon layer, the N-type silicon layer having a thickness in a range of 1 to 20 nanometers, wherein both the intrinsic silicon layer and the N-type silicon layer are microcrystalline or polycrystalline silicon layers.

2. The solar cell of claim 1, wherein the N-type silicon layer is an N-type microcrystalline or polycrystalline silicon layer comprising particles embedded in an amorphous silicon matrix and having no long range order.

3. The solar cell of claim 2, wherein the NThe concentration of N-type dopant in the type microcrystalline or polycrystalline silicon layer is 1E17-1E20 atoms/cm³Within the range of (1).

4. The solar cell of claim 3, wherein the passivating dielectric layer is silicon dioxide (SiO) having a thickness in a range of 10 to 200 angstroms₂) And (3) a layer.

5. The solar cell of claim 1, further comprising:

an anti-reflective coating (ARC) disposed on the N-type silicon layer.

6. The solar cell of claim 1, wherein the light-receiving surface has a textured topography, and wherein both the intrinsic silicon layer and the N-type silicon layer are conformal to the textured topography of the light-receiving surface.

7. The solar cell of claim 1, wherein the substrate further comprises a back surface opposite the light-receiving surface, the solar cell further comprising:

a plurality of alternating N-type and P-type semiconductor regions at or above the back surface of the substrate; and

a conductive contact structure electrically connected to the plurality of alternating N-type and P-type semiconductor regions.

8. The solar cell of claim 5, wherein the antireflective coating comprises silicon nitride.

9. A method of fabricating a solar cell, the method comprising:

forming an intrinsic silicon layer (110) over a light-receiving surface (102) of a silicon substrate (100); and

an N-type silicon layer (112) is formed on the intrinsic silicon layer (110), wherein one or both of the intrinsic silicon layer (110) and the N-type silicon layer (112) is a microcrystalline or polycrystalline silicon layer.

10. The method of claim 9, wherein the N-type silicon layer (112) is an N-type microcrystalline or polycrystalline silicon layer, and forming the N-type microcrystalline or polycrystalline silicon layer comprises: depositing an N-type amorphous silicon layer; and then phase-converting the N-type amorphous silicon layer into the N-type microcrystalline or polycrystalline silicon layer.

11. The method of claim 9, wherein the N-type silicon layer (112) is an N-type microcrystalline or polycrystalline silicon layer, and forming the N-type microcrystalline or polycrystalline silicon layer comprises: and depositing the N-type microcrystalline or polycrystalline silicon layer.

12. The method of claim 9, further comprising: an anti-reflective coating (ARC) layer is formed on the N-type silicon layer.

13. The method of claim 9, further comprising:

forming a plurality of alternating N-type and P-type semiconductor regions at or above a back surface of the substrate opposite the light-receiving surface; and

forming a conductive contact structure electrically connected to the plurality of alternating N-type and P-type semiconductor regions.

Technical Field

Embodiments of the present disclosure relate to the field of renewable energy, and in particular, to methods of passivating a light-receiving surface of a solar cell with crystalline silicon and the resulting solar cell.

Background

Photovoltaic cells, often referred to as solar cells, are well known devices for directly converting solar radiation into electrical energy. Generally, solar cells are fabricated on a semiconductor wafer or substrate using semiconductor processing techniques to form a p-n junction near the surface of the substrate. Solar radiation impinging on the substrate surface and into the substrate forms electron and hole pairs in the bulk of the substrate. The electron and hole pairs migrate to the p-doped and n-doped regions in the substrate, thereby creating a voltage difference between the doped regions. The doped regions are connected to conductive regions on the solar cell to conduct current from the cell to an external circuit coupled thereto.

Efficiency is an important characteristic of solar cells, as it is directly related to the power generation capacity of the solar cell. Also, the efficiency of fabricating solar cells is directly related to the cost effectiveness of such solar cells. Therefore, techniques to improve the efficiency of solar cells or techniques to improve the efficiency of manufacturing solar cells are generally desired. Some embodiments of the present disclosure allow for increased manufacturing efficiency of solar cells by providing a new process for manufacturing solar cell structures. Some embodiments of the present disclosure allow for improved solar cell efficiency by providing new solar cell structures.

Drawings

Fig. 1A-1E show cross-sectional views of various stages in solar cell fabrication, according to an embodiment of the present disclosure, in which:

FIG. 1A shows a starting substrate for a solar cell;

FIG. 1B shows the structure of FIG. 1A after a passivating dielectric layer is formed on the light-receiving surface of the substrate;

FIG. 1C shows the structure of FIG. 1B after an intrinsic silicon layer is formed on the passivating dielectric layer;

FIG. 1D shows the structure of FIG. 1C after an N-type silicon layer is formed on the intrinsic silicon layer; and

fig. 1E shows the structure of fig. 1D after an anti-reflective coating (ARC) is formed on the N-type silicon layer.

Fig. 2 is a flow chart listing operations in a method of fabricating a solar cell corresponding to fig. 1A-1E, in accordance with an embodiment of the present disclosure.

Fig. 3 illustrates a cross-sectional view of a back contact solar cell having an emitter region formed over a back surface of a substrate and having a first exemplary layer stack on a light-receiving surface of the substrate, in accordance with an embodiment of the present disclosure.

Fig. 4 illustrates a cross-sectional view of a back contact solar cell having an emitter region formed in a back surface of a substrate and having a first exemplary layer stack on a light-receiving surface of the substrate, in accordance with an embodiment of the present disclosure.

Fig. 5 is an energy band diagram of a first exemplary layer stack disposed on a light-receiving surface of a solar cell as described in connection with fig. 3 and 4 in accordance with an embodiment of the disclosure.

Fig. 6A shows a cross-sectional view of a back contact solar cell having an emitter region formed over a back surface of a substrate and having a second exemplary layer stack on a light-receiving surface of the substrate, in accordance with an embodiment of the present disclosure.

Fig. 6B is an energy band diagram of a second exemplary layer stack disposed on a light-receiving surface of a solar cell as described in connection with fig. 6A in accordance with an embodiment of the disclosure.

Fig. 7A shows a cross-sectional view of a back contact solar cell having an emitter region formed over a back surface of a substrate and having a third exemplary layer stack on a light-receiving surface of the substrate, in accordance with an embodiment of the present disclosure.

Fig. 7B is an energy band diagram of a third exemplary layer stack disposed on a light-receiving surface of a solar cell described in conjunction with fig. 7A, in accordance with an embodiment of the present disclosure.

Detailed Description

The following detailed description is merely exemplary in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. As used herein, the word "exemplary" means "serving as an example, instance, or illustration. Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, brief summary or the following detailed description.

This specification includes references to "one embodiment" or "an embodiment". The appearances of the phrase "in one embodiment" or "in an embodiment" are not necessarily referring to the same embodiment. The particular features, structures, or characteristics may be combined in any suitable manner consistent with the present disclosure.

Terminology. The following paragraphs provide definitions and/or context for terms present in this disclosure (including the appended claims):

"include". The term is open ended. As used in the appended claims, the term does not exclude additional structures or steps.

"configured to". Various units or components may be described or claimed as "configured to" perform one or more tasks. In such context, "configured to" is used to connote structure by indicating that the unit/component includes structure for performing one or more of those tasks during operation. Thus, a given unit/component may be said to be configured to perform a task even when the unit/component is not currently operating (e.g., not turned on/active). Detailed description a unit/circuit/component "configured to" perform one or more tasks is expressly intended to mean that 35 u.s.c. § 112, sixth paragraph, is not applied to that unit/component.

"first", "second", etc. These terms, as used herein, are used as labels to the nouns that follow and do not imply any type of order (e.g., spatial, temporal, logical, etc.). For example, reference to a "first" solar cell does not necessarily imply that the solar cell is the first solar cell in a sequence; rather, the term "first" is used to distinguish the solar cell from another solar cell (e.g., a "second" solar cell).

"coupled" -the following description means that elements or nodes or structural features are "coupled" together. As used herein, unless expressly stated otherwise, "coupled" means that one element/node/feature is directly or indirectly connected to (or directly or indirectly communicates with) another element/node/feature, and not necessarily mechanically.

"prevent" -as used herein, prevent is used to describe reducing or minimizing the effect. When a component or feature is described as blocking an action, motion, or condition, it may completely prevent some outcome or consequence or future state. Additionally, "preventing" may also refer to reducing or diminishing certain consequences, manifestations, and/or effects that may occur. Thus, when a component, element, or feature is referred to as preventing a result or state, it does not necessarily prevent or eliminate the result or state altogether.

Furthermore, certain terminology is also used in the following description for the purpose of reference only, and thus, is not intended to be limiting. For example, terms such as "upper," "lower," "above," or "below" refer to the orientation in which reference is made in the drawings. Terms such as "front," "back," "rear," "side," "outer," and "inner" describe the orientation and/or position of certain portions of the component within a consistent but arbitrary frame of reference, which is clearly understood by reference to the text and the associated drawings describing the component in question. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

Methods of passivating a light-receiving surface of a solar cell with crystalline silicon and the resulting solar cell are described herein. In the following description, numerous specific details are set forth, such as specific process flow operations, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known fabrication techniques, such as lithography and patterning techniques, have not been described in detail in order to avoid unnecessarily obscuring embodiments of the present disclosure. Further, it is understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

Solar cells are disclosed herein. In one embodiment, a solar cell includes a silicon substrate having a light-receiving surface. An intrinsic silicon layer is disposed over the light-receiving surface of the silicon substrate. An N-type silicon layer is disposed on the intrinsic silicon layer. One or both of the intrinsic silicon layer and the N-type silicon layer is a microcrystalline or polycrystalline silicon layer.

In another embodiment, a solar cell includes a silicon substrate having a light-receiving surface. A passivation dielectric layer is disposed on the light-receiving surface of the silicon substrate. An N-type microcrystalline or polycrystalline silicon layer is disposed on the passivation dielectric layer.

Methods of fabricating solar cells are also disclosed herein. In one embodiment, a method of fabricating a solar cell involves forming a passivating dielectric layer on a light-receiving surface of a silicon substrate. The method also includes forming an N-type microcrystalline or polycrystalline silicon layer over the passivation dielectric layer. The method also includes forming an anti-reflective coating (ARC) layer on the N-type microcrystalline or polycrystalline silicon layer.

One or more embodiments described herein relate to methods for achieving improved Front Surface Field (FSF) performance of solar cells. In one embodiment, a crystalline silicon (Si) interlayer is used to achieve improved FSF performance to provide improved efficiency and reliability.

To provide context, light-induced degradation (LID) and/or Ultraviolet (UV) degradation cause long-term problems associated with long-term stability of solar cell performance. High efficiency solar cells are particularly subject to this degradation mode due to the increased sensitivity of their front surface passivation. Research has been conducted to improve the stability of such solar cells in a manner that reduces passivation or solar spectral absorption (e.g., JSC loss) without affecting performance. Performance stability may be critical for performance assurance as well as for product quality differentiation. More specifically, front surface passivation may be critical to the performance of high efficiency solar cells. Typically, front surface passivation is performed using a diffusion process, followed by high temperature oxidation, and finally by an anti-reflective coating (ARC) using Plasma Enhanced Chemical Vapor Deposition (PECVD). Silicon nitride (SiN or SiN: H) is often used as an ARC due to its optical properties and also due to its excellent passivation quality. A silicon nitride layer may be used to provide H + to the crystalline silicon/thermal oxide (c-Si/TOX) interface. Unfortunately, the interface may degrade due to prolonged exposure to UV light via hot electron injection at the interface, which destroys the existing Si-H bonds. Hot electrons can become trapped in subsequent layers and re-excited, bouncing back and forth across the interface, a process known as interface wear.

To address one or more of the above issues, according to one or more embodiments described herein, the efficiency and reliability of a solar cell is improved by interposing a crystalline silicon (Si) interlayer between a passivation oxide layer and an ARC layer (e.g., a SiN layer or SiN: H layer). In one embodiment, passivation and stability of the c-Si/TOX interface is improved by interposing a crystalline or partially crystalline Si interlayer between the thermal oxide and SiN or SiN: H ARC layer. Furthermore, an increase in Jsc can be achieved for solar cells by using a more transparent interlayer. Such interlayers may be deposited by a variety of suitable methods. In one embodiment, direct deposition of a microcrystalline or polycrystalline N-type silicon (μ c-Si: N) layer or a polycrystalline Si: N layer is performed. In another embodiment, a post-treatment is performed to first deposit an amorphous N-type silicon (Si: N) layer, and then an annealing process is used to crystallize the deposited layer. Post-processing may be performed with or without an ARC layer.

Without being bound by theory, in one embodiment, improved stability is achieved by direct deposition or phase inversion to a more crystalline phase, thereby improving the stress state of the N-type silicon interlayer, which balances the compressive properties of the underlying thermal oxide. The result is a more aggressive Si-O bond profile. Furthermore, the transition to the crystalline state may reduce the total number of O-H bonds at the surface of the underlying thermal oxide, thereby reducing the amount of trapping states for hot electron trapping and causing reduced interface wear.

More generally, in accordance with one or more embodiments, intrinsic microcrystalline or amorphous silicon, N-type microcrystalline or polycrystalline silicon (denoted as i: N) structures are fabricated with or without a thin oxide for improved passivation. In another embodiment, an N-type microcrystalline or polycrystalline silicon layer may be used alone, as long as the quality of the thin oxide is high enough to maintain good passivation. In the case of intrinsic microcrystalline or polycrystalline or amorphous silicon, the material provides additional passivation protection against the presence of oxide defects. In some embodiments, including a phosphorus doped microcrystalline or polycrystalline silicon layer in addition to the intrinsic layer can improve stability against UV degradation. A phosphorus doped layer may be implemented to achieve band bending, which can reduce the amount of recombination by driving off minority carriers to assist in shielding the interface.

Fig. 1A-1E show cross-sectional views of various stages in the manufacture of a solar cell according to an embodiment of the present disclosure. Fig. 2 is a flow chart listing operations in a method of fabricating a solar cell corresponding to fig. 1A-1E, in accordance with an embodiment of the present disclosure.

Fig. 1A shows a starting substrate of a solar cell. Referring to fig. 1A, a substrate 100 has a light-receiving surface 102 and a back surface 104. In one embodiment, the substrate 100 is a monocrystalline silicon substrate, such as a bulk monocrystalline N-type doped silicon substrate. However, it should be understood that the substrate 100 may be a layer disposed on the entire solar cell substrate, such as a polysilicon layer. In one embodiment, the light receiving surface 102 has a textured topography 106. In one such embodiment, a hydroxide-based wet etchant is employed to texture the front surface of the substrate 100. It should be appreciated that the textured surface may be a surface having a regular or irregular shape that serves to scatter incident light, reducing the amount of light reflected off the light receiving surface of the solar cell.

Fig. 1B shows the structure of fig. 1A after a passivating dielectric layer is formed on the light-receiving surface of the substrate. Referring to fig. 1B and corresponding operation 202 in flowchart 200, a passivating dielectric layer 108 is formed on the light-receiving surface 102 of the substrate 100. In one embodiment, the light receiving surface 102 has a textured topography 106, and the passivating dielectric layer 108 is conformal with the textured topography 106, as shown in fig. 1B.

In one embodiment, passivation dielectric layer 108 is silicon dioxide (SiO)₂) And (3) a layer. In one such embodiment, silicon dioxide (SiO)₂) The thickness of the layer is approximately in the range of 10 angstroms to 200 angstroms. In one embodiment, the passivating dielectric layer 108 is hydrophilic. In one embodiment, the passivation dielectric layer 108 is formed by techniques such as, but not limited to: subjecting a portion of a light-receiving surface of a silicon substrate to chemical oxidation, Plasma Enhanced Chemical Vapor Deposition (PECVD) of silicon dioxide (SiO)₂) Performing thermal oxidation and Atomic Layer Deposition (ALD) of SiO on a part of the light-receiving surface of the silicon substrate₂Or AlOx, or at O₂Or O₃Optical connection of silicon substrate in environmentThe receiving surface is exposed to Ultraviolet (UV) radiation.

Figure 1C shows the structure of figure 1B after an intrinsic silicon layer is formed on the passivating dielectric layer. Referring to fig. 1C, an intrinsic silicon layer 110 is formed on the passivation dielectric layer 108. In one embodiment, as shown in fig. 1C, the intrinsic silicon layer 110 is conformal with the textured topography 106.

In one embodiment, the intrinsic silicon layer 110 is an intrinsic microcrystalline or polycrystalline silicon layer. In one such embodiment, the thickness of the intrinsic microcrystalline or polycrystalline silicon layer is approximately in the range of 1 nanometer to 5 nanometers. In one embodiment, the intrinsic microcrystalline or polycrystalline silicon layer has a crystallization ratio approximately in the range of 0.1 to 0.9 (i.e., 10% to 90%), with the balance being amorphous. In one embodiment, the intrinsic microcrystalline or polycrystalline silicon layer comprises small particles having a diameter in the micrometer or nanometer range. The small particles may be embedded in a substantially amorphous silicon matrix and have substantially no long range order.

In one embodiment, the intrinsic microcrystalline or polycrystalline silicon layer is formed by depositing an intrinsic amorphous silicon layer and then phase converting the intrinsic amorphous silicon layer into an intrinsic microcrystalline or polycrystalline silicon layer. In one such embodiment, the intrinsic amorphous silicon layer is formed by a deposition process such as, but not limited to, Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), or sputtering (physical vapor deposition, PVD). In one embodiment, the phase transformation is achieved using techniques such as, but not limited to, heating in a furnace, Rapid Thermal Processing (RTP), laser annealing, or Forming Gas Annealing (FGA). In another embodiment, the intrinsic microcrystalline or polycrystalline silicon layer is formed by depositing the intrinsic microcrystalline or polycrystalline silicon layer. In one such embodiment, a PECVD is used to deposit the intrinsic microcrystalline or polysilicon layer.

In another embodiment, the intrinsic silicon layer 110 is an intrinsic amorphous silicon layer. In one such embodiment, the intrinsic amorphous silicon layer has a thickness approximately in the range of 1 nanometer to 5 nanometers. In one embodiment, forming the intrinsic amorphous silicon layer on the passivation dielectric layer 108 is performed at a temperature below about 400 degrees celsius. In one embodiment, the intrinsic amorphous silicon layer is formed using Plasma Enhanced Chemical Vapor Deposition (PECVD), represented by a-Si: H, which includes Si-H covalent bonds throughout the layer.

Fig. 1D shows the structure of fig. 1C after an N-type silicon layer is formed on the intrinsic silicon layer. Referring to fig. 1D and corresponding operation 204 in flowchart 200, an N-type silicon layer 112 is formed on intrinsic silicon layer 110. In one embodiment, as shown in fig. 1D, the N-type silicon layer 112 is conformal to the textured topography 106.

In one embodiment, the N-type silicon layer 112 is an N-type microcrystalline or polycrystalline silicon layer. In one such embodiment, the thickness of the intrinsic microcrystalline or polycrystalline silicon layer is approximately in the range of 1 nanometer to 20 nanometers. In one embodiment, the N-type microcrystalline or polycrystalline silicon layer has a crystallization ratio approximately in the range of 0.1 to 0.9 (i.e., 10% to 90%), with the balance being amorphous. In one embodiment, the concentration of N-type dopant (e.g., phosphorus) in the N-type microcrystalline or polycrystalline silicon layer is approximately 1E17-1E20 atoms/cm³Within the range of (1). In one embodiment, the N-type microcrystalline or polycrystalline silicon layer comprises small particles having a diameter in the micrometer or nanometer range. The small particles may be embedded in a substantially amorphous silicon matrix and have substantially no long range order. In one embodiment, the N-type dopant is included in the amorphous portion, the crystalline portion, or both.

In one embodiment, the N-type microcrystalline or polycrystalline silicon layer is formed by depositing an N-type amorphous silicon layer and then phase converting the N-type amorphous silicon layer into an N-type microcrystalline or polycrystalline silicon layer. In one such embodiment, the N-type amorphous silicon layer is formed by a deposition process such as, but not limited to, Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), or sputtering (physical vapor deposition, PVD). In one embodiment, the phase transformation is achieved using techniques such as, but not limited to, heating in a furnace, Rapid Thermal Processing (RTP), laser annealing, or Forming Gas Annealing (FGA). In another embodiment, the N-type microcrystalline or polycrystalline silicon layer is formed by depositing an N-type microcrystalline or polycrystalline silicon layer. In one such embodiment, an N-type microcrystalline or polycrystalline silicon layer is deposited using PECVD.

In another embodiment, the N-type silicon layer 112 is an N-type amorphous silicon layer. In one embodiment, forming an N-type amorphous silicon layer on the intrinsic silicon layer 110 is performed at a temperature of less than about 400 degrees celsius. In one embodiment, the N-type amorphous silicon layer is formed using Plasma Enhanced Chemical Vapor Deposition (PECVD), represented by phosphorus doped a-Si: H, which contains Si-H covalent bonds throughout the layer.

In both cases, in one embodiment, the microcrystalline or polycrystalline or amorphous N-type silicon layer 112 includes a dopant, such as a phosphorous dopant. In one such embodiment, the phosphorous dopant is incorporated during film deposition or in a post-implant operation.

Referring again to fig. 1D, in the first embodiment, the intrinsic silicon layer 110 is an amorphous intrinsic silicon layer, and the N-type silicon layer 112 is a microcrystalline or polycrystalline N-type silicon layer. In the second embodiment, the intrinsic silicon layer 110 is a microcrystalline or polycrystalline intrinsic silicon layer, and the N-type silicon layer 112 is an amorphous N-type silicon layer. In the third embodiment, the intrinsic silicon layer 110 is a microcrystalline or polycrystalline intrinsic silicon layer, and the N-type silicon layer 112 is a microcrystalline or polycrystalline N-type silicon layer.

Fig. 1E shows the structure of fig. 1D after an anti-reflective coating (ARC) is formed on the N-type silicon layer. Referring to fig. 1E and corresponding operation 206 in flowchart 200, an anti-reflective coating (ARC)114 is formed on the N-type silicon layer 112. In one embodiment, as shown in FIG. 1E, ARC layer 114 is conformal with textured topography 106.

In one embodiment, ARC layer 114 is a non-conductive ARC layer. In one such embodiment, the non-conductive ARC layer comprises silicon nitride. In one such embodiment, the silicon nitride is formed at a temperature of less than about 400 degrees celsius. In another embodiment, ARC layer 114 is a conductive ARC layer. In one such embodiment, the conductive ARC layer comprises an Indium Tin Oxide (ITO) layer.

Fig. 3 illustrates a cross-sectional view of a back contact solar cell having an emitter region formed over a back surface of a substrate and having a first exemplary layer stack on a light-receiving surface of the substrate, in accordance with an embodiment of the present disclosure.

Referring to fig. 3, the solar cell includes a silicon substrate 100 having a light-receiving surface 102. A passivation dielectric layer 108 is provided on the light receiving surface of the silicon substrate 100. An intrinsic silicon layer 110 is disposed on the passivating dielectric layer 108. An N-type silicon layer 112 is disposed on the intrinsic silicon layer 110. An anti-reflective coating (ARC)114 is disposed on the N-type silicon layer 112. As such, the layer stack on the light-receiving surface of the solar cell of fig. 3 is the same as described in connection with fig. 1A-1E.

Referring again to fig. 3, in the first embodiment, the intrinsic silicon layer 110 is an amorphous intrinsic silicon layer, and the N-type silicon layer 112 is a microcrystalline or polycrystalline N-type silicon layer. In the second embodiment, the intrinsic silicon layer 110 is a microcrystalline or polycrystalline intrinsic silicon layer, and the N-type silicon layer 112 is an amorphous N-type silicon layer. In the third embodiment, the intrinsic silicon layer 110 is a microcrystalline or polycrystalline intrinsic silicon layer, and the N-type silicon layer 112 is a microcrystalline or polycrystalline N-type silicon layer.

Referring again to fig. 3, on the back surface of the substrate 100, alternating P-type emitter regions 120 and N-type emitter regions 122 are formed. In one such embodiment, trenches 121 are provided between alternating P-type emitter regions 120 and N-type emitter regions 122. More specifically, in one embodiment, a first polysilicon emitter region 122 is formed on a first portion of a thin dielectric layer 124 and is doped with N-type impurities. A second polysilicon emitter region 120 is formed on a second portion of the thin dielectric layer 124 and is doped with P-type impurities. In one embodiment, the tunneling dielectric layer 124 is a silicon oxide layer having a thickness of about 2 nanometers or less.

Referring again to fig. 3, the conductive contact structure 128/130 is fabricated by: the insulating layer 126 is first deposited and patterned to have openings, and then one or more conductive layers are formed in the openings. In one embodiment, conductive contact structure 128/130 comprises a metal and is formed by deposition, photolithography, and etching methods, or alternatively by a printing process or an electroplating process, or alternatively by a foil bonding process.

Fig. 4 illustrates a cross-sectional view of a back contact solar cell having an emitter region formed in a back surface of a substrate and having a first exemplary layer stack on a light-receiving surface of the substrate, in accordance with an embodiment of the present disclosure.

Referring to fig. 4, the solar cell includes a silicon substrate 100 having a light-receiving surface 102. A passivation dielectric layer 108 is provided on the light receiving surface of the silicon substrate 100. An intrinsic silicon layer 110 is disposed on the passivating dielectric layer 108. An N-type silicon layer 112 is disposed on the intrinsic silicon layer 110. An anti-reflective coating (ARC)114 is disposed on the N-type silicon layer 112. As such, the layer stack on the light-receiving surface of the solar cell of fig. 4 is the same as described in connection with fig. 1A-1E.

Referring again to fig. 4, in the first embodiment, the intrinsic silicon layer 110 is an amorphous intrinsic silicon layer, and the N-type silicon layer 112 is a microcrystalline or polycrystalline N-type silicon layer. In the second embodiment, the intrinsic silicon layer 110 is a microcrystalline or polycrystalline intrinsic silicon layer, and the N-type silicon layer 112 is an amorphous N-type silicon layer. In the third embodiment, the intrinsic silicon layer 110 is a microcrystalline or polycrystalline intrinsic silicon layer, and the N-type silicon layer 112 is a microcrystalline or polycrystalline N-type silicon layer.

Referring again to fig. 4, within the back surface of substrate 100, alternating P-type emitter regions 150 and N-type emitter regions 152 are formed. More specifically, in one embodiment, the first emitter region 152 is formed within the first portion of the substrate 100 and is doped with N-type impurities. The second emitter region 150 is formed in the second portion of the substrate 100 and is doped with P-type impurities. Referring again to fig. 4, the conductive contact structure 158/160 is fabricated by: the insulating layer 156 is first deposited and patterned to have openings, and then one or more conductive layers are formed in the openings. In one embodiment, conductive contact structure 158/160 comprises a metal and is formed by deposition, photolithography, and etching methods, or alternatively by a printing process or an electroplating process, or alternatively by a foil bonding process.

Fig. 5 is an energy band diagram 500 of a first exemplary layer stack disposed on a light-receiving surface of a solar cell as described in connection with fig. 3 and 4 in accordance with an embodiment of the disclosure. Referring to band diagram 500, a band structure of a material stack comprising N-type doped silicon (N), intrinsic silicon (i), a thin oxide layer (Tox), and a crystalline silicon substrate (c-Si) is provided. The fermi level is shown at 502, indicating good passivation of the light receiving surface of a substrate with this material stack.

Fig. 6A shows a cross-sectional view of a back contact solar cell having an emitter region formed over a back surface of a substrate and having a second exemplary layer stack on a light-receiving surface of the substrate, in accordance with an embodiment of the present disclosure.

Referring to fig. 6A, the solar cell includes a silicon substrate 100 having a light-receiving surface 102. An intrinsic silicon layer 110 is provided on the light receiving surface 102 of the silicon substrate 100 (in this case, the growth may be epitaxial). An N-type silicon layer 112 is disposed on the intrinsic silicon layer 110. An anti-reflective coating (ARC)114 is disposed on the N-type silicon layer 112. As such, the stack on the light-receiving surface of the solar cell of fig. 6A does not include the passivation dielectric layer 108 described in connection with fig. 3. However, other features described in connection with fig. 3 are similar. Additionally, it should be appreciated that the emitter region may be formed within the substrate, as described in connection with fig. 4.

Referring again to fig. 6A, in the first embodiment, the intrinsic silicon layer 110 is an amorphous intrinsic silicon layer, and the N-type silicon layer 112 is a microcrystalline or polycrystalline N-type silicon layer. In the second embodiment, the intrinsic silicon layer 110 is a microcrystalline or polycrystalline intrinsic silicon layer, and the N-type silicon layer 112 is an amorphous N-type silicon layer. In the third embodiment, the intrinsic silicon layer 110 is a microcrystalline or polycrystalline intrinsic silicon layer, and the N-type silicon layer 112 is a microcrystalline or polycrystalline N-type silicon layer.

Fig. 6B is an energy band diagram 600 of a second exemplary layer stack disposed on a light-receiving surface of a solar cell as described in connection with fig. 6A in accordance with an embodiment of the disclosure. Referring to band diagram 600, a band structure of a material stack comprising N-type doped silicon (N), intrinsic silicon (i), and crystalline silicon substrate (c-Si) is provided. The fermi level is shown at 602, indicating that the light receiving surface of the substrate with this material stack has good passivation, but no oxide layer is disposed to block the via 604.

Fig. 7A shows a cross-sectional view of a back contact solar cell having an emitter region formed over a back surface of a substrate and having a third exemplary layer stack on a light-receiving surface of the substrate, in accordance with an embodiment of the present disclosure.

Referring to fig. 7A, the solar cell includes a silicon substrate 100 having a light-receiving surface 102. A passivation dielectric layer 108 is disposed on the light-receiving surface 102 of the silicon substrate 100. A microcrystalline or polycrystalline N-type silicon layer 112 is disposed on the passivation dielectric layer 108. An anti-reflective coating (ARC)114 is disposed on the microcrystalline or polycrystalline N-type silicon layer 112. As such, the stack on the light-receiving surface of the solar cell of fig. 7A does not include the microcrystalline or polycrystalline or amorphous intrinsic silicon layer 110 described in connection with fig. 3. However, other features described in connection with fig. 3 are similar. Additionally, it should be appreciated that the emitter region may be formed within the substrate, as described in connection with fig. 4.

Fig. 7B is an energy band diagram 700 of a third exemplary layer stack disposed on a light-receiving surface of a solar cell as described in connection with fig. 7A in accordance with an embodiment of the present disclosure. Referring to band diagram 700, a band structure of a stack of materials including microcrystalline or polycrystalline N-type doped silicon (N), a thin oxide layer (Tox), and a crystalline silicon substrate (c-Si) is provided. The fermi level is shown at 702, indicating good passivation of the light receiving surface of the substrate with this material stack.

In general, while certain materials have been described above with particularity, some materials may be readily substituted for other such embodiments while remaining within the spirit and scope of the embodiments. For example, in one embodiment, a substrate of a different material, such as a III-V material substrate or a polysilicon substrate, may be used in place of the silicon substrate. Further, it should be understood that the substrate may be an n + or p + type material. Furthermore, it should be understood that while N + type and P + type doping are specifically described for emitter regions on the back surface of the solar cell, other embodiments are contemplated that include opposite conductivity types, such as P + type and N + type doping, respectively. This also applies to front contact cell and double-sided cell architectures.

Thus, a method of passivating a light receiving surface of a solar cell with crystalline silicon and the resulting solar cell are disclosed.

Although specific embodiments have been described above, even if only a single embodiment is described with respect to a particular feature, these embodiments are not intended to limit the scope of the present disclosure. Examples of features provided in the present disclosure are intended to be illustrative, not limiting, unless otherwise specified. The above description is intended to cover alternatives, modifications, and equivalents, which may be apparent to those skilled in the art having the benefit of this disclosure.

The scope of the present disclosure includes any feature or combination of features disclosed herein (either explicitly or implicitly), or any generalization thereof, whether or not it mitigates any or all of the problems addressed herein. Accordingly, new claims may be formulated to any such combination of features during the prosecution of this application (or of an application claiming priority thereto). In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in the specific forms enumerated in the appended claims.

In one embodiment, a solar cell includes a silicon substrate having a light-receiving surface. An intrinsic silicon layer is disposed over the light-receiving surface of the silicon substrate. An N-type silicon layer is disposed on the intrinsic silicon layer, and one or both of the intrinsic silicon layer and the N-type silicon layer is a microcrystalline or polycrystalline silicon layer.

In one embodiment, the N-type silicon layer is an N-type microcrystalline or polycrystalline silicon layer having a crystallization ratio approximately in the range of 0.1 to 0.9, with the balance being amorphous.

In one embodiment, the concentration of N-type dopant in the N-type microcrystalline or polycrystalline silicon layer is approximately 1E17-1E20 atoms/cm³Within the range of (1).

In one embodiment, the solar cell further comprises a passivation dielectric layer disposed on the light-receiving surface of the silicon substrate, and an intrinsic silicon layer is disposed on the passivation dielectric layer.

In one embodiment, the passivation dielectric layer is silicon dioxide (SiO) having a thickness approximately in the range of 10 to 200 angstroms₂) And (3) a layer.

In one embodiment, the solar cell further comprises an anti-reflective coating (ARC) disposed on the N-type silicon layer.

In one embodiment, the light receiving surface has a textured topography, and both the intrinsic silicon layer and the N-type silicon layer are conformal to the textured topography of the light receiving surface.

In one embodiment, the substrate further includes a back surface opposite the light-receiving surface, and the solar cell further includes a plurality of alternating N-type and P-type semiconductor regions at or above the back surface of the substrate, and a conductive contact structure electrically connected to the plurality of alternating N-type and P-type semiconductor regions.

In one embodiment, a solar cell includes a silicon substrate having a light-receiving surface. A passivation dielectric layer is disposed on the light-receiving surface of the silicon substrate. An N-type microcrystalline or polycrystalline silicon layer is disposed on the passivation dielectric layer.

In one embodiment, the N-type microcrystalline or polycrystalline silicon layer has a crystallization ratio approximately in the range of 0.1 to 0.9, with the balance being amorphous.

In one embodiment, the concentration of N-type dopant in the N-type microcrystalline or polycrystalline silicon layer is approximately 1e17-1e20 atoms/cm³Within the range of (1).

In one embodiment, the solar cell further comprises an anti-reflective coating (ARC) disposed on the N-type microcrystalline or polycrystalline silicon layer.

In one embodiment, the passivation dielectric layer is silicon dioxide (SiO) having a thickness approximately in the range of 10 to 200 angstroms₂) And (3) a layer.

In one embodiment, the light-receiving surface of the substrate has a textured topography, and the N-type microcrystalline or polycrystalline silicon layer is conformal with the textured topography of the light-receiving surface.

In one embodiment, the substrate further includes a back surface opposite the light-receiving surface, and the solar cell further includes a plurality of alternating N-type and P-type semiconductor regions at or above the back surface of the substrate, and a conductive contact structure electrically connected to the plurality of alternating N-type and P-type semiconductor regions.

In one embodiment, a method of fabricating a solar cell includes forming a passivation dielectric layer on a light-receiving surface of a silicon substrate. The method also includes forming an N-type microcrystalline or polycrystalline silicon layer over the passivation dielectric layer. The method also includes forming an anti-reflective coating (ARC) layer on the N-type microcrystalline or polycrystalline silicon layer.

In one embodiment, forming the N-type microcrystalline or polycrystalline silicon layer comprises: depositing an N-type amorphous silicon layer; and then phase-converting the N-type amorphous silicon layer into an N-type microcrystalline or polycrystalline silicon layer.

In one embodiment, forming the N-type microcrystalline or polycrystalline silicon layer comprises: and depositing an N-type microcrystalline or polycrystalline silicon layer.

In one embodiment, the method further comprises forming an intrinsic microcrystalline or polycrystalline or amorphous silicon layer on the passivation dielectric layer, and forming an N-type microcrystalline or polycrystalline silicon layer comprises forming on the intrinsic microcrystalline or polycrystalline or amorphous silicon layer.

In one embodiment, forming the passivation dielectric layer comprises using a technique selected from the group consisting of: subjecting a portion of a light-receiving surface of a silicon substrate to chemical oxidation, Plasma Enhanced Chemical Vapor Deposition (PECVD) of silicon dioxide (SiO)₂) Atomic Layer Deposition (ALD) SiO₂Or AlOx, thermally oxidizing a part of the light-receiving surface of the silicon substrate, and₂or O₃The light-receiving surface of the silicon substrate is exposed to Ultraviolet (UV) radiation in an environment.