阅读说明：本技术 一种音频传输方法、系统、计算机设备、介质及应用 (Audio transmission method, system, computer equipment, medium and application ) 是由 王荀 林川 彭辉 龙仕强 于 2021-08-18 设计创作，主要内容包括：本发明属于数据传输技术领域,公开了一种音频传输方法、系统、计算机设备、介质及应用,在某个时钟周期T0时刻开始传输,首先让WS信号发生变化；WS发生变化后,准备该通道需要发送的数据,WS＝0表示接下来传输右声道,WS＝1表示接下来传输左声道；在下一个时钟周期T0+1时刻的下降沿让四个数据位同步发生变化；接收方会在下一个上升沿时刻进行数据的并行采样；在SDATA右声道数据R0,R1,R2,R3发生变化的同时WS信号也拉高为1切换到左声道；在WS切换到左声道时的下一时刻的下降沿让四个数据位同步发生变化；接收方会在下一个上升沿时刻进行数据的并行采样；继续发下一个音频数据。本发明提升了音频传输效率。(The invention belongs to the technical field of data transmission, and discloses an audio transmission method, a system, computer equipment, a medium and application, wherein transmission is started at the moment of a certain clock period T0, and a WS signal is changed; after the WS changes, preparing data that needs to be sent by the channel, where WS equals 0 to indicate that the right channel is to be transmitted next, and WS equals 1 to indicate that the left channel is to be transmitted next; the falling edge at the time of the next clock cycle T0+1 allows the four data bits to change synchronously; the receiver performs parallel sampling of data at the next rising edge moment; the WS signal is also pulled up to 1 to switch to the left channel while the SDATA right channel data R0, R1, R2, R3 change; the four data bits are synchronously changed at the falling edge of the next moment when the WS is switched to the left channel; the receiver performs parallel sampling of data at the next rising edge moment; the next audio data is sent on. The invention improves the audio transmission efficiency.)

1. An audio transmission method is characterized in that the audio transmission method is compatible with an I2S multichannel transmission protocol at a physical transmission layer, the same wire is used for transmitting I2S, and four serial data lines are the same as the I2S transmission protocol when transmitting multichannel audio; and when the two-channel audio is transmitted, the transmission of the 4bits of the two channels is completed by adopting a parallel transmission mode.

2. The audio transmission method as claimed in claim 1, wherein the audio transmission method starts transmission at a time of a certain clock period T0, so that the WS signal is changed.

3. The audio transmission method as claimed in claim 2, wherein after WS changes, data required to be transmitted by the channel is prepared, WS-0 indicates that the right channel is transmitted next, and WS-1 indicates that the left channel is transmitted next.

4. The audio transmission method as claimed in claim 3, wherein the four data bits are changed in synchronization at a falling edge at a time of the next clock period T0+ 1; the receiver will perform parallel sampling of the data at the next rising edge instant.

5. The audio transmission method as claimed in claim 4, wherein the falling edge at the time of the next clock cycle T0+1 allows four data bits to be changed in synchronization, the four data being R0, R1, R2, R3 of the right channel, respectively.

6. The audio transmission method of claim 4, wherein the WS signal is pulled high to 1 and switched to the left channel while the SDATA right channel data R0, R1, R2, R3 are changed.

7. The audio transmission method of claim 5, wherein a falling edge at a next time when WS switches to the left channel allows four data bits to change in synchronization; the receiver will perform parallel sampling of the data at the next rising edge instant.

8. The audio transmission method as claimed in claim 7, wherein the falling edge at the next time when WS switches to the left channel allows four data bits to be changed in synchronization, the four data being L0, L1, L2, L3 of the left channel, respectively.

9. The audio transmission method as claimed in claim 7, wherein the next audio data is continued to be transmitted.

10. The audio transmission method as claimed in claim 4 or 7, wherein the parallel-to-serial operation is performed after the parallel sampling data of the receiving side.

11. An audio transmission system for implementing the audio transmission method according to any one of claims 1 to 9, wherein the audio transmission system comprises:

a signal change module, configured to start transmission at a time of a certain clock period T0, and first change the WS signal;

a sending data preparation module, configured to prepare data to be sent by the channel after WS changes;

a data bit synchronization change module, configured to change four data bits synchronously at a falling edge of a next clock period T0+ 1; the receiver performs parallel sampling of data at the next rising edge moment;

a channel switching module, configured to switch the WS signal to the left channel by pulling up to 1 when the SDATA right channel data R0, R1, R2, and R3 change; the four data bits are synchronously changed at the falling edge of the next moment when the WS is switched to the left channel; the receiver will perform parallel sampling of the data at the next rising edge instant.

12. A computer arrangement, characterized in that the computer arrangement comprises a memory and a processor, the memory storing a computer program which, when executed by the processor, causes the processor to carry out the steps of the audio transmission method of any of claims 1-9.

13. A computer-readable storage medium, storing a computer program which, when executed by a processor, causes the processor to carry out the steps of the audio transmission method of any of claims 1 to 9.

14. Use of an audio transmission method according to any of claims 1 to 9 in an audio device.

Technical Field

The invention belongs to the technical field of data transmission, and particularly relates to an audio transmission method, an audio transmission system, computer equipment, a medium and application.

Background

At present: the I2S bus, also called the integrated circuit built-in audio bus, is commonly used as the integrated circuit built-in bus of audio devices on the market today. The bus is a bus standard established by Philips for audio data transmission between digital audio devices, is widely used at present, and adopts a design of transmitting a clock and a data signal by using independent wires to separate the data and the clock signal. Therefore, a standard I2S bus typically consists of 3 serial conductors, one time division multiplexed data line; a word selection line; a clock line.

The first prior art is as follows: CN201821939725.7 is a communication device with an audio single channel full duplex communication circuit. The utility model provides a communication equipment with audio frequency single channel full duplex communication circuit, include: exciter unit, the control unit, single channel audio power amplifier, receiving element, baseband unit, power supply unit and duplexer, wherein, the exciter unit with the control unit both way junction, the control unit with the receiving element, the receiving element is connected with the receiving terminal of baseband unit and duplexer, single channel audio power amplifier with the transmitting terminal of duplexer is connected, the baseband unit with the exciter unit is connected, the baseband unit further is connected with data terminal, the power supply unit with exciter unit, the control unit, single channel audio power amplifier, receiving element, baseband unit and duplexer are connected in order to supply power.

The utility model discloses reach certain stability, the reliability is also fine simultaneously.

The second prior art is: CN201710512532.7 is a multifunctional audio integration system. The utility model provides a multi-functional audio integrated system, includes audio signal input device and power amplifier output device, be equipped with audio signal processing's integrated circuit module between audio signal input device and the power amplifier output device, the integrated circuit module includes signal input module, single double-channel switches module, signal amplification circuit, overload compression circuit, bass passageway processing module, automatic silence module and power amplifier output module, the audio signal input of signal input module is connected with single double-channel switches module, single double-channel switches module including single double-switch, left side passageway audio processing circuit and right side passageway audio processing circuit. The invention determines the output of single track and stereo by the single-channel and double-channel switching module, and sets overload compression protection in the left channel and the right channel, thereby ensuring that no over-high voltage occurs after the audio signal is amplified and maintaining the stability of the audio integrated system.

The prior art is three: CN201120510657.4 four-channel audio processor. A four-channel audio processor is characterized by comprising an audio input module, an input processing module, a four-channel output processing module and an audio output module; the audio input module is used for receiving an external audio signal and inputting the external audio signal to the input processing module; the input processing module comprises a first input processing unit and a second input processing unit, wherein each input processing unit is provided with a 5-section parametric equalizer and is used for carrying out signal selection, primary overall processing and 5-section parametric equalization regulation on an input audio signal; the four-channel output processing module comprises first to fourth output processing channels, each output processing channel comprises a primary processing unit, a high-pass filter and a secondary processing unit which are sequentially and electrically connected, the primary processing unit is provided with a 5-section parametric equalizer, and the secondary processing unit is provided with a 2-section parametric equalizer and is used for dividing the audio signals which are primarily and integrally processed into four channels and carrying out further detailed processing according to different requirements; the audio output module comprises first to fourth channel output ends which are respectively and electrically connected with the tail ends of the first to fourth output processing channels and are used for simultaneously outputting the audio signals processed by the first to fourth output processing channels; the audio input module, the input processing module, the four-channel output processing module and the audio output module are electrically connected in sequence. The utility model discloses a four-channel audio processor carries out holistic parameter equalization regulation back in the audio signal that will input is divided into first and second input processing unit, and the branch passageway refines in the first to fourth output processing passageway of input respectively again and handles and parameter equalization regulation, makes the audio signal of each passageway output can have different audios to reach different stereo effect when exporting. A plurality of parametric equalizers are provided in the audio signal processing process, so that not only can the overall adjustment be realized, but also each output channel can be subjected to fine adjustment, and the use requirement of multi-sound-effect equalization adjustment is met.

The prior art is four: CN201720304551.6 is an eight-channel audio processor. The utility model discloses an eight-channel audio processor, which comprises an eight-channel audio processor body, wherein a plurality of heat dissipation holes are respectively arranged on two corresponding sides of the eight-channel audio processor body, an equipment box is arranged at the center of the top of the eight-channel audio processor body, a top plate is arranged at the top of the equipment box, a baffle is arranged on one side of each heat dissipation hole, the top of the baffle is connected with the inner wall of the top of the eight-channel audio processor body through an electric push rod, a PLC controller is arranged on one side of the electric push rod, a temperature sensor is arranged on one side of the PLC controller, a drying box is arranged in the equipment box, a plurality of through holes are arranged at the bottom of the drying box, guide rails are arranged on two corresponding sides of the bottom of the equipment box, a movable slider is arranged on the guide rails, and a radiator is arranged at the bottom of the movable slider, the eight-channel audio processor has a good heat dissipation effect.

In the commonly used audio data, there are two-channel, four-channel, six-channel, eight-channel, and so on audio data in addition to the single channel. The I2S bus addresses multiple channels by providing three additional data lines, for a total of four data lines, supporting eight channel audio communications at most. However, when the four data line I2S bus transmits single-channel or dual-channel audio data, only one data line is used, and the rest data lines do not transmit any data, which is in a redundant state, resulting in low audio transmission efficiency and resource waste.

Through the above analysis, the problems and defects of the prior art are as follows: the current I2S bus has low audio transmission efficiency when transmitting single-channel or double-channel audio data.

The difficulty in solving the above problems and defects is: the current I2S bus transmission is not compatible with the parallel transmission of single-channel or dual-channel audio data under the condition of a multi-channel data line, and a new transmission mode is needed to solve the problems.

The significance of solving the problems and the defects is as follows: the transmission mode of the invention is compatible with the existing I2S bus transmission protocol, and simultaneously can transmit single-channel or double-channel audio data in parallel. The audio transmission efficiency is improved.

Disclosure of Invention

In view of the problems in the prior art, the present invention provides an audio transmission method, system, computer device, medium, and application.

The invention is realized in such a way that an audio transmission method comprises the following steps:

first, transmission is started at the time of a certain clock period T0, and the WS (channel selection) signal is first changed.

And secondly, after the WS is changed, preparing data which needs to be sent by the channel, wherein the WS is 0 to indicate that the right channel is transmitted next, and the WS is 1 to indicate that the left channel is transmitted next.

Third, the four data bits are changed synchronously at the falling edge at the time of the next clock cycle T0+ 1. The receiver will perform parallel sampling of the data at the next rising edge instant.

In the fourth step, it is assumed that four bytes of audio data are transmitted, the four bytes being R0, R1, R2, R3 from the upper to the lower. The WS signal is also pulled up to 1 and switched to the left channel while the SDATA right channel data R0, R1, R2, R3 change. And completing the parallel transmission of the right channel data.

Fifthly, changing four data bits synchronously at the falling edge of the next moment when WS switches to the left channel; the receiver will perform parallel sampling of the data at the next rising edge instant.

And sixthly, continuing transmitting the audio data of the next channel until all the audio data are transmitted.

Further, in a first step, the WS signal determines the left and right channels for the audio data to be transmitted next.

Further, in the third step, the falling edge at the time of the next clock cycle T0+1 causes four data bits to change in synchronization, which are R0, R1, R2, and R3 of the right channel, respectively.

Further, in the fourth step, since the timing at which WS changes is always one clock cycle earlier than the timing at which SDATA changes, the WS signal is pulled up to 1 and switched to the left channel while SDATA right channel data R0, R1, R2, R3 changes.

Further, in the fifth step, the falling edge at the next timing when WS switches to the left channel causes four data bit syncs to change, and the four bytes of data of the left channel from the upper order to the lower order are L0, L1, L2, and L3, respectively. . The receiver will perform parallel sampling of the data at the next rising edge instant.

Another object of the present invention is to provide an audio transmission system implementing the audio transmission method, the audio transmission system including:

and a signal change module, configured to start transmission at a time T0 of a certain clock cycle, and first change the WS signal.

And the sending data preparation module is used for preparing the data to be sent by the channel after the WS is changed.

A data bit synchronization change module, configured to change four data bits synchronously at a falling edge of a next clock period T0+ 1; the receiver will perform parallel sampling of the data at the next rising edge instant.

A channel switching module, configured to switch the WS signal to the left channel by pulling up to 1 when the SDATA right channel data R0, R1, R2, and R3 change; the four data bits are synchronously changed at the falling edge of the next moment when the WS is switched to the left channel; the receiver will perform parallel sampling of the data at the next rising edge instant.

It is a further object of the invention to provide a computer arrangement comprising a memory and a processor, the memory storing a computer program which, when executed by the processor, causes the processor to carry out the steps of the audio transmission method.

It is a further object of the present invention to provide a computer readable storage medium, storing a computer program which, when executed by a processor, causes the processor to perform the steps of the audio transmission method.

Another object of the present invention is to provide an application of the audio transmission method in an audio device.

By combining all the technical schemes, the invention has the advantages and positive effects that: the invention is compatible with I2S multichannel transmission protocol at a physical transmission layer, uses the same wire as I2S transmission, and has the same electrical characteristics. The serial data lines are four in total, as in the I2S transport protocol when carrying multichannel audio. However, when the two-channel audio is transmitted, a parallel transmission mode is adopted, so that the transmission of the 4bits of the two channels can be completed only by two clock cycles. The method provided by the invention can use the remaining data lines for parallel transmission when transmitting single-channel or double-channel audio data, thereby improving the audio transmission efficiency.

Drawings

Fig. 1 is a flowchart of an audio transmission method according to an embodiment of the present invention.

Fig. 2 is a schematic structural diagram of an audio transmission system according to an embodiment of the present invention;

in fig. 2: 1. a signal change module; 2. a transmit data preparation module; 3. a data bit synchronous change module; 4. and a sound channel switching module.

FIG. 3 is a timing diagram of I2S transmitting two-channel audio according to an embodiment of the present invention.

Fig. 4 is a timing diagram of the present invention for transmitting two-channel audio according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

In view of the problems in the prior art, the present invention provides an audio transmission method, which is described in detail below with reference to the accompanying drawings.

As shown in fig. 1, the audio transmission method provided by the present invention includes the following steps:

s101: at the time of a certain clock cycle T0, transmission is started, and the WS (channel select) signal is first changed.

S102: after the WS changes, data to be transmitted by the channel is prepared, where WS equals 0 to indicate that the right channel is transmitted next, and WS equals 1 to indicate that the left channel is transmitted next.

S103: the falling edge at time T0+1 of the next clock cycle synchronizes the four data bits. The receiver will perform parallel sampling of the data at the next rising edge instant.

S104: the WS signal is also pulled up to 1 and switched to the left channel while the SDATA right channel data R0, R1, R2, R3 change.

S105: the four data bits are synchronously changed at the falling edge of the next moment when the WS is switched to the left channel; the receiver will perform parallel sampling of the data at the next rising edge instant.

S106: the next audio data is sent on.

In the invention, the parallel-serial operation is carried out after the receiving party samples the data in parallel.

Those skilled in the art of audio transmission methods provided by the present invention may also implement other steps, and the invention of fig. 1 is provided as only one specific embodiment.

As shown in fig. 2, the audio transmission system provided by the present invention includes:

the signal change module 1 is configured to start transmission at a time of a certain clock period T0, and first change the WS signal.

And a sending data preparation module 2, configured to prepare data that needs to be sent by the channel after the WS changes.

A data bit synchronous change module 3, configured to change four data bits synchronously at a falling edge of a next clock period T0+ 1; the receiver will perform parallel sampling of the data at the next rising edge instant.

A channel switching module 4, configured to switch the WS signal to the left channel by pulling up to 1 while the SDATA right channel data R0, R1, R2, and R3 change; the four data bits are synchronously changed at the falling edge of the next moment when the WS is switched to the left channel; the receiver will perform parallel sampling of the data at the next rising edge instant.

The technical solution of the present invention is further described below with reference to the accompanying drawings.

The I2S of the audio transmission method provided by the present invention mainly has three types of signals in audio transmission:

(1) the serial clock SCLK, also called the bit clock BCLK, has one pulse for each bit of data of the digital audio. SCLK has a frequency of 2x sampling frequency x number of sampling bits.

(2) A word selection line WS for switching data of the left and right channels. WS is the sampling frequency. 0 indicates that left channel data is transmitted and 1 indicates that the right channel is transmitted.

(3) Serial data SDATA, I2S formatted signal, regardless of how many bits of valid data, the most significant bit of data always appears at the 2 nd SCLK pulse after the LRCK change (i.e., the beginning of a frame). This allows the number of significant bits to be different between the receiving side and the transmitting side. If the number of effective digits which can be processed by the receiving end is less than that of the transmitting end, redundant low-order data in the data frame can be abandoned; if the number of the significant digits which can be processed by the receiving end is more than that of the transmitting end, the rest bits can be self-complemented. The synchronization mechanism facilitates interconnection of digital audio devices without causing data skew.

As shown in fig. 3, there are three other data lines for transmitting the rest of the channels, in the figure, I2S transmits two-channel audio, and each channel transmits 4 bits. It can be seen that the remaining three data lanes are not utilized and the data transfer takes a total of 8 clock cycles to complete the transfer.

Fig. 4 is a timing diagram of transmitting two-channel audio data according to the present invention.

The audio transmission method provided by the invention specifically comprises the following steps:

the method comprises the following steps: at the time of a certain clock period T0, transmission is started, and the WS signal is changed to determine the left and right channels to which audio data is to be transmitted next.

Step two: after the WS changes, data to be transmitted by the channel is prepared, where WS equals 0 to indicate that the right channel is transmitted next, and WS equals 1 to indicate that the left channel is transmitted next. The right channel data is transmitted first in the example of fig. 4.

Step three: the falling edge at the time of the next clock cycle T0+1 causes four data bits to change in synchronization, which are R0, R1, R2, R3 for the right channel, respectively. The receiver will perform parallel sampling of the data at the next rising edge instant.

Step four: since the timing at which WS changes is always one clock cycle earlier than the timing at which SDATA changes, the WS signal is pulled up to 1 and switched to the left channel while SDATA right channel data R0, R1, R2, R3 changes.

Step five: the falling edge at the next time when WS switches to the left channel causes four data bit syncs to change, L0, L1, L2, L3 for the left channel, respectively. The receiver will perform parallel sampling of the data at the next rising edge instant.

Step six: the next audio data is sent on.

It should be noted that the embodiments of the present invention can be realized by hardware, software, or a combination of software and hardware. The hardware portion may be implemented using dedicated logic; the software portions may be stored in a memory and executed by a suitable instruction execution system, such as a microprocessor or specially designed hardware. Those skilled in the art will appreciate that the apparatus and methods described above may be implemented using computer executable instructions and/or embodied in processor control code, such code being provided on a carrier medium such as a disk, CD-or DVD-ROM, programmable memory such as read only memory (firmware), or a data carrier such as an optical or electronic signal carrier, for example. The apparatus and its modules of the present invention may be implemented by hardware circuits such as very large scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, or programmable hardware devices such as field programmable gate arrays, programmable logic devices, etc., or by software executed by various types of processors, or by a combination of hardware circuits and software, e.g., firmware.

The above description is only for the purpose of illustrating the present invention and the appended claims are not to be construed as limiting the scope of the invention, which is intended to cover all modifications, equivalents and improvements that are within the spirit and scope of the invention as defined by the appended claims.