阅读说明：本技术 栅极驱动阵列型显示面板 (Grid driving array type display panel ) 是由 朱静 于 2019-08-20 设计创作，主要内容包括：本揭示提供一种栅极驱动阵列型显示面板,所述栅极驱动阵列型显示面板定义有显示区和边框区,以及所述栅极驱动阵列型显示面板包含：多个像素单元,以阵列形式设置在所述显示区内；以及GOA电路,包含：GOA单元组,设置在所述显示区内；以及走线组,与所述GOA单元组电性连接且设置在所述边框区内,其中所述走线组包含GOA总线和公共电极线。通过将GOA电路的级联的GOA单元组设置显示区内以实现极窄边框的设计。(The present disclosure provides a gate driving array type display panel, which is defined with a display region and a frame region, and includes: a plurality of pixel units arranged in an array within the display area; and a GOA circuit comprising: the GOA unit group is arranged in the display area; and the routing group is electrically connected with the GOA unit group and is arranged in the frame area, wherein the routing group comprises a GOA bus and a common electrode wire. The design of an extremely narrow frame is realized by arranging the cascaded GOA unit groups of the GOA circuit in the display area.)

1. A gate driving array type display panel, wherein the gate driving array type display panel is defined with a display region and a frame region, and the gate driving array type display panel comprises:

a plurality of pixel units arranged in an array within the display area; and

a GOA circuit, comprising:

the GOA unit group is arranged in the display area; and

and the routing group is electrically connected with the GOA unit group and is arranged in the frame area, wherein the routing group comprises a GOA bus and a common electrode wire.

2. The gate driving array type display panel of claim 1, wherein the group of GOAs is arranged along an extending direction of a long side of the gate driving array type display panel.

3. A gate driving array type display panel as claimed in claim 2, wherein the group of lines is arranged along an extending direction of a short side of the gate driving array type display panel, wherein the long side is adjacent to the short side.

4. The gate driving array type display panel of claim 1, wherein the group of GOA cells comprises a plurality of cascaded GOA cells.

5. The gate driving array type display panel of claim 4, wherein each GOA unit comprises a pull-up control circuit, a pull-up circuit, a pull-down sustain circuit, and a bootstrap capacitor.

6. A gate driving array type display panel according to claim 1, wherein the width of the wiring group is equal to a distance from a side of the wiring group contacting the display region to an edge of the short side of the gate driving array type display panel.

7. A gate drive array type display panel as claimed in claim 6, wherein said width of said group of lines is 1.2 μm or less.

8. The gate driving array type display panel of claim 1, wherein the gate driving array type display panel comprises two sets of routing groups respectively disposed at two opposite sides of the display area, and the two sets of routing groups are respectively adjacent to edges of two short sides of the gate driving array type display panel.

9. The gate driving array type display panel of claim 1, wherein the gate driving array type display panel comprises two sets of GOA cell groups, one of the two sets of GOA cell groups is adjacent to an edge of the display region.

10. The gate driving array type display panel of claim 9, wherein one of the two groups of GOA cell groups is disposed between the pixel cells of two adjacent rows.

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a gate driving array type display panel.

Background

The gate driver on array (GOA) technology is a technology in which gate driver ICs (ICs) are directly fabricated on an array substrate instead of a driver chip fabricated from an external silicon chip. The GOA circuit can be directly arranged around the panel, manufacturing procedures are reduced, the design of a narrow frame on one side of the display screen where the GOA circuit is arranged is facilitated, production cost can be reduced, and therefore the GOA circuit is widely applied and researched.

In response to consumer demand, large-sized, high-resolution displays with very Narrow bezel (SNB) designs are becoming a market trend. Moreover, the requirement of the spliced display screen for designing narrow edge width is more necessary. However, as the resolution becomes higher and the pixel size becomes smaller, the GOA layout (layout) space becomes larger accordingly. Therefore, how to realize a narrow bezel becomes a problem to be solved.

Referring to fig. 1, a schematic diagram of a gate driving array type display panel 1 in the prior art is shown. The gate driving array type display panel 1 defines a display area (active area)10 and a frame area 11, wherein the display area 10 is used for setting a pixel array and the frame area 11 is used for setting related wirings such as a driving circuit. The pair of GOA circuits 12 are respectively disposed in the frame regions 11 on opposite sides of the gate driver array type display panel 1. Referring to fig. 2, a partial cross-sectional view of the gate driving array type display panel 1 along the a-a section line of fig. 1 is shown. The gate driving array type display panel 1 includes a GOA circuit 12, a lower substrate 13, an upper substrate 14, an insulating layer 15, and a plastic frame 16 in a frame region 11 where the GOA circuit 12 is disposed, wherein the GOA circuit 12 includes N-level GOA units 121, a GOA bus 122, and a common electrode line 123. For a large-size and high-resolution display screen, the resistance-capacitance loading (RC loading) during signal transmission is large, so that a design with a wide GOA bus 122 is required, resulting in a large width d1 of the frame region 11. For example, in the conventional products, the width d1 of the frame area 11 is generally over 5mm, which cannot meet the requirements of consumers and lacks market competitiveness.

In view of the above, it is desirable to provide a gate driving array type display panel to solve the problems in the prior art.

Disclosure of Invention

In order to solve the above-mentioned problems of the prior art, an object of the present disclosure is to provide a gate driving array type display panel, which changes the circuit layout to change the cascaded GOA unit sets of the GOA circuits from the frame area of the display panel into the display area, so as to achieve the design of having very narrow frames on both sides of the display panel.

To achieve the above object, the present disclosure provides a gate driver array (GOA) type display panel, the GOA type display panel defining a display region and a frame region, and the GOA type display panel comprising: a plurality of pixel units arranged in an array within the display area; and a GOA circuit comprising: the GOA unit group is arranged in the display area; and the routing group is electrically connected with the GOA unit group and is arranged in the frame area, wherein the routing group comprises a GOA bus and a common electrode wire.

In one preferred embodiment of the present disclosure, the group of GOA cells is disposed along an extending direction of a long side of the gate driving array type display panel.

In one preferred embodiment of the present disclosure, the routing groups are disposed along an extending direction of short sides of the gate driving array type display panel, wherein the long sides are adjacent to the short sides.

In a preferred embodiment of the present disclosure, the group of GOA units includes a plurality of cascaded GOA units.

In one preferred embodiment of the present disclosure, each GOA cell includes a pull-up control circuit, a pull-up circuit, a pull-down sustain circuit, and a bootstrap capacitor.

In one preferred embodiment of the present disclosure, the width of the routing group is equal to a distance from a side of the routing group contacting the display region to an edge of the short side of the gate driving array type display panel.

In one preferred embodiment of the present disclosure, the width of the routing group is less than or equal to 1.2 μm.

In one preferred embodiment of the present disclosure, the gate driving array type display panel includes two sets of routing groups respectively disposed on two opposite sides of the display area, and the two sets of routing groups are respectively adjacent to edges of two short sides of the gate driving array type display panel.

In one preferred embodiment of the present disclosure, the gate driving array type display panel includes two GOA unit sets, and one of the two GOA unit sets is adjacent to an edge of the display region.

In one preferred embodiment of the present disclosure, one of the two GOA cell groups is disposed between two adjacent rows of pixel cells.

Compared with the prior art, the display area is provided with the cascaded GOA unit groups of the GOA circuit from the grid drive array type display panel, so that the design of an extremely narrow frame can be realized. Moreover, the routing group of the GOA circuit is arranged in the frame area to be separated from the data line of the pixel unit, so that the data line cannot be overlapped with the GOA bus in the longitudinal direction, and the problems that the pixel unit is not charged enough or the display picture is not uniform and the like due to large resistance-capacitance load generated when signals are transmitted on the data line and the GOA bus can be avoided.

Drawings

FIG. 1 is a schematic diagram of a prior art grid-driven array type display panel;

FIG. 2 is a partial cross-sectional view of the gate driver array type display panel of FIG. 1 along a-A section line;

FIG. 3 is a schematic diagram of a gate-driven array type display panel according to a preferred embodiment of the present disclosure; and

fig. 4 shows a schematic diagram of a GOA unit according to a preferred embodiment of the present disclosure.

Detailed Description

In order to make the aforementioned and other objects, features and advantages of the present disclosure comprehensible, preferred embodiments accompanied with figures are described in detail below.

Referring to fig. 3, a schematic diagram of a gate driving array type display panel 2 according to a preferred embodiment of the disclosure is shown. The gate driving array type display panel 2 is a display panel in which a gate driving circuit is formed on an array substrate instead of a driving chip formed from an external silicon chip. The gate-driven array display panel 2 defines a display area 20 and a frame area 21, wherein the display area 20 is an active area (active area) of the display panel for displaying images, and the frame area 21 surrounds the display area 20 to serve as a layout space for circuits and related traces.

As shown in fig. 3, the gate driving array type display panel 2 includes a GOA circuit 22 and a plurality of pixel units 25. A plurality of pixel units 25 are disposed in the display area 20 in an array form. The GOA circuit 22 includes a GOA cell group 23 and a trace group 24. The GOA unit set 23 is disposed in the display area 20, and the routing group 24 is electrically connected to the GOA unit set 23 and disposed in the frame area 21. The routing group 24 includes a GOA bus line 241 and a common electrode line 242.

As shown in fig. 3, the gate driving array type display panel 2 has a substantially rectangular outline including two opposite long sides 201 and two opposite short sides 202, wherein the long sides 201 are adjacent to the short sides 202. The GOA cell groups 23 are arranged along the extending direction X of the long side 201 of the gate drive array type display panel 2, and the routing group 24 is arranged along the extending direction Y of the short side 202 of the gate drive array type display panel 2.

As shown in fig. 3, each GOA cell group 23 includes a plurality of GOA cells, such as GOA (1), GOA (2), GOA (M-1), GOA (M), etc., where M is a positive integer greater than 1. The GOA cell group 23 is connected to the GOA bus 241 by its own signal lead. The driving signal of the display panel 2 is input from each signal input terminal, and is transmitted to the signal lead of each GOA unit of the GOA unit group 23 connected thereto through the GOA bus 241, and further reaches the clock signal input terminal of each GOA unit, so as to realize signal driving for each GOA unit.

Referring to fig. 4, a schematic diagram of a GOA unit in a preferred embodiment of the present disclosure is shown. The plurality of GOA units of the GOA unit group 23 are cascaded, and each level of GOA unit correspondingly drives one level of horizontal scanning line. The GOA unit includes a pull-up control circuit 231, a pull-up circuit 232, a pull-down circuit 233, a pull-down circuit 234, a pull-down sustain circuit 235, and a bootstrap capacitor 236 responsible for potential boosting. The pull-up control circuit 231 controls the on time of the pull-up circuit 232 to be Q (N) point to realize pre-charging, wherein N is a positive integer greater than 1. The pull-up control circuit 231 is connected to the down signal G (N-1) transmitted from the upper-level GOA unit. The pull-up circuit 232 outputs the clock signal as the gate signal g (n). The pass-down circuit 233 controls the turn-on and turn-off of the signal G (N +1) in the next-stage GOA unit. The pull-down circuit 234 is responsible for pulling the gate signal low at the first time, i.e., turning off the gate signal. The pull-down holding circuit 235 holds (holding) the point potential of q (n) in an off state (i.e., a negative potential). The bootstrap capacitor 236 raises the point q (n) twice, which is favorable for outputting the gate signal g (n) of the pull-up circuit 232.

As shown in fig. 3, the width of the routing group 24 of the GOA circuit 22 is equal to the distance from the side of the routing group 24 contacting the display area 20 to the edge of the short side 202 of the gate driving array type display panel 2. Preferably, the width of the trace group 24 is less than or equal to 1.2 micrometers. In a preferred embodiment, the present disclosure can manufacture a gate driving array type display panel 2 having a total width in the long side extending direction X equal to the width of the display region in the prior art (the width of the display region 10 of the display panel 1 shown in fig. 1, i.e., the width 2 d1 of the frame region 11 is not included), with the same resolution as that of the prior art display panel. For example, when a 4K-resolution display screen design is adopted, the gate driving array type display panel 2 includes 3840 × 3 pixel units 25 in the extending direction X of the long side. Compared with the pixel size of the conventional display panel, the pixel size is reduced by about 10%, for example, by 0.22um, and the overall layout does not significantly affect the visual effect. By this design, a total width of 3840 × 3 × 0.22um — 2304um can be obtained. The obtained width is equally distributed to the frame regions 21 on both sides of the gate drive array type display panel 2 so that the width d2 of the frame region 21 is only 1.152 μm. The width d2 of the frame area 21 is sufficient for arranging the GOA bus lines 241 and the common electrode lines 242 of the GOA circuit 22.

It should be noted that, as shown in fig. 3, the gate driving array type display panel 2 in the present embodiment adopts a dual-edge driving scheme, that is, the gate driving array type display panel 2 includes two groups of GOA cell groups 23 and two groups of routing lines 24, however, in other embodiments, different numbers of GOA cell groups 23 and routing lines 24 may be adopted, and the invention is not limited thereto. Preferably, the two sets of routing groups 24 are respectively disposed on two opposite sides of the display area 20, and the two sets of routing groups 24 are respectively adjacent to the edges of two short sides 202 of the gate driving array type display panel 2. Also, one of the two groups of GOA cell groups 23 is adjacent to the edge of the display area 20, and the other group of GOA cell groups 23 is disposed between the pixel cells 25 of two adjacent rows.

In summary, the present disclosure can realize a very narrow frame design by disposing the cascaded GOA cell groups of the GOA circuits in the display region from the gate driving array type display panel. Moreover, the routing group of the GOA circuit is arranged in the frame area to be separated from the data line of the pixel unit, so that the data line is not overlapped with the GOA bus in the longitudinal direction (Y direction), thereby avoiding the related problems of insufficient charging of the pixel unit or uneven display picture caused by the large resistance-capacitance load generated when the signal is transmitted on the data line and the GOA bus. Moreover, the uniformity of the resistance-capacitance load generated by the GOA bus can be ensured due to the consistency of the layout design of the GOA bus. In addition, the grid driving array type display panel does not need to change the existing manufacturing process and add an additional metal layer, and further the production cost can be reduced.

The foregoing is merely a preferred embodiment of the present disclosure, and it should be noted that modifications and refinements may be made by those skilled in the art without departing from the principle of the present disclosure, and these modifications and refinements should also be regarded as the protection scope of the present disclosure.