阅读说明：本技术 算术设备和乘法-累加系统 (Arithmetic apparatus and multiply-accumulate system ) 是由 吉田浩 于 2020-02-28 设计创作，主要内容包括：一种算术设备包括多个输入线和一个或多个乘法-累加装置。对应于输入值的电信号中的每一个在预定输入周期内被输入到多个输入线中。乘法-累加装置的多个乘法单元基于输入到多个输入线中的每一个的电信号,生成与通过将输入值乘以权重值而获得的乘积值相对应的电荷。乘法-累加装置的累加单元累积与多个乘法单元中的每一个生成的乘积值对应的电荷。乘法-累加装置的充电单元在输入周期后对其中累积与乘积值对应的电荷的累加单元进行充电。乘法-累加装置的输出单元在通过充电单元开始充电之后,通过使用预定阈值对累加单元保持的电压执行阈值确定,输出表示乘积值的总和的乘法-累加信号。在一个或多个乘法-累加装置中,通过充电单元的充电以共同充电模式执行,并且共同阈值被设置为预定阈值。(An arithmetic device includes a plurality of input lines and one or more multiply-accumulate means. Each of the electric signals corresponding to the input values is input into the plurality of input lines within a predetermined input period. The plurality of multiplication units of the multiply-accumulate device generate charges corresponding to product values obtained by multiplying input values by weight values, based on the electric signals input to each of the plurality of input lines. An accumulation unit of the multiply-accumulate apparatus accumulates charges corresponding to product values generated by each of a plurality of multiplication units. The charging unit of the multiply-accumulate device charges the accumulation unit in which the charge corresponding to the product value is accumulated after the input period. An output unit of the multiply-accumulate device outputs a multiply-accumulate signal representing a sum of product values by performing threshold determination on a voltage held by an accumulation unit using a predetermined threshold after charging is started by a charging unit. In one or more multiply-accumulate devices, charging by the charging unit is performed in a common charging mode, and the common threshold is set to a predetermined threshold.)

1. An arithmetic device comprising:

a plurality of input lines to each of which an electric signal corresponding to an input value is input in a predetermined input period; and

one or more multiply-accumulate units, each multiply-accumulate unit comprising

A plurality of multiplication units that generate charges corresponding to product values obtained by multiplying the input values by weight values based on the electric signals input to each of the plurality of input lines,

an accumulation unit that accumulates charges corresponding to the product value generated by each of the plurality of multiplication units,

a charging unit that charges the accumulation unit in which the electric charge corresponding to the product value is accumulated after the input period, and

an output unit that outputs a multiply-accumulate signal representing a sum of the product values by performing threshold determination on the voltage held by the accumulation unit using a predetermined threshold after charging is started by the charging unit, wherein

In the one or more multiply-accumulate devices, the charging by the charging unit is performed in a common charging mode, and a common threshold is set to the predetermined threshold.

2. Arithmetic device according to claim 1, wherein

The one or more multiply-accumulate devices are a plurality of multiply-accumulate devices connected in parallel to the plurality of input lines.

3. Arithmetic device according to claim 1, wherein

The common charging mode includes charging supplied with the same charging signal during a common charging period.

4. Arithmetic device according to claim 1, wherein

The common charging mode includes charging at a common charging speed.

5. Arithmetic device according to claim 1, wherein

The common charging mode includes charging according to a common time constant.

6. Arithmetic device according to claim 1, wherein

Defining a sum of absolute values of the weight values set in the plurality of multiplication units as a weight sum value, the common charge mode including charge based on a maximum value of the weight sum value in the one or more multiply-accumulate devices.

7. Arithmetic device according to claim 5, wherein

Each of the one or more multiply-accumulate devices includes a charge output line,

the plurality of multiplication units output charges corresponding to the product values to the charge output lines, an

The common charging mode includes charging in which a time constant associated with outputting the electric charge corresponding to the product value to the electric charge output line by the plurality of multiplication units whose sum value of weights is a maximum value is used as the common time constant.

8. Arithmetic device according to claim 1, wherein

The common threshold is set based on a duration of the input period.

9. Arithmetic device according to claim 1, wherein

Defining a sum of absolute values of the weight values set in the plurality of multiplication units as a weight sum value, the common threshold being set based on a maximum value of the weight sum values in the one or more multiply-accumulate devices.

10. Arithmetic device according to claim 1, wherein

The common charging mode includes charging supplied with the same charging signal during the common charging period, and

the charging unit includes a charging line connected to the accumulation unit and supplying the same charging signal to the accumulation unit during the common charging period.

11. Arithmetic device according to claim 1, wherein

The common charging mode includes charging supplied with the same charging signal during the common charging period, and

the charging unit supplies the same charging signal to the accumulation unit via the plurality of input lines during the common charging period.

12. Arithmetic device according to claim 1, wherein

The plurality of multiplication units include at least one of a positive weight multiplication unit that generates a positive weight charge corresponding to a product value obtained by multiplying the input value by a positive weight value and a negative weight multiplication unit that generates a negative weight charge corresponding to a product value obtained by multiplying the input value by a negative weight value,

the accumulation unit includes a positive charge accumulation unit capable of accumulating the positive weight charges generated by the positive weight multiplication unit and a negative charge accumulation unit capable of accumulating the negative weight charges generated by the negative weight multiplication unit,

the charging unit charges the positive charge accumulation unit and the negative charge accumulation unit in the common charging mode, and

the output unit outputs the multiply-accumulate signal by thresholding each of the positive charge accumulation unit and the negative charge accumulation unit using the common threshold.

13. The arithmetic device of claim 12, wherein

Defining a sum of the positive weight values set in the plurality of multiplication units as a positive sum value, and defining a sum of absolute values of the negative weight values as a negative sum value, the common charging pattern including charging based on a maximum value of the positive sum value and the negative sum value in the one or more multiply-accumulate means.

14. The arithmetic device of claim 13, wherein

Each of the one or more multiply-accumulate devices includes a positive charge output line and a negative charge output line,

the positive charge multiplying unit outputs the positive weight charges to the positive charge output line,

the negative charge multiplying unit outputs the negative weight charges to the negative charge output line, an

Assuming that the maximum value of the positive sum value and the negative sum value in the one or more multiply-accumulate devices is a maximum sum value

The positive weight charge or the negative weight charge associated with the maximum sum value is the maximum weight charge, an

The positive charge output line or the negative charge output line from which the maximum weight charge is output is a maximum charge output line,

defining a time constant associated with output of the maximum weight charges to the maximum charge output line as a common time constant, the common charging mode including charging according to the common time constant.

15. The arithmetic device of claim 12, wherein

Defining a sum of the positive weight values set in the plurality of multiplication units as a positive sum value, and defining a sum of absolute values of the negative weight values as a negative sum value, the common threshold being set based on a maximum value of the positive sum value and the negative sum value in the one or more multiply-accumulate means.

16. The arithmetic device of claim 12, wherein

Absolute values of the positive weight value and the negative weight value are fixed to the same value, set to any one of a plurality of values different from each other, or randomly set, and

in the one or more multiply-accumulate means, a value obtained by adding the positive sum value and the negative sum value is a common value.

17. The arithmetic device of claim 12, wherein

Absolute values of the positive weight value and the negative weight value are fixed to the same value, set to any one of a plurality of values different from each other, or randomly set, and

in the one or more multiply-accumulate means, a value obtained by adding the positive sum value and the negative sum value is a random value.

18. The arithmetic device of claim 12, wherein

The common charging mode includes charging supplied with the same charging signal during the common charging period, and

the charging unit includes charging lines connected to the positive charge accumulation unit and the negative charge accumulation unit and supplying the same charging signal to the positive charge accumulation unit and the negative charge accumulation unit during the common charging period.

19. The arithmetic device of claim 12, wherein

The common charging mode includes charging supplied with the same charging signal during the common charging period, and

the charging unit supplies the same charging signal to the positive charge accumulating unit and the negative charge accumulating unit via the plurality of input lines during the common charging period.

20. A multiply-accumulate system comprising:

a plurality of input lines to each of which an electric signal corresponding to an input value is input in a predetermined input period;

one or more analog circuits, each analog circuit comprising

A plurality of multiplication units that generate charges corresponding to product values obtained by multiplying the input values by weight values based on the electric signals input to each of the plurality of input lines,

an accumulation unit that accumulates charges corresponding to the product value generated by each of the plurality of multiplication units,

a charging unit that charges the accumulation unit in which the electric charge corresponding to the product value is accumulated after the input period, and

an output unit that outputs a multiply-accumulate signal representing a sum of the product values by performing threshold determination on the voltage held by the accumulation unit using a predetermined threshold after charging is started by the charging unit; and

a network circuit configured by connecting a plurality of analog circuits, wherein

In the one or more analog circuits, charging by the charging unit is performed in a common charging mode, and a common threshold is set to the predetermined threshold.

Technical Field

The present technology relates to an arithmetic device and a multiply-accumulate system applicable to multiply-accumulate operations using an analog method.

Background

Conventionally, techniques for performing multiply-accumulate operations have been developed. The multiply-accumulate operation is an operation of multiplying each of a plurality of input values by a weight and adding the multiplication results to each other, and is used for processing for recognizing an image, voice, or the like by a neural network or the like, for example.

For example, patent document 1 describes an analog circuit in which a multiply-accumulate process is performed in an analog manner. In the analog circuit, a weight corresponding to each of the plurality of electric signals is set. Further, the electric charges according to the corresponding electric signals and the weights are respectively output, and the output electric charges are appropriately accumulated in the capacitors. The value representing the multiply-accumulate result to be calculated is calculated based on the voltage of the capacitor in which the electric charge is accumulated. Therefore, power consumption required for multiply-accumulate operations can be reduced compared to, for example, digital processing (paragraphs [0003], [0049] to [0053], and [0062] of patent document 1, fig. 3, and the like).

CITATION LIST

Patent document

Patent document 1: WO 2018/034163

Disclosure of Invention

Technical problem

It is desirable to reduce power consumption of a neural network or the like by using such an analog circuit, and to provide a technique for realizing efficient and high-speed arithmetic processing.

In view of the above-described circumstances, it is an object of the present technology to provide an arithmetic apparatus, a multiply-accumulate system, and a setting method, by which efficient and high-speed operation processing can be realized in an analog circuit that performs a multiply-accumulate operation.

Solution to the problem

To achieve the above object, an arithmetic device according to an embodiment of the present technology includes a plurality of input lines and one or more multiply-accumulate apparatuses.

Each of the electric signals corresponding to the input values is input into the plurality of input lines within a predetermined input period.

The one or more multiply-accumulate devices each include a plurality of multiplication units, an accumulation unit, a charging unit, and an output unit.

The plurality of multiplication units generate charges corresponding to a product value obtained by multiplying an input value by a weight value based on an electric signal input to each of the plurality of input lines.

The accumulation unit accumulates charges corresponding to the product value generated by each of the plurality of multiplication units.

After the input period, the charging unit charges the accumulation unit in which the electric charge corresponding to the product value is accumulated.

After the charging is started by the charging unit, the output unit outputs a multiply-accumulate signal representing the sum of the product values by performing threshold determination on the voltage held by the accumulation unit using a predetermined threshold.

Further, in the one or more multiply-accumulate devices, the charging by the charging unit is performed in a common charging mode, and the common threshold is set to a predetermined threshold.

In the arithmetic device, charging is performed in a common charging mode with respect to one or more multiply-accumulate means, and threshold determination is performed by using a common threshold. Therefore, efficient and high-speed arithmetic processing can be realized in an analog circuit that performs multiply-accumulate-operation.

The one or more multiply-accumulate devices may be a plurality of multiply-accumulate devices connected in parallel to the plurality of input lines.

The common charging mode may include charging supplied with the same charging signal during the common charging period.

The common charging mode may include charging at a common charging speed.

The common charging mode may include charging according to a common time constant.

The common charge mode may include a charge based on a maximum value of the weight sum values in the one or more multiply-accumulate devices, with a sum of absolute values of the weight values set in the plurality of multiplication units being defined as a weight sum value.

Each of the one or more multiply-accumulate devices may include a charge output line. In this case, the plurality of multiplication units may output charges corresponding to the product values to the charge output lines. Further, the common charge mode may include charge in which a time constant associated with outputting the electric charge corresponding to the product value to the electric charge output line by a plurality of multiplication units whose weight sum value is a maximum value is used as the common time constant.

The common threshold may be set based on the duration of the input period.

The sum of the absolute values of the weight values set in the plurality of multiplication units is defined as a weight sum value, and the common threshold value may be set based on the maximum value of the weight sum values in the one or more multiply-accumulate devices.

The common charging mode may include charging supplied with the same charging signal during the common charging period. In this case, the charging unit may include charging lines connected to the accumulation unit and providing the same charging signal to the accumulation unit during a common charging period.

The common charging mode may include charging supplied with the same charging signal during the common charging period. In this case, the charging unit may supply the same charging signal to the accumulation unit via the plurality of input lines during the common charging period.

The plurality of multiplication units may include at least one of a positive weight multiplication unit that generates a positive weight charge corresponding to a product value obtained by multiplying the input value by a positive weight value, and a negative weight multiplication unit that generates a negative weight charge corresponding to a product value obtained by multiplying the input value by a negative weight value. In this case, the accumulation unit may include a positive charge accumulation unit capable of accumulating the positive weight charges generated by the positive weight multiplication unit and a negative charge accumulation unit capable of accumulating the negative weight charges generated by the negative weight multiplication unit. In addition, the charging unit may charge the positive charge accumulation unit and the negative charge accumulation unit in a common charging mode. Further, the output unit may output the multiply-accumulate signal by thresholding each of the positive charge accumulation unit and the negative charge accumulation unit using a common threshold.

The common charge mode may include charging based on a maximum value of the positive sum value and the negative sum value in the one or more multiply-accumulate means, with a sum of the positive weight values set in the plurality of multiplication units defined as a positive sum value, and a sum of absolute values of the negative weight values defined as a negative sum value.

Each of the one or more multiply-accumulate devices may include a positive charge output line and a negative charge output line. In this case, the positive charge multiplying unit may output the positive weight charges to the positive charge output line. Further, the negative charge multiplying unit may output the negative weight charges to the negative charge output line. Further, assuming that the maximum value of the positive sum value and the negative sum value in the one or more multiply-accumulate means is the maximum sum value, the positive weight charge or the negative weight charge associated with the maximum sum value is the maximum weight charge, and the positive charge output line or the negative charge output line from which the maximum weight charge is output is the maximum charge output line; the time constant associated with the output of the maximum weight charge to the maximum charge output line is defined as a common time constant, and the common charging mode may include charging according to the common time constant.

A sum of the positive weight values set in the plurality of multiplication units is defined as a positive sum value, and a sum of absolute values of the negative weight values is defined as a negative sum value, and the common threshold value may be set based on a maximum value of the positive sum value and the negative sum value in the one or more multiply-accumulate means.

The absolute values of the positive weight value and the negative weight value may be fixed to the same value, set to any one of a plurality of values different from each other, or randomly set. In this case, in one or more multiply-accumulate devices, a value obtained by adding a positive sum value and a negative sum value may be a common value.

The absolute values of the positive weight value and the negative weight value may be fixed to the same value, set to any one of a plurality of values different from each other, or randomly set. In this case, in one or more multiply-accumulate devices, a value obtained by adding a positive sum value and a negative sum value may be a random value.

The common charging mode may include charging supplied with the same charging signal during the common charging period. In this case, the charging unit may include charging lines connected to the positive charge accumulation unit and the negative charge accumulation unit and supplying the same charging signal to the positive charge accumulation unit and the negative charge accumulation unit during a common charging period.

The common charging mode may include charging supplied with the same charging signal during the common charging period. In this case, the charging unit may supply the same charging signal to the positive charge accumulation unit and the negative charge accumulation unit via a plurality of input lines during a common charging period.

A multiply-accumulate system in accordance with embodiments of the present technique includes a plurality of input lines, one or more analog circuits, and a network circuit.

The one or more analog circuits include a plurality of multiplication units, an accumulation unit, a charging unit, and an output unit.

The network circuit is configured by connecting a plurality of analog circuits.

Further, in the one or more analog circuits, the charging by the charging unit is performed in a common charging mode, and the common threshold is set to a predetermined threshold.

Drawings

Fig. 1 is a schematic diagram showing a configuration example of an arithmetic device according to an embodiment of the present technology.

Fig. 2 shows a schematic diagram of an example of an electrical signal to be input into an analog circuit.

Fig. 3 is a schematic diagram showing a specific configuration example of an arithmetic device.

Fig. 4 shows a schematic diagram of a configuration example of a neuron circuit.

Fig. 5 is a schematic circuit diagram showing an example of an analog circuit of the PWM method.

Fig. 6 is a diagram for describing a calculation example of the multiply-accumulate signal of the analog circuit shown in fig. 5.

Fig. 7 shows a calculation example of the multiply-accumulate signal, showing a schematic diagram of the entire multiply-accumulate result.

Fig. 8 shows a schematic circuit diagram of an example of an analog circuit according to the TACT method.

Fig. 9 is a schematic graph for describing the potential of each output line at the end of the input period.

Fig. 10 is a diagram showing a configuration example of an arithmetic device including a plurality of analog circuits according to the PWM method.

Fig. 11 is a diagram showing a configuration example of an arithmetic device including a plurality of analog circuits according to the PWM method.

Fig. 12 is a diagram showing a configuration example of an arithmetic device including a plurality of analog circuits according to the TACT method.

Fig. 13 is a diagram showing a configuration example of an arithmetic device including a plurality of analog circuits according to the TACT method.

Fig. 14 shows a schematic diagram of a configuration example of a neural network.

Fig. 15 shows a schematic circuit diagram of another example of an analog circuit according to the PWM method.

Fig. 16 shows a schematic circuit diagram of another example of an analog circuit according to the PWM method.

Fig. 17 is a diagram for describing a calculation example of the multiply-accumulate signal according to the analog circuit shown in fig. 16.

Detailed Description

Hereinafter, embodiments according to the present technology will be described with reference to the drawings.

[ configuration of arithmetic device ]

Fig. 1 is a schematic diagram showing a configuration example of an arithmetic device according to an embodiment of the present technology. The arithmetic device 100 is an analog type arithmetic device that performs predetermined arithmetic processing including a multiply-accumulate operation. For example, by using the arithmetic device 100, arithmetic processing can be performed according to a mathematical model such as a neural network.

The arithmetic device 100 includes a plurality of signal lines 1, a plurality of input units 2, and a plurality of analog circuits 3. Each of the signal lines 1 is a line that transmits a predetermined type of electric signal. For example, an analog signal representing a signal value by using analog quantities such as pulse timing and pulse width is used as the electric signal. The direction of electrical signal transmission is schematically shown in fig. 1 by means of arrows. In the present embodiment, the analog circuit 3 corresponds to a multiply-accumulate device.

For example, a plurality of signal lines 1 are connected to one analog circuit 3. The signal line 1 that transmits an electric signal to the analog circuit 3 is an input signal line into which an electric signal is input for the analog circuit 3 connected to the signal line 1. Further, the signal line 1 that transmits the electric signal output from the analog circuit 3 is an output signal line from which an electric signal is output for the analog circuit 3 connected to the signal line 1. In the present embodiment, the input signal line corresponds to the input line.

The plurality of input units 2 each generate a plurality of electrical signals corresponding to input data 4. The input data 4 is, for example, data to be processed using a neural network or the like implemented by the arithmetic device 100. Therefore, it can also be said that the respective signal values of the plurality of electric signals corresponding to the input data 4 are input values of the arithmetic device 100.

For example, arbitrary data such as image data, audio data, and statistical data to be processed by the arithmetic device 100 is used as the input data 4. For example, in the case where image data is used as the input data 4, an electric signal using a pixel value (RGB value, luminance value, or the like) of each pixel of the image data as a signal value is generated. Further, the electric signal corresponding to the input data 4 can be appropriately generated according to the type of the input data 4 and the content of the processing performed by the arithmetic device 100.

The analog circuit 3 is an analog circuit that performs a multiply-accumulate operation based on an input electric signal. The multiply-accumulate operation is, for example, an operation of adding a plurality of product values obtained by multiplying a plurality of input values by weight values corresponding to the input values. Therefore, it can also be said that the multiply-accumulate operation is a process of calculating the sum of product values (hereinafter referred to as a multiply-accumulate result).

As shown in fig. 1, a plurality of input signal lines are connected to one analog circuit 3 and a plurality of electric signals are supplied thereto. According to the present embodiment, a plurality of input signal lines and an analog circuit constitute a multiply-accumulate operation circuit. Further, a plurality of electric signals are input from each of the input signal lines, and thus the multiply-accumulate method according to the present embodiment is performed by a multiply-accumulate operation circuit (analog circuit 3).

Hereinafter, it is assumed that the total number of electric signals input to one analog circuit 3 is N. It should be noted that the number N of electric signals to be input to each analog circuit 3 is set appropriately for each circuit according to, for example, a model of arithmetic processing, precision, and the like.

In the analog circuit 3, for example, w is calculated_i*x_iA signal value x represented by an electric signal inputted from the i-th input signal line_iAnd corresponds to the signal value x_iWeight value w of_iThe product value of (c). Here, i represents a natural number equal to or less than N (i ═ 1,2, … …, N). The product value operation is performed for each electric signal (input signal line), and N product values are calculated. A value obtained by adding N product values is calculated as a multiply-accumulate result (sum of N product values). Therefore, the multiply-accumulate result calculated by one analog circuit 3 is represented by the following expression.

[ equation 1]

Weight value w_iIs set at, for example, -alpha ≦ w_iThe range of not more than + alpha. Here, α represents an arbitrary real value. Thus, the weight value w_iMay include a positive weight value w_iA negative weight value w_iZero weight value w_iAnd the like. As described above, by weighting the value w_iSetting to be within the predetermined range, a case where the multiplication-accumulation result diverges can be avoided.

Further, for example, a weight value w may be set_iThe range of (a) is normalized. In this case, the weight value w_iIs set at-1 or less w_iLess than or equal to 1. Thus, for example, the maximum value, the minimum value, or the like of the multiply-accumulate result may be adjusted, and the multiply-accumulate operation may be performed with a desired accuracy.

In a neural network or the like, a method called binary concatenation, which weights values w_iSet to + α or- α. Binary concatenation is used in various fields, such as image recognition using deep neural networks (multilayer neural networks). Using binary concatenation may simplify the weight values w_iWithout lowering the recognition accuracy and the like. In binary concatenation, the absolute values of the positive and negative weight values are fixed to the same value.

As described above, in binary concatenation, the weight value w_iIs binarized to a binary value (± α). Thus, for example, the weight value w can be determined by_iEasily setting a desired weight value w by changing to positive or negative_i. Optionally, a binarized weight value w_iMay be normalized and weighted by a weight value w_iMay be set to ± 1.

In addition, the weight value w_iMay be multivalued. In this case, the weight value w is set by selecting from a plurality of discrete weight value candidates_i. Examples of the weight value candidates include (-3, -2, -1,0,1,2,3) and (1,2,5, 10). Further, normalized weight value candidates (-1, -0.5,0,0.5,1), or the like may be used. Selects one value from these weight value candidates and sets it as the weight value w_i. Number and setting of weight value candidatesThe method of setting the candidate value and the like are not limited. For example, by weighting the value w_iMultivalued, a neural network with high versatility can be constructed, and the like.

In addition, the weight value w_iThe setting range, the setting value, and the like of (a) are not limited, and may be appropriately set to achieve a desired processing accuracy, for example. For example, the weight value w may be set randomly_i。

Signal value x_iFor example, an electric signal output from the input unit 2 and a multiply-accumulate result output from the analog circuit 3. In this way, it can also be said that the input unit 2 and the analog circuit 3 function to output the signal value x_iThe signal source of (2).

In the example shown in fig. 1, a single electric signal (single signal value x) is output from one signal source (input unit 2, analog circuit 3)_i). Therefore, the same electrical signal is input to each of the plurality of signal lines 1 connected to the output side of one signal source. Further, one signal source and the analog circuit 3 into which an electric signal output from the signal source is input are connected to each other through a single input signal line.

Thus, for example, the M input signal lines are connected to the analog circuit 3 connected to the M signal sources in the arithmetic device 100 shown in fig. 1. In this case, the total number N of electric signals input to the analog circuit 3 is N ═ M. It should be noted that, therein, a pair of electric signals (a pair of signal values x) corresponding to a positive value and a negative value are outputted from one signal source_i ⁺、x_i ^-) Are possible.

As shown in fig. 1, the arithmetic device 100 has a layered structure in which a plurality of analog circuits 3 are provided in each of a plurality of layers. By configuring the layer structure of the analog circuit 3, for example, a multilayer perceptron type neural network or the like is constructed. For example, the number of analog circuits provided in each layer, the number of layers, and the like are appropriately designed so that desired processing can be performed. Hereinafter, the number of analog circuits 3 provided in the j-th layer is sometimes referred to as N_j。

For example, N electric signals generated by N input units 2 are input to a circuit provided in the circuitIn each analog circuit 3 in the layer of the first stage (the lowest layer). The analog circuit 3 of the first stage calculates and inputs the signal value x of the data_iThe associated multiply-accumulate result is not output to the analog circuit 3 of the next layer (second stage) after the linear conversion processing.

N representing respective multiply-accumulate results calculated in a first stage₁The respective electric signals are inputted into the respective analog circuits 3 provided in the second layer (upper layer). Thus, from the viewpoint of the analog circuit 3 of the second stage, the result of the nonlinear conversion processing of the corresponding multiply-accumulate result calculated in the first stage is the signal value x of the electric signal_i. The analog circuit 3 of the second stage calculates the signal value x output from the first stage_iAnd outputs the calculated multiply-accumulate result to the analog circuit 3 of the upper layer.

In this way, in the arithmetic apparatus 100, the multiply-accumulate result of the analog circuit 3 in the upper layer is calculated based on the multiply-accumulate result calculated by the analog circuit 3 in the lower layer. Such processing is performed a plurality of times, and the processing result is output from the analog circuit 3 included in the top layer (the layer of the third stage in fig. 1). Thus, for example, processing such as image recognition that determines that the object is a cat may be performed based on image data (input data 4) obtained by imaging a cat.

As described above, a desired network circuit can be configured by appropriately connecting a plurality of analog circuits 3. The network circuit functions as a data stream processing system that performs arithmetic processing by, for example, passing a signal therethrough. In the network circuit, various processing functions can be realized by appropriately setting, for example, a weight value (synaptic connection). Through this network circuit, the multiply-accumulate system of the present embodiment is constructed.

It should be noted that a method of connecting the analog circuits 3 to each other, and the like are not limited, and for example, a plurality of analog circuits 3 may also be connected to each other as appropriate so that desired processing can be performed. For example, even in the case where the analog circuits 3 are connected to each other to configure another structure different from the hierarchical structure, the present technology can be applied.

In the above description, the configuration in which the multiply-accumulate result calculated at the lower layer is input to the upper layer as it is has been described. The present technique is not limited to this, and for example, conversion processing or the like may be performed on the multiply-accumulate result. For example, in the neural network model, a process of nonlinearly converting the multiply-accumulate result of each analog circuit 3 by using an activation function, for example, and inputting the conversion result to an upper layer is performed.

In the arithmetic device 100, for example, a function circuit 5 or the like that performs nonlinear conversion on an electric signal using an activation function is used. The function circuit 5 is, for example, a circuit which is provided between a lower layer and an upper layer and which appropriately converts a signal value of an input electric signal and outputs the electric signal according to the conversion result. For example, the function circuit 5 is provided for each of the signal lines 1. The number of function circuits 5, the arrangement of the function circuits 5, and the like are appropriately set according to, for example, a mathematical model implemented in the arithmetic device 100.

For example, a ReLU function (ramp function) or the like is used as the activation function. ReLU function, e.g. at signal value x_iOutput signal value x as is in the case of 0 or more_iOtherwise, 0 is output. For example, a function circuit 5 that implements a ReLU function is appropriately connected to each of the signal lines 1. Thus, the processing of the arithmetic device 100 can be realized.

Fig. 2 is a schematic diagram showing an example of an electric signal input into the analog circuit 3. In each of a and B of fig. 2, a graph representing waveforms of a plurality of electric signals is schematically shown. The horizontal axis of the graph represents a time axis, and the vertical axis represents the voltage of the electric signal.

An exemplary waveform of the electric signal according to a Pulse Width Modulation (PWM) method is shown in a of fig. 2. For example, the PWM method is by using the pulse width τ of the pulse waveform_iTo represent the signal value x_iThe method of (1). That is, in the PWM method, the pulse width τ of the electric signal_iIs dependent on the signal value x_iLength of (d).

Generally, the pulse width τ_iThe longer the signal value x_iThe higher.

Further, the electric signal is input to the analog circuit 3 for a predetermined input period T. More specifically, the respective electric signals are input into the analog circuit 3 so that the pulse waveforms of the electric signals fall within the input period T. Therefore, the maximum value of the pulse width of the electric signal is similar to the input period T. It should be noted that the timing or the like of each pulse waveform (electric signal) input is not limited as long as the pulse waveform falls within the input period T.

In the PWM method, for example, a pulse width τ may be used_iDuty ratio R to input period T_i(＝τ_i/T) to normalize the signal value x_i. I.e. the normalized signal value x_iIs represented as a signal value x_i＝R_i. It should be noted that the signal value x is set_iAnd pulse width τ_iThe associated method is not limited, and for example, the representative signal value x may be set appropriately_iPulse width τ of_iThereby making it possible to perform calculation processing and the like with desired accuracy.

In the case of using the electric signal according to the PWM method, a time axis analog multiplication-accumulation operation using the analog circuit 3 according to the PWM method can be performed.

In B of fig. 2, an exemplary waveform of an electric signal of a spike timing method (hereinafter referred to as a TACT method) is shown. For example, the TACT method is to represent a signal value x by using the rising timing of a pulse_iThe method of (1). For example, by using a predetermined timing as a reference, a pulse is input at a timing corresponding to an input value.

The electric signal is input to the analog circuit 3 for a predetermined input period T. Signal value x_iIndicated by the pulse input timing within the input period T. E.g. maximum signal value x_iIndicated by a pulse input at the same time as the start of the input period T. Minimum signal value x_iIndicated by the pulse input at the same time as the end of the input period T.

It can also be said that the signal value x_iRepresented by the duration from the input timing of the pulse to the end timing of the input period T. For example, the maximum signal value x_iRepresented by one pulse, the duration of the pulse from the input timing of the pulse to the end timing of the input period T is equal to the input period T.Minimum signal value x_iRepresented by one pulse, the duration of which from the input timing of the pulse to the end timing of the input period T is 0.

It should be noted that, in B of fig. 2, a continuous pulse signal that rises to a timing corresponding to an input value and holds the ON level until a multiplication-accumulation result is obtained is used as the electric signal according to the TACT method. The present technology is not limited thereto, and a rectangular pulse or the like having a predetermined pulse width may be used as the electric signal according to the TACT method.

In the case of using the electric signal according to the TACT method, a time axis analog multiplication-accumulation operation using the analog circuit 3 according to the TACT method can be performed.

As shown in a and B of fig. 2, a pulse signal whose duration with respect to the ON time of the input period T corresponds to an input value may be used as the electric signal corresponding to the input value. It should be noted that the signal value x represented by each electrical signal will be assumed hereinafter_iVariables from 0 to 1 are described.

Fig. 3 is a schematic diagram showing a specific configuration example of the arithmetic device 100. Fig. 3 is an example of arrangement of a circuit for realizing the arithmetic device 100 shown in fig. 1, for example, schematically showing a plurality of analog circuits 3 provided in one layer of the arithmetic device 100.

Each analog circuit 3 includes a pair of output lines 7, a plurality of synaptic circuits 8, and a neuron circuit 9. As shown in fig. 3, one analog circuit 3 is configured to extend in a predetermined direction (vertical direction in the figure). A plurality of such analog circuits 3 extending in the vertical direction are arranged side by side in the horizontal direction, thereby forming one layer. In the following, it is assumed that the leftmost analog circuit 3 in the figure is the first analog circuit 3. The direction in which the analog circuit 3 extends is sometimes referred to as the extending direction.

A pair of output wires 7 are spaced apart from each other in the extending direction. The pair of output lines 7 includes a positive charge output line 7a and a negative charge output line 7 b. Each of the positive charge output line 7a and the negative charge output line 7b is connected to a neuron circuit 9 via a plurality of synapse circuits 8.

The synaptic electrical circuit 8 calculates a signal value x represented by the electrical signal_iAnd weight value w_iValue of (w)_i*x_i). Specifically, the electric charge (current) corresponding to the product value is output to the positive charge output line 7a or the negative charge output line 7 b.

As will be described later, the positive weight value w_i ⁺Or a negative weight value w_i ^-Is set to the synaptic electrical circuit 8. For example, corresponding to a positive weight value w_i ⁺The positive weight charge of the product value of (a) is output to the positive charge output line 7 a. Further, for example, corresponding to a negative weight value w_i ^-The negative weight charge of the product value of (b) is output to the negative charge output line 7 b.

It should be noted that in the synaptic electrical circuit 8, the weight value w is not critical_iWhether positive or negative, a charge (e.g., positive charge) having the same sign is output as a charge corresponding to the product value. That is, the positive weight charges and the negative weight charges become charges having the same sign.

In this way, each of the synaptic electrical circuits 8 is configured to be dependent on the weight value w_iOutputs the electric charge corresponding to the multiplication result to a different output line 7a or 7 b. The specific configuration of the synaptic electrical circuit 8 will be described in detail later. In this embodiment, the plurality of synapse circuits 8 function as a plurality of multiplication units that generate charges corresponding to product values obtained by multiplying input values by weight values based on electrical signals input to each of a plurality of input lines.

In this embodiment, a single input signal line 6 and a pair of output lines 7 are connected to a single synaptic electrical circuit 8. That is, a single electrical signal is input to the single synapse circuit 8, and a charge corresponding to a product value calculated based on the input electrical signal is output to the output line 7a or 7 b. Therefore, the synapse circuit 8 is a single-input dual-output circuit connected to a single input signal line 6 and a pair of output lines 7 (a positive charge output line 7a and a negative charge output line 7 b).

In one analog circuit 3, a plurality of synaptic electrical circuits 8 are arranged along a pair of output lines 7. Each synapse circuit 8 is connected in parallel to a positive charge output line 7a (negative charge output line 7 b). Hereinafter, it is assumed that the synapse circuit 8 disposed on the most downstream side (the side connected to the neuron circuit 9) is the first synapse circuit.

As shown in fig. 3, the plurality of input signal lines 6 are wired to intersect a pair of output lines 7 of each of the plurality of analog circuits 3. Typically, the input signal line 6 is arranged orthogonal to each output line 7. That is, the arithmetic device 100 has a crossbar configuration (crossbar configuration) in which the input signal line 6 and the output line 7 cross each other. By the vertical and horizontal arrangement, for example, the analog circuit 3 and the like can be integrated at high density.

Further, in the arithmetic device 100, the jth synapse circuit 8 included in the respective analog circuits 3 is connected in parallel to the jth input signal line 6. Thus, similar electrical signals are input to the synaptic electrical circuits 8 connected to the same input signal line 6. Therefore, a configuration of connecting one signal source contained in the lower layer to a plurality of analog circuits 3 contained in the upper layer can be realized.

It should be noted that, in the example shown in fig. 3, the analog circuit 3 (pre-neuron) included in the lower layer is schematically shown as a signal source that inputs an electric signal into each input signal line 6. The present technology is not limited to this, and for example, a crossbar configuration may also be used in the case where the input unit 2 is used as a signal source.

As described above, in the arithmetic device 100, the plurality of analog circuits 3 are connected in parallel to each of the plurality of input signal lines 6. Thus, for example, it is possible to input an electrical signal in parallel into each analog circuit 3 (each synapse circuit 8) and realize high-speed arithmetic processing. Therefore, excellent operation performance can be exhibited.

The neuron circuit 9 calculates a multiply-accumulate result shown by expression (formula 1) based on the product value calculated by the synapse circuit 8. Specifically, the neuron element circuit 9 outputs an electric signal representing a multiply-accumulate result (multiply-accumulate signal) based on electric charges input via the pair of output lines 7.

Fig. 4 is a schematic diagram showing a configuration example of the neuron circuit 9. The neuron element circuit 9 includes an accumulation unit 11 and a signal output unit 12. Fig. 4 shows a two-input single-output neuron circuit 9 connected to a pair of output lines 7 and a single output signal line 10. It should be noted that, in some cases, a two-input two-output circuit or the like may be used as the neuron circuit 9.

The accumulation unit 11 accumulates the electric charges output to the pair of output lines 7 by the plurality of synapse circuits 8. The accumulation unit 11 includes two capacitors 13a and 13 b. The capacitor 13a is connected between the positive charge output line 7a and GND. Further, a capacitor 13b is connected between the negative charge output line 7b and GND. Accordingly, the charges flowing in from the positive charge output line 7a and the negative charge output line 7b are accumulated in the capacitors 13a and 13b, respectively.

For example, when the input period T of the electric signal has elapsed, the electric charge accumulated in the capacitor 13a is the sum σ of the positive weight electric charges⁺Each positive weight charge corresponds to a positive weight value w_i ⁺The product value of (c). Further, the electric charge accumulated in the capacitor 13b is a value corresponding to a negative weight w_i ^-Sum σ of negative weight charges of product values of (c)^-。

For example, when positive weight charges are accumulated in the capacitor 13a, the potential of the positive charge output line 7a with reference to GND rises. Therefore, the potential of the positive charge output line 7a depends on the positive weight values w respectively corresponding to the positive weight values_i ⁺The sum of the charges of the product values of (a) (-), (a)⁺The value of (c). It should be noted that the potential of the positive charge output line 7a corresponds to the voltage held by the capacitor 13 a.

Similarly, in the case where negative weight charges are accumulated in the capacitor 13b, the potential of the negative charge output line 7b with GND as a reference rises. Therefore, the potential of the negative charge output line 7b depends on the potentials respectively corresponding to the negative weight values w_i ^-The sum of the charges of the product values of (a) (-), (a)^-The value of (c). It should be noted that the potential of the negative charge output line 7b corresponds to the voltage held by the capacitor 13 b.

The signal output unit 12 outputs a value (w) representing the product based on the electric charges accumulated in the accumulation unit 11_i ⁺*x_i) Multiply-accumulate the signal of the sum. The multiply-accumulate signal is, for example, a signal representing the total multiply-accumulate result, which is all positive and negative weight values w_iAnd the signal value x_iThe sum of the product values of (c). For example, by the expression (equation 1)) The expressed multiply-accumulate result can be written as follows.

[ formula 2]

Here, N⁺And N^-Respectively a positive weight value w_i ⁺Total number of (2) and negative weight value w_i ^-The total number of (c). As shown in the expression (equation 2), the total multiply-accumulate result can be calculated as a multiply-accumulate result of a positive weight charge (i.e., a positive weight value w)_i ⁺Value of (w)_i ⁺*x_i) Sum of) and a negative weight charge (i.e., a negative weight value w)_i ^-Value of the product (| w)_i ^-|*x_i) The sum of (d) of the first and second images.

In the example shown in fig. 4, the signal output unit 12 generates a signal representing the total multiply-accumulate result, for example, as a multiply-accumulate signal. Specifically, by appropriately referring to the electric charges accumulated in the accumulation unit 11 (the capacitors 13a and 13b), the positive multiply-accumulate result and the negative multiply-accumulate result are calculated, and the total multiply-accumulate result is calculated based on the difference therebetween. Further, for example, two signals of a positive multiply-accumulate signal and a negative multiply-accumulate signal representing a positive multiply-accumulate result and a negative multiply-accumulate result, respectively, may be generated as the multiply-accumulate signal.

A method of referring to the electric charges accumulated in the accumulation unit 11 is not limited. As an example, a method of detecting the electric charge accumulated in one capacitor 13 will be described. In the case of using the electric signal according to the PWM method shown in a of fig. 2, charges each corresponding to a product value are accumulated in the capacitor 13 within the input period T. That is, accumulation of electric charges each corresponding to a product value does not occur before and after the input period T.

For example, after the input period T ends, the capacitor 13 is charged at a predetermined charging speed. At this time, a comparator or the like is used to detect the timing at which the potential of the output line connected to the capacitor 13 reaches a predetermined threshold potential. For example, as more electric charges are accumulated at the start of charging, the time at which the potential reaches the threshold potential becomes earlier. Therefore, the charge accumulated in the input period T (multiply-accumulate result) can be represented based on the timing. It should be noted that the charging speed may be expressed, for example, in terms of a charge amount per unit time, and may also be referred to as a charging rate.

It should be noted that the threshold determination corresponds to increasing the voltage held by the capacitor 13 by charging and detecting the timing of reaching the threshold voltage.

In the case of using the electric signal according to the TACT method shown in B of fig. 2, since the ON level is also maintained after the end of the input period T, electric charges are accumulated in the capacitor 13. For such charge accumulation, the timing at which the potential of the output line connected to the capacitor 13 reaches a predetermined threshold potential is detected by using a comparator or the like. For example, as more electric charges are accumulated at the end of the input period T, the time at which the potential reaches the threshold potential becomes earlier. Therefore, the charge accumulated in the input period T (multiply-accumulate result) can be represented based on the timing.

It should be noted that the threshold determination corresponds to the timing at which the voltage held by the detection capacitor 13 reaches the threshold voltage.

For example, by performing such threshold determination, the timing representing the multiply-accumulate result is detected. The multiply-accumulate signal of the positive weight charge, the multiply-accumulate signal of the negative weight charge, or the total multiply-accumulate signal is appropriately generated based on the detection result. In addition, each multiply-accumulate result can be calculated, for example, by directly reading the potential of the capacitor 13 at the end of the input period T.

It should be noted that the voltage depending on the accumulated positive-weight charges and the voltage depending on the accumulated negative-weight charges may be amplified respectively to generate multiply-accumulate signals. Further, the multiply-accumulate signal may be generated by amplifying a differential voltage between a voltage depending on the accumulated positive weight charges and a voltage depending on the accumulated negative weight charges. For example, a differential amplifier or the like having an arbitrary configuration may be provided in the neuron element circuit 9.

In the present embodiment, the neuron element circuit 9 functions as an output unit that accumulates charges corresponding to product values generated by a plurality of multiplication units and outputs a multiply-accumulate signal representing the sum of the product values based on the accumulated charges. In addition, the capacitor 13a and the capacitor 13b function as a positive charge accumulation unit and a negative charge accumulation unit. The neuron element circuit 9 accumulates at least one of the positive weight charges generated by the positive weight multiplication unit and the negative weight charges generated by the negative weight multiplication unit, thereby outputting a multiply-accumulate signal.

Further, as will be described later in detail, in the present embodiment, a charging unit is configured, and the accumulation unit 11 (capacitor 13) in which the electric charge corresponding to the product value is accumulated is charged after the input period T. It should be noted that the charging according to the present technique includes accumulating charges in the capacitor 13 by a pulse signal that maintains an ON level in the case of using the electric signal according to the TACT method.

The signal output unit 12 functions as an output unit for outputting a multiply-accumulate signal representing the sum of product values by threshold-determining the voltage held by the accumulation unit 11 after the charging unit starts charging using a predetermined threshold. The signal output unit 12 outputs a multiply-accumulate signal by performing threshold determination for each of the positive charge accumulation unit and the negative charge accumulation unit.

[ analog Circuit according to PWM method ]

Fig. 5 is a schematic circuit diagram showing an example of an analog circuit according to the present embodiment. In fig. 5, an example of the analog circuit 3 according to the PWM method is shown. The analog circuit 3 is provided to extend in a direction orthogonal to the plurality of input signal lines 6. That is, in the example shown in fig. 5, a vertical and horizontal arrangement is adopted.

The analog circuit 3 includes a pair of output lines (a positive charge output line 7a and a negative charge output line 7b), a plurality of synapse circuits (a plurality of multiplication units) 8, a neuron circuit 9, and a charging unit 15. In the example shown in fig. 5, the neuron element circuit 9 includes an accumulation unit 11, a signal output unit 12, and switches 16a and 16 b.

Each having an AND signal value x_iPulse of corresponding pulse widthSignal (PWM signal) as input signal in₁To in₆Are input to the plurality of input signal lines 6. In the example shown in fig. 5, six input signal lines 6 are shown, but the number of input signal lines 6 is not limited. Inputting an input signal in during an input period T having a predetermined duration₁To in₆(see fig. 6).

The positive charge output line 7a outputs and passes the signal value x_iMultiplying by a positive weight value w_i ⁺The product value (w) thus obtained_i ⁺*x_i) Corresponding positive weight charge. The negative charge output line 7b outputs and passes the signal value x_iMultiplied by a negative weight value w_i ^-And the obtained product value (| w)_i ^-|*x_i) Corresponding negative weight charge. In the present embodiment, the pair of output lines 7 corresponds to one or more output lines.

A plurality of synapse circuits 8 are arranged in association with the plurality of input signal lines 6, respectively. In this embodiment, one synaptic electrical circuit 8 is provided in one input signal line 6. Each of the plurality of synaptic electrical circuits 8 includes a resistor 17 connected between a corresponding one of the plurality of input signal lines 6 and either one of the positive charge output line 7a or the negative charge output line 7 b. The resistor 17 may have a non-linear characteristic and may have a function of preventing a current from flowing backward. Corresponding to the product value (w)_i ⁺*x_i) (or (| w)_i ^-|*x_i) Is output to the output line 7a (or 7b) to which the resistor 17 is connected.

For example, to convert a signal value x in each synaptic electrical circuit 8_iMultiplying by a positive weight value w_i ⁺The resistor 17 is connected between the input signal line 6 and the positive charge output line 7a and causes the positive charge output line 7a to output the positive weight charge. In the example shown in fig. 5, an input signal in is input₁、in₃、in₆Is a synapse circuit 8a of a positive weight multiplication unit configured to generate a positive weight charge. It can also be said that the synaptic electrical circuit 8a is a multiplication unit with a positive weight set.

To make at each synaptic electricalSignal value x in way 8_iMultiplied by a negative weight value w_i ^-The resistor 17 is connected between the input signal line 6 and the negative charge output line 7b and causes the negative charge output line 7b to output the negative weight charge. In the example shown in fig. 5, an input signal in is input₂、in₄、in₅Is a synapse circuit 8b of a negative weight multiplication unit configured to generate a negative weight charge. It can also be said that the synapse circuit 8b is a multiplication unit with a negative weight set.

Hereinafter, the synaptic electrical circuits 8a and 8b will sometimes be referred to as a positive weight multiplication unit 8a and a negative weight multiplication unit 8 b. Further, the resistor 17 connected between the input signal line 6 and the positive charge output line 7a is sometimes referred to as a positive resistor 17 a. Further, the resistor 17 connected between the input signal line 6 and the negative charge output line 7b is sometimes referred to as a negative resistor 17 b.

It should be noted that the weight value w to be set will have_iA resistor of a corresponding resistance value is used as the resistor 17. That is, the resistor 17 serves as a weight value w defining in the arithmetic device 100 that performs the multiply-accumulate operation at the analog circuit 3_iThe element of (1).

For example, a fixed resistor element, a variable resistor element, a MOS transistor operating in a sub-threshold region, or the like is used as the resistor 17. For example, by using a MOS transistor operating in the sub-threshold region as the resistor 17, power consumption can be reduced. Of course, any other resistor may be used.

The accumulation unit 11 accumulates corresponding product values (w) generated by the plurality of synapse circuits 8_i*x_i) Of the charge of (c). In this embodiment, two capacitors 13a and 13b are provided as the accumulation unit 11.

The capacitor 13a is connected to the positive charge output line 7a via a switch 16a to accumulate the positive weight charge generated by the synapse circuit 8 a. The capacitor 13b is connected to the negative charge output line 7b via a switch 16b to accumulate the negative weight charge generated by the synapse circuit 8 b.

The charging unit 15 accumulates the and product value (w)_i*x_i) The corresponding charge-summed accumulation unit 11 is charged. In the present embodimentThe charging unit 15 includes a signal source (not shown), a charging line 19, and two resistors 20.

The charging line 19 is arranged in parallel with the input signal line 6. A resistor 20a of the two resistors 20 is connected between the charging line 19 and the positive charge output line 7 a. Another resistor 20b is connected between the charging line 19 and the negative charge output line 7 b. Thus, the charging line 19 is connected to the capacitor 13a via the resistor 20 a. Further, the charging line 19 is connected to the capacitor 13a via a resistor 20 b.

Resistors 20a and 20b having the same resistance value are used. Although the same resistor is generally used, different types of resistors having the same resistance value may be used. The specific configuration of the resistors 20a and 20b is not limited, and various configurations as in the resistor 17 may be used. Further, as the resistors 20a and 20b, the same resistor as the resistor 17 or a resistor different from the resistor 17 may be used.

The charging is performed after the input period T ends. In the present embodiment, the charging signal CH is input via the charging line 19 after the input period T ends. That is, the same charging signal CH is supplied from the charging line 19 to the capacitors 13a and 13 b. Accordingly, charges based on the high level value of the charging signal CH and the resistance values of the resistors 20a and 20b are accumulated in the capacitors 13a and 13 b.

Since the resistance values of the resistors 20a and 20b are equal to each other, the capacitors 13a and 13b are charged at the same charging speed. By the charging of the charging unit 15, the potential V of the positive charge output line 7a⁺(voltage held by capacitor 13 a) and potential V of negative charge output line 7b^-(the voltage held by the capacitor 13b) is raised.

After the charging unit 15 starts charging, the signal output unit 12 performs threshold determination on the voltage held by the accumulation unit 11 based on a predetermined threshold value, thereby outputting a value representing the product (w)_i*x_i) Multiply-accumulate the signal of the sum. In this embodiment, two comparators 22a and 22b and a signal generation unit 23 are provided as the signal output unit 12.

The comparator 22a detects the timing at which the voltage held by the capacitor 13a exceeds a predetermined threshold. It should be noted that the magnitude of the voltage held by the capacitor 13a is determined by the total amount of positive-weight electric charges accumulated in the capacitor 13a and the amount of electric charges (charging speed × time).

The comparator 22b detects the timing at which the voltage held by the capacitor 13b exceeds a predetermined threshold. It should be noted that the magnitude of the voltage held by the capacitor 13b is determined by the total amount of the negative weight electric charges accumulated in the capacitor 13b and the amount of electric charges (charging speed × time).

It should be noted that, in the present embodiment, the multiply-accumulate signal is output by performing threshold determination for each of the capacitors 13a and 13b having the common threshold value θ. Therefore, the efficiency and speed of the operation can be improved. Of course, in the case of using thresholds different from each other, a multiply-accumulate operation is also possible.

The signal generation unit 23 outputs a value (w) representing the product based on the timing detected by the comparator 22a and the timing detected by the comparator 22b_i*x_i) Multiply-accumulate the signal of the sum. In other words, the signal generating unit 23 outputs the multiply-accumulate signal based on the timing at which the voltage held by the capacitor 13a reaches the threshold value θ and the timing at which the voltage held by the capacitor 13b reaches the threshold value θ.

In this embodiment, the PMW signal, which is a pulse signal whose pulse width has been modulated, is output as a multiply-accumulate signal. The specific circuit configuration and the like of the signal generating unit 23 are not limited and may be designed arbitrarily.

Fig. 6 and 7 are diagrams for describing calculation examples of the multiply-accumulate signal of the analog circuit 3 shown in fig. 5. In the present embodiment, a signal representing a total multiply-accumulate result including a positive value and a negative value is calculated from a positive weight charge multiply-accumulate result based on the positive weight charge accumulated in the capacitor 13a and a negative weight charge multiply-accumulate result based on the negative weight charge accumulated in the capacitor 13 b.

The calculation of the multiply-accumulate result of the positive weight charge and the calculation of the multiply-accumulate result of the negative weight charge are the same process. First, a method of calculating a multiply-accumulate result from the charge accumulated in the capacitor 13 without distinguishing positive and negative values (multiply-accumulate method) will be described with reference to fig. 6.

The parameters described in fig. 6 will be described. "t" represents time. "T" denotes each of the input period and the output period. "t" s_n"indicates the end timing of the input period T," T_m"indicates the end timing of the output period T.

In the present embodiment, the duration of the input period T and the duration of the output period T are set equal to each other. Further, the output period T is timed from the end of the input period T_nAnd starting. Therefore, the end timing T of the input period T_nCorresponding to the start timing of the output period T.

Further, in the present embodiment, the charging unit 15 performs charging in the output period T after the input period T. Therefore, the output period T corresponds to the charging period.

"θ" denotes a common threshold value used for the threshold value determination performed by the signal output unit 12 (comparator 22).

“S_i(t) "represents an input signal (PWM signal) input to the i-th input signal line 6. ' tau_i"denotes the input signal S_i(t) pulse width. "P_i(t) "represents the amount of change in the internal state (potential) in each synaptic electrical circuit 8 shown in FIG. 5. "w_i"represents a weight value and is defined by the resistance value of the resistor 17 shown in fig. 5.

“V_n(t) "represents" P_i(t) "and corresponds to the total amount of charge accumulated in the capacitor 13. "S_n(t) "represents a multiply-accumulate signal (PWM signal) representing a multiply-accumulate result. ' tau_n"denotes a pulse width of the multiply-accumulate signal to be output. Specifically, "τ_n"indicates a timing from the timing when the voltage held by the capacitor 13 exceeds the threshold value θ in the output period T to the end timing T of the output period T_mCorresponding to the value of duration of (d).

"ch (T)" is a charging signal input to the charging line 19 in the output period T as the charging period. As shown in fig. 6, in the present embodiment, a pulse signal that becomes the ON level during the output period T is input as a charging signal. Thus, the pulse width τ of the charging signal_CHEqual to the pulse width of the charging signal in the output period T.

In this example, the switches 16a and 16b are provided, and in particular, reduction in power consumption can be improved by turning off the output lines via the switches.

Here, as shown in the following expression, an input value (signal value) x_iFrom an input signal S_i(t) pulse width τ_iDuty ratio R relative to input period T_i(. tau/T).

[ formula 3]

The synaptic electrical circuit 8 shown in FIG. 5 generates and passes the signal value x_iMultiplied by a weight value w_iThe obtained product value corresponds to the charge. In particular, the resistance of the resistor 17 is at a constant slope w_iThe internal state (potential) is increased.

End timing T of input period T_nChange amount P of internal potential of each synaptic circuit 8 at that time_i(t_n) Given by the following expression. It should be noted that the input signal S_iThe high level value of (t) is set to 1.

[ formula 4]

P_i(t_n)＝w_iR_iT＝w_ix_iT

The total amount of charge V accumulated in the capacitor 13_n(t_n) Is Pi (t)_n) The sum of (a) and (b) is thus given by the following expression.

[ formula 5]

At the end timing T of the input period T_nIs initially charged by the charging unit 15 (current source 18). As described above, in the present embodiment, the output period T corresponds to the charging period.

By being charged by the charging unit 15, the internal potential of each synaptic circuit 8 is timed T from the end of the input period T_nIncreasing with a slope a. The charging speed α is determined by the high level value of the charging signal and the resistance value of the resistor 20. It should be noted that the illustration of the internal potential variation of each synaptic electrical circuit 8 within the output period T is omitted in fig. 6 (the value of the internal potential at the end of the input period T is schematically shown by a dotted line).

A pulse signal having a high level value equal to that of the input signal may be used as the charging signal. Of course, a pulse signal having a high value different from that of the input signal may be used. Any other electrical signal different from the input signal may be used as the charging signal.

Is generated to have a timing from the timing at which the voltage held by the capacitor 13 exceeds the threshold value θ in the output period T to the end timing T of the output period T_mThe duration of which corresponds to the pulse width τ n.

Suppose pulse width τ of multiply-accumulate signal_nDuty ratio to output period T is R_n(＝τ_n/T)，R_nGiven by the following expression. It should be noted that the threshold value θ is equal to or greater than the total amount of charge V_n(t_n)。

[ formula 6]

Therefore, will all pass the signal value x_iAnd weight value w_iProduct value (w) obtained by multiplication_i*x_i) The multiply-accumulate result obtained by the addition is given by the following expression.

[ formula 7]

That is, the multiply-accumulate result is obtained by accumulating from α R_n＝α·(τ_nT) minusThe charging speed α, the threshold value θ, and a constant defined by the output period T. In this way, the multiply-accumulate signal representing the multiply-accumulate result can be output based on the timing at which the voltage held by the accumulation unit 11 exceeds the threshold value θ in the output period T having a predetermined duration.

Fig. 7 is a diagram showing a calculation example of a multiply-accumulate signal representing an overall multiply-accumulate result of the multiply-accumulate results based on both the positive weight charges and the negative weight charges. In fig. 7, the multiply-accumulate signal indicating the multiply-accumulate result of the positive weight charge is represented by "S_n ⁺(t) "represents that the pulse width thereof is represented by" τ_n ⁺"means. In addition, the multiply-accumulate signal representing the multiply-accumulate result of the negative weight charge is represented by "S_n ^-(t) "represents that the pulse width thereof is represented by" τ_n ^-"means. In addition, the multiply-accumulate signal representing the total multiply-accumulate result is represented by "S_n(t) "represents that the pulse width thereof is represented by" τ_n"means.

At the end timing T of the input period T_nThe total amount V of positive weight charges accumulated in the capacitor 13a_n ⁺(t_n) Given by the following expression. It should be noted that w_i ⁺Representing a positive weight value.

[ formula 8]

At the end timing T of the input period T_nThe total amount V of negative weight charges accumulated in the capacitor 13b_n ^-(t_n) Given by the following expression. It should be noted that w_i ^-Representing a negative weight value.

[ formula 9]

Multiply-accumulate signal S_n ⁺(t) is R_n ⁺(＝τ_n ⁺T), will pass the signal value x_iMultiplying by a positive weight value w_i ⁺The obtained product value (w)_i ⁺*x_i) The positive multiply-accumulate result obtained by the addition is given by the following expression. It should be noted that the threshold θ is assumed to be equal to or greater than the total amount V of positive-weight charges_n ⁺(t_n)。

[ equation 10]

At negative multiply-accumulate signal S_n ^-(t) a duty cycle of R_n ^-(＝τ_n ^-In the case of/T), will be determined by inputting the value x_iMultiplied by a negative weight value w_i ^-The obtained product value (| w)_i ^-|*x_i) The negative multiply-accumulate result obtained by the addition is given by the following expression. It should be noted that the charging speed α and the threshold value θ are equal to the values used in the expression (equation 10). Further, it is assumed that the threshold θ is equal to or larger than the total amount V of negative weight charges_n ^-(t_n)。

[ formula 11]

Thus, with the above expression (equation 2), the total multiply-accumulate result is given by the following expression.

[ formula 12]

I.e. the total multiply-accumulate result is passed through the charging speed alpha, the multiply-accumulate signal S_n ⁺(t) pulse width τ_n ⁺Multiply-accumulate signal S_n ^-(t) pulse width τ_n ^-And the output period T is obtained. That is, the multiply-accumulate result can be easily calculated based on the timing detected by the comparator 22a and the timing detected by the comparator 22 b.

As shown in fig. 7, it is possible to easily output a pulse having a pulse width "τ_n"multiplication-accumulation signal" S_n(t) "as a multiply-accumulate signal representing the total multiply-accumulate result. It should be noted that the multiply-accumulate signal S may be determined_n ⁺(t) pulse width τ_n ⁺And multiply-accumulate signal S_n ^-(t) pulse width τ_n ^-Which is larger. At pulse width τ_n ⁺Multiply-accumulate signal "S" in the case of larger values_n(t) "may be output as a positive multiply-accumulate signal and at pulse width τ_n ^-Multiply-accumulate signal "S" in the case of larger values_n(t) "may also be output as a negative multiply-accumulate signal. For comparing pulse widths τ_n ⁺And pulse width τ_n ^-The circuit of (2) can be realized by appropriately using an AND circuit, a NOT circuit, or the like.

It may also be arranged so that in the case of using a ReLU function (ramp function) or the like, for example, when a positive multiply-accumulate signal "S" is obtained_n(t) ", the signal is outputted as it is, when a negative multiply-accumulate signal" S "is obtained_n(t) ", 0 is output.

When the charging speed α and the threshold value θ are set, α is set to θ/T for the output period T. Therefore, constants determined by the charging speed α, the threshold θ, and the output period T included in the expressions (equation 6), (equation 7), (equation 10), and (equation 11) can be set to zero, and the processing can be simplified.

For example, the high level value of the charging signal and the resistance value of the resistor 20 are appropriately set to adjust the charging speed α. The threshold value θ is set based on the duration of the input period T. Therefore, advantageous effects can be exerted.

[ analog Circuit according to the TACT method ]

FIG. 8 is a diagram showing an example of the analog circuit 3 according to the TACT methodSchematic circuit diagram. At the AND signal value x_iWith corresponding timing, a pulse signal (TACT signal) as an input signal in₁To in₆Are inputted to the plurality of input signal lines 6.

Here, as shown in B of fig. 2, a continuous pulse signal which rises to a timing corresponding to an input value and maintains an ON level is input. As for the pulse signal, the duration of the ON time with respect to the input period T corresponds to the input value in the input period T. Hereinafter, the duration of the ON time in the input period T is sometimes referred to as a pulse width in the input period T.

At the timing when the input period T elapses, the charges accumulated in the capacitor 13a are each equal to the positive weight value w_i ⁺The sum σ of the positive weight charges corresponding to the product value of (c)⁺. Similarly, the charges accumulated in the capacitor 13b are each equal to the negative weight value w_i ^-The sum σ of the negative weight charges corresponding to the product value of (c)^-。

Since the ON level of the electric signal is maintained also after the end of the input period T, electric charges are accumulated in the capacitors 13a and 13 b. Based on the timing at which the voltage held by the capacitor 13a exceeds the threshold value θ, a multiply-accumulate signal (PWM signal) representing the multiply-accumulate result of the positive weight charge is generated.

Further, a multiply-accumulate signal (PWM signal) representing a multiply-accumulate result of the negative weight charge is generated based on the timing at which the voltage held by the capacitor 13b exceeds the threshold value θ. A multiply-accumulate signal representing the total multiply-accumulate result may be generated based on these positive and negative multiply-accumulate signals.

In the analog circuit 3 according to the TACT method shown in fig. 8, the output period T corresponds to the charging period. Further, the input signal in input to the plurality of input signal lines 6 in the output period T₁To in₆Corresponding to the charging signal.

Therefore, according to the analog circuit 3 of the TACT method shown in fig. 8, the same charging signal is supplied to the capacitors 13a and 13b via the plurality of input signal lines 6. Although not shown in the figure, for applying the input signal in during the output period T₁To in₆Input to a plurality of input messagesThe configuration of the sign line 6 corresponds to the charging unit 15. Therefore, for inputting the input signal in₁To in₆Is also used as the charging unit 15. As shown in fig. 8, the plurality of input signal lines 6 themselves may be regarded as a part of the charging unit 15.

Here, the inventors have considered the time constant as a parameter associated with charge accumulation of the capacitor 13 in the input period T and the output period (charging period) T. In the above, the charge accumulation in the input period T and the output period T is approximated to a linear change and the "slope w" is used_i"and" slope α "as shown in fig. 6. Of course, the analog-type arithmetic apparatus 100 capable of accurately performing predetermined arithmetic processing including multiply-accumulate operations can be realized based on such approximation.

On the other hand, it is considered that the electric charge (potential) of the capacitor 13 is accumulated in the input period T and the output period (charging period) T according to a time constant determined by the circuit configuration of the analog circuit 3 shown in fig. 5 and 8. Therefore, the inventors thought that by appropriately designing the circuit configuration, more accurate multiply-accumulate operation can be realized on the basis of accumulating electric charges according to the time constant.

Hereinafter, the charge (potential) of the capacitor 13 will sometimes be described as the (charge) potential of the output line 7 for outputting the charge to the capacitor 13.

The inventors have found a configuration that makes the time constant of the output line 7 independent of the number of resistors 17 provided between the output line 7 and the plurality of input signal lines 6.

First, it is assumed that the capacitors 13a and 13b functionally include parasitic capacitances (not shown) generated in the output lines 7a and 7 b. In this case, the minimum value of the capacitances that the capacitors 13a and 13b can take is the parasitic capacitance generated in the output line 7. For example, even in the case where the capacitor 13 is not provided, electric charges can be accumulated based on parasitic capacitances generated in the output lines 7a and 7b, and a multiply-accumulate signal can be generated based on threshold determination. The same applies to the analog circuit 3 according to the PWM method shown in fig. 5.

The time constant of the output line 7 is continuously changed in accordance with the number of input signals sequentially input with time and the number of resistors 17 (on-resistances) in a state in which signals can be transmitted to the output line 7. Here, the emphasis is placed on the time constant at the end of the input period T. In the analog circuit 3 according to the TACT method of the present embodiment, signals are input to all the input signal lines 6 at the end of the input period T. Therefore, the number of input signals at the end of the input period T takes a maximum value and a constant value. As a result, the time constant at the end of the input period T continuously changes according to the number of on-resistances.

Here, the resistance value of the resistor 17 is set to the same resistance value R. In other words, a binary connected configuration is employed. Further, the parasitic capacitance of each synaptic circuit 8 is designed as a constant capacitance C. Since the resistors 17 are connected in parallel to one output line 7, the combined resistance is R/N in the case where N resistors 17 are connected (the number of on-resistances is N). On the other hand, since the number of synaptic electrical circuits 8 is N, which is equal to the number of resistors 17, the combined capacitance is NC.

For example, without providing the capacitor 13, the multiply-accumulate signal is generated based on the parasitic capacitance of each synapse circuit 8. In this case, the value of the combined resistance × the combined capacitance is RC irrespective of the number of resistors 17 (the number of on-resistances), and therefore the time constant of the output line 7 at the end of the input period T is RC irrespective of the number of resistors 17.

In the case where the capacitor 13 is mounted, the capacitance of the capacitor 13 is set by setting a predetermined constant C₀A value (the number of resistors 17 × C) obtained by multiplying the number of resistors 17 (the number of on-resistances)₀). Thus, the time constant is R/Nx (NC + NC)₀)＝R×(C+C₀) And is independent of the number of resistors 17. Therefore, the time constant can be made constant regardless of the number of resistors 17.

Therefore, the potential V of each output line 7 at the end of the input period T can be approximated by the following expression.

[ formula 13]

Fig. 9 is a schematic graph for describing the potential V of each output line 7 at the end of the input period T. The potential V of each output line 7 at the end of the input period T will be described with reference to expression (formula 13) and fig. 9. It should be noted that the time constant curve in the graph of fig. 9 is a curve corresponding to the expression (formula 13).

"Vc" represents a constant and is a value corresponding to a convergence value of the potential after a time equal to or longer than a time constant has elapsed.

“t_ave"represents an average value of the pulse width of the pulse signal input to the input signal line 6 in the input period T.

It should be noted that the change in the electric charge of each output line 7 until the end of the input period T does not always occur according to the time constant curve shown in fig. 9. It is found that the potential V of each output line 7 at least at the end of the input period T can be approximated by the expression (formula 13).

ON the other hand, in the output period (charging period) T, the input signal in is at the ON level₁To in₆The (charging signal) is input to all the input signal lines 6. Therefore, it can be considered that the change of the electric charge in the output period (charging period) T is performed according to the time constant curve shown in fig. 9.

Here, assume the end timing T of the input period T_nThe potential V of each output line 7 at that time is approximately expressed as "Vt" by the expression (formula 13)_n". Further, from the end timing T of the input period T_nThe time from (the time within the output period T) is set to T. Then, the potential "V" of each output line 7 in the output period T_out"can be approximated by the following equation.

[ formula 14]

Here, as shown in fig. 9, according to the time corresponding to the expression (formula 13)The inter-constant curve determines the input period T and the threshold θ. That is, the input period T is substituted into "T" of (equation 13)_aveThe potential V at "is set to the threshold value θ. Therefore, when the maximum pulse having the maximum pulse width in the input period T is input to all the input signal lines 6, the potential of the output line 7 exceeds the threshold value at the end timing of the input period T (the start timing of the output period T).

On the other hand, when a pulse having a pulse width of 0 in the input period T is input to all the input signal lines 6, the potential of the output line 7 exceeds the threshold at the end timing of the output period T. Therefore, the multiply-accumulate signal can be accurately calculated with high resolution within the output period T. That is, by setting the threshold value θ based on the duration of the input period T, an advantageous effect can be exhibited.

As shown in fig. 9, the threshold determination is performed on each of the capacitors 13a and 13b based on the threshold θ. Therefore, "T" using the average value of the pulse widths of the respective pulse signals in the input period T can be accurately generated and output_aveAs pulse width τ_n"multiplication-accumulation signal" S_n(t) ". Thus, the multiply-accumulate signal "S" is found_n(t) "pulse width" τ_n"may also be approximated by the expression (equation 13).

The potential V of the positive charge output line 7a is combined in each analog circuit 3 regardless of the number of resistors 17 for connecting the input signal line 6 and the positive charge output line 7a (i.e., the number of positive weight multiplying units) and the number of resistors 17 for connecting the input signal line 6 and the negative charge output line 7b (i.e., the number of negative multiplying units)⁺And potential V of negative charge output line 7b^-The multiply-accumulate operation shown in fig. 9 is implemented.

Thus, as shown in FIG. 7, it is possible to accumulate the signal S based on the multiply-accumulate signal_n ⁺(t) pulse width τ_n ⁺And multiply-accumulate signal S_n ^-(t) pulse width τ_n ^-To calculate a multiply-accumulate signal 'S' representing the total multiply-accumulate result_n(t)”。

It should be noted that it is preferable that,even in the case of adopting other configurations, the analog circuit 3 is designed such that the time constant of the positive charge output line 7a is equal to the time constant of the negative charge output line 7. Therefore, the potential V with respect to the positive charge output line 7a⁺And potential V of negative charge output line 7b^-The multiply-accumulate operation shown in fig. 9 is implemented.

Of course, the present technique is not limited to the case of employing a binary concatenated configuration, where the positive weight value w_i ⁺And a negative weight value w_i ^-Is fixed to the same value.

For example, a positive weight value w_i ⁺And a negative weight value w_i ^-Is multivalued. I.e. a positive weight value w_i ⁺And a negative weight value w_i ^-Is set to any one of a plurality of values different from each other. Alternatively, the positive weight value w is randomly set_i ⁺And a negative weight value w_i ^-Absolute value of (a).

Also in this case, the analog circuit 3 is designed such that the time constant of the positive charge output line 7a is equal to the time constant of the negative charge output line 7. Therefore, the potential V with respect to the positive charge output line 7a⁺And potential V of negative charge output line 7b^-The multiply-accumulate operation shown in fig. 9 is implemented.

In the present disclosure, the time constant of the output line 7 is included in the time constant associated with outputting the electric charge corresponding to the product value to the output line 7 through the plurality of synapse circuits 8. The time constant of the positive charge output line 7a is included in the time constant associated with outputting positive charges to the positive charge output line 7a through the plurality of positive weight multiplication units 8 a. The time constant of the negative charge output line 7b is included in the time constants associated with outputting the weight charges to the negative charge output line 7b through the plurality of weight multiplication units 8 b.

Next, consider the analog circuit 3 according to the PWM method shown in fig. 5. In the analog circuit 3 according to the PWM method shown in fig. 5, the signal in is input₁To in₆The input signal lines 6 are input to the input period T. Then, in the output period T, via the charging lineThe charging signal CH is input at 19.

Here, the potential V of the output line 7 at the end of the input period T can be approximated by the expression (expression 13) as in the TACT method. That is, as shown in fig. 9, the time constant curve can be approximated from the time constant of the output line 7. Thereafter, the resistance values of the charging line 19 and the resistor 20 are designed so that the charging unit 15 performs charging according to the same time constant curve. Thus, the multiply-accumulate operation shown in fig. 9 is realized.

For example, in the configuration shown in fig. 5, the combined resistance of the positive resistor 17a and the resistance value of the resistor 20a connected to the charging wire 19 are made equal. Thus, the multiply-accumulate operation shown in fig. 9 is implemented with respect to the positive charge output line 7 a. Further, the combined resistance of the negative resistor 17b and the resistance value of the resistor 20b connected to the charging line 19 are made equal. Thus, the multiply-accumulate operation shown in fig. 9 is realized with respect to the negative charge output line 7 b.

For example, the analog circuit 3 is designed such that the time constant of the positive charge output line 7a and the time constant of the negative charge output line 7b are equal in the input period T. Then, the combined resistance of the positive resistor 17a and the resistance value of the resistor 20a are made equal, and the combined resistance of the negative resistor 17b and the resistance value of the resistor 20b are made equal.

Therefore, according to the potential V with respect to the positive charge output line 7a⁺And potential V of negative charge output line 7b^-The same time constant as shown in fig. 9. Therefore, it is possible to accurately generate and output an average value of pulse widths of respective pulse signals having an input period T as the pulse width "τ_n"multiplication-accumulation signal" S_n(t)”。

Of course, the application of the present technique is not limited to the case of implementing the multiply-accumulate operation shown in fig. 9. As the analog circuit 3 according to the PWM method and the analog circuit 3 according to the TACT method, other configurations and other multiply-accumulate operations can be performed. In any case, the result of the multiply-accumulate operation may be based on the potential V of the positive charge output line 7a (the voltage held in the capacitor 13 a)⁺And the potential of the negative charge output line 7b (held in the capacitor 13b)Voltage) V^-To obtain the final product.

In the present embodiment, the analog circuit 3 according to the PWM method and the analog circuit 3 according to the TACT method each include a plurality of input signal lines 6, a plurality of synapse circuits 8, an accumulation unit 11, a charging unit 15, and a signal output unit 12.

The accumulation unit 11 includes a capacitor 13a capable of accumulating a positive weight charge generated by the synapse circuit (positive weight multiplication unit) 8a and a capacitor 13b capable of accumulating a negative weight charge generated by the synapse circuit (negative weight multiplication unit) 8 b.

The charging unit 15 charges the capacitors 13a and 13b after the input period T. The signal output unit 12 may output the multiply-accumulate signal by performing threshold determination on each of the capacitors 13a and 13b using a predetermined threshold. It should be noted that the predetermined threshold may be set based on the duration of the input period.

Fig. 10 to 13 are schematic diagrams each showing an example of the configuration of the arithmetic device 100.

The arithmetic device 100 shown in fig. 10 to 13 includes a plurality of input signal lines 6 and a plurality of analog circuits 3 connected in parallel with the plurality of input signal lines 6. By adopting such a configuration, an electric signal can be input in parallel into each analog circuit 3, and the arithmetic processing speed can be increased. Therefore, excellent operation performance can be exhibited.

In the arithmetic device 100 shown in fig. 10 and 11, the analog circuit 3 according to the PWM method described with reference to fig. 5 to 7 is arranged as a plurality of analog circuits 3. In the arithmetic device 100 shown in fig. 12 and 13, the analog circuit 3 according to the TACT method described with reference to fig. 8 and 9 is arranged as a plurality of analog circuits 3.

In the present embodiment, the charging unit 15 performs charging on the plurality of analog circuits 3 in the common charging mode. Further, the common threshold is set as a predetermined threshold for threshold determination of the signal output unit 12 in the neuron element circuit 9. That is, charging is performed in the same charging mode and threshold determination is performed using the same threshold in each analog circuit 3.

In the analog circuit 3, a common charging mode is performed for each of the capacitors 13a and 13 b. That is, the charging of the plurality of capacitors 13a and 13b included in the plurality of analog circuits 3 is performed in the common charging mode. Then, threshold determination is performed at the plurality of analog circuits 3 by using a common threshold, and the multiply-accumulate signal is output.

The common charging mode may be charging in which a charging signal is supplied to each analog circuit 3 during a common charging period. Further, the common charging mode also includes a mode in which the same charging signal is supplied in each analog circuit 3. Further, the common charging mode includes charging at a common charging speed (charging rate), charging according to a common time constant, and the like. Of course, the present technology is not limited thereto.

For example, as shown in fig. 10 and 11, a common charging line 19 is arranged for a plurality of analog circuits 3. The charging lines 19 are arranged in parallel to the plurality of input signal lines 6. A resistor 20a is connected between the charging line 19 and the positive charge output line 7a of each analog circuit 3. The resistor 20b is connected between the charging line 19 and the negative charge output line 7b of each analog circuit 3.

The charging signal that becomes ON level during the output period (charging period) T is input via the charging line 19. Thus, the same charging signal may be provided in a common charging period. Resistors all having the same resistance value are arranged as the resistors 20a and 20 b. Accordingly, charging may be performed at a common charging rate at a common charging speed.

For example, assume that charging is performed at a common charging speed in a common charging period. In this case, the potential of the positive charge output line 7a and the potential of the negative charge output line 7b of each analog circuit 3 rise in accordance with the charging speed α, as shown in fig. 6.

Therefore, as shown in fig. 7, it is possible to accumulate the signal S based on the multiply-accumulate signal S in each analog circuit 3_n ⁺(t) pulse width τ_n ⁺And multiply-accumulate signal S_n ^-(t) pulse width τ_n ^-To calculate a multiply-accumulate signal 'S' representing the total multiply-accumulate result_n(t)”。

Further, each analog circuit 3 and the charging unit 15 are designed such that a time constant of each output line 7 (positive charge output line 7a or negative charge output line 7b) in the output period T is a common value. In this case, charging according to a common time constant can be achieved.

Each analog circuit 3 is designed such that a time constant of the positive charge output line 7a and a time constant of the negative charge output line 7b in the input period T are equal in each of the plurality of analog circuits 3 and such that the value of the time constant is a common value in all the analog circuits 3. Then, the charging unit 15 is designed such that the time constant of the positive charge output line 7a and the time constant of the negative charge output line 7b in the output period T are equal to the time constant in the input period T. Thus, the multiply-accumulate operation shown in fig. 9 is realized in each analog circuit 3. It should be noted that the threshold is determined from the time constant curve based on the input period T, and is set as the common threshold.

Further, as shown in fig. 12 and 13, the input signal is input so as to maintain the ON state in the output period T. Accordingly, charging is performed in which the same charging signal is supplied during the common charging period.

Further, each analog circuit 3 and the charging unit are designed such that the time constant of each output line 7 (positive charge output line 7a, negative charge output line 7b) is a common value. In this case, charging according to a common time constant can be achieved. Therefore, the multiply-accumulate operation shown in fig. 9 can be implemented in each analog circuit 3. It should be noted that the threshold is determined from a time constant curve based on the input period T, and is used as a common threshold.

Here, the inventors also consider the output of the multiply-accumulate signal of the analog circuit 3 when the charging according to the common charging mode is performed and when the threshold determination using the common threshold is performed. Then, the inventors found that the precision of the multiply-accumulate operation is improved by appropriately outputting the multiply-accumulate signal from each analog circuit 3 in the common output period T. In other words, the inventors found that the precision of the multiply-accumulate operation is improved by increasing the number of analog circuits capable of outputting the multiply-accumulate signal within the common output period T.

For example, assume that a binary connection configuration is adopted in the arithmetic device 100 shown in fig. 10 and 11. In the binary concatenation, the absolute values of the positive weight value and the negative weight value are fixed to the same value. That is, the resistance values of the resistors 17 are all fixed to the same value.

In the configuration shown in fig. 10, at each analog circuit 3, the sum of the number of positive resistors 17a and the number of negative resistors 17b is set to a common value (seven). Therefore, with the configuration shown in fig. 10, in the plurality of analog circuits 3, a value obtained by adding the sum of the positive weight values set in the plurality of synaptic circuits 8 (hereinafter referred to as a positive sum value) and the sum of the absolute values of the negative weight values set in the plurality of synaptic circuits 8 (hereinafter referred to as a negative sum value) is a common value.

It should be noted that a value obtained by adding the positive sum value and the negative sum value corresponds to a sum of absolute values of weight values set in the plurality of synapse circuits 8, and will be referred to as a weight sum value hereinafter.

In the configuration shown in fig. 11, at each analog circuit 3, the sum of the number of positive resistors 17a and the number of negative resistors 17b is not set to a common value. For example, the total number of the resistors 17 may be set to any number of a plurality of numbers different from each other. Alternatively, the total number of resistors 17 may be set randomly.

Therefore, with the configuration shown in fig. 11, in the plurality of analog circuits 3, a value (weighted sum value) obtained by adding the positive sum value and the negative sum value is not a common value. For example, a configuration may be realized in which the weight sum value is any of a plurality of values different from each other. Alternatively, a configuration in which the weight sum value is a random value may also be implemented.

It should be noted that in the configuration shown in fig. 11, there is a synapse circuit 8 in which both the positive and negative resistors 17a, 17b are not set. Such a synapse circuit 8 may be said to be a multiplication unit corresponding to a term having a weight value of zero in a multiply-accumulate operation.

With regard to the configurations shown in fig. 10 and 11, it is assumed that a configuration other than binary connection is employed. The absolute values of the positive and negative weight values are multivalued. Alternatively, the absolute values of the positive and negative weight values are randomly set.

As for a value (weighted sum value) obtained by adding up a positive sum value and a negative sum value, any of a configuration in which the value is a common value, a configuration in which the value is any one of a plurality of values different from each other, and a configuration in which the value is a random value can be realized.

For example, the arithmetic device 100 shown in fig. 10 and 11 can be implemented using the resistor 17 having a multivalued resistance value or the resistor 17 having a random resistance value as appropriate under the condition that the weight sum value is a common value or the weight sum value is any one of a plurality of values different from each other.

The same applies to the arithmetic device 100 shown in fig. 12 and 13. For example, in the case of adopting the binary connection configuration, with the configuration shown in fig. 12, the weight and the total value are common values in the plurality of analog circuits 3. With the configuration shown in fig. 13, the weight sum value is not a common value in the plurality of analog circuits 3. For example, a configuration may be realized in which the weight sum value is any of a plurality of values different from each other. Alternatively, a configuration in which the weight sum value is a random value may also be implemented.

With regard to the configurations shown in fig. 12 and 13, it is assumed that a configuration other than binary connection is employed. In this case, any one of a configuration in which the weight sum value is a common value, a configuration in which the weight sum value is any of a plurality of values different from each other, and a configuration in which the weight sum value is a random value may be realized.

Charging according to a common charging mode and threshold determination using a common threshold are performed on the multiple-input multiple-output arithmetic device 100 having such various configurations, thereby causing each analog circuit 3 to output a multiply-accumulate signal appropriately. For this reason, the inventors paid attention to the weight sum value, the positive sum value, and the negative sum value in each analog circuit 3.

Then, the inventors newly designed to perform charging based on the maximum value of the weight sum value among the plurality of analog circuits 3 and perform threshold determination using the threshold based on the maximum value of the weight sum value among the plurality of analog circuits 3. That is, the inventors newly devised a technique of performing charging based on the maximum value between the weight sum values in the plurality of analog circuits 3 and performing threshold determination using a threshold value based on the maximum value.

For example, in the configurations shown in fig. 10 and 11, the combined resistance in the case where all the resistors 17 included in the analog circuit 3 having the largest weight sum value are connected in parallel is used as the common resistance value. Then, the resistance values of all the resistors 20a and 20b are unified to the common resistance value. In this case, charging according to the common time constant is achieved within the output period T.

Such charging corresponds to charging in which a time constant associated with outputting the electric charge corresponding to the product value to the output line 7 using the plurality of synapse circuits 8 whose sum value is the maximum value by the weight is used as a common time constant.

The threshold value is determined based on the input period T according to a time constant curve, which is collectively defined by resistance values. Accordingly, each analog circuit 3 can be caused to output the multiply-accumulate signal in the common output period T. Therefore, the precision of the multiply-accumulate operation can be improved. It should be noted that the threshold value corresponds to a threshold value based on a maximum value.

Further, the inventors newly devised to perform charging based on the maximum value of the positive sum value and the negative sum value in the plurality of analog circuits 3, and perform threshold determination using the threshold based on the maximum value of the positive sum value and the negative sum value in the plurality of analog circuits 3. That is, the inventors devised to compare the positive sum value and the negative sum value of each analog circuit 3 on all of the plurality of analog circuits 3, perform charging based on the maximum value among them, and perform threshold determination using a threshold value based on the maximum value.

Here, the maximum value of the positive sum value and the negative sum value in the plurality of analog circuits 3 is defined as a maximum sum value.

The positive or negative weight charge associated with the maximum sum value is defined as the maximum weight charge. For example, assume that the positive sum value of one analog circuit 3 of the plurality of analog circuits 3 is the maximum sum value. The positive charge output from the positive charge output line 7a in the analog circuit 3 is the maximum weight charge in the input period T.

Alternatively, it is assumed that the negative sum value of one analog circuit 3 is the maximum sum value. Then in the input period T, the negative charge output from the negative charge output line 7b in the analog circuit 3 is the maximum weight charge.

It should be noted that the maximum weight charge is a parameter that is independent of the level of the input signal and the like. That is, the positive weight charge or the negative weight charge (which is a maximum sum value) output from the positive weight output line or the negative weight output line is the maximum weight charge regardless of what signal is input as the input signal.

A positive charge output line or a negative charge output line from which the most weighted charge is output is defined as a maximum charge output line.

In the configurations shown in fig. 12 and 13, the combined resistance of the resistors 17 connected to the maximum charge output line is used as the common resistance value. Then, the resistance values of all the resistors 20a and 20b are unified to the common resistance value. In this case, charging according to the common time constant is achieved within the output period T. It should be noted that the combined resistance of the resistors 17 connected to the maximum charge output line is a parameter corresponding to the maximum sum value.

Such charging corresponds to charging in which the time constant associated with the output of the maximum weight charge to the maximum charge output line is used as the common time constant.

The threshold value is determined based on the input period T according to a time constant curve, which is collectively defined by resistance values. Accordingly, each analog circuit 3 can be caused to output the multiply-accumulate signal in the common output period T. Therefore, the precision of the multiply-accumulate operation can be improved. It should be noted that the threshold value corresponds to a threshold value based on the maximum sum value.

It should be noted that the sum of the weights of the analog circuits 3 in which all the resistors 17 are connected to only one of the positive charge output line and the negative charge output line is assumed to be the maximum value among the plurality of analog circuits 3. In this case, the maximum value of the weight sum value is also the maximum sum value, which is the maximum value of the positive sum value and the negative sum value. Therefore, charging is performed in the same charging mode, and the threshold determination is performed using the same threshold.

In the configuration shown in fig. 12 and 13, in the case where the charging signal in the output period T is input to the output line to which all the resistors 17 included in the analog circuit 3 are connected in parallel, the threshold value is set according to the time constant curve, and the sum value of the weights of the analog circuit is the maximum value. It should be noted that in practice there is not always an output line to which all the resistors 17 included in the analog circuit 3 whose weight sum value is the maximum value are coupled in parallel.

By setting such a threshold value, the multiply-accumulate signal can be output in each analog circuit 3 during the common output period T. Therefore, the precision of the multiply-accumulate operation can be improved. It should be noted that the threshold value corresponds to a threshold value based on a maximum value.

Further, in the case where the charging signal is input in the output period T, the threshold is set to the maximum charge output line according to the time constant curve. Therefore, the multiply-accumulate signal can be output in each analog circuit 3 during the common output period T. Therefore, the precision of the multiply-accumulate operation can be improved. It should be noted that the threshold value corresponds to a threshold value based on the maximum sum value.

It should be noted that the sum of the weights of the analog circuits 3 in which all the resistors 17 are connected to only one of the positive charge output line and the negative charge output line is assumed to be the maximum value among the plurality of analog circuits 3. In this case, the maximum value of the weight sum value is also the maximum sum value of the maximum values of the positive sum value and the negative sum value. Therefore, the threshold determination is performed with the same threshold value.

Of course, the present technique is not limited to such charging modes and setting of thresholds. Any configuration and method of implementing charging according to a common charging mode and determining a threshold using a common threshold may be employed. Further, these configurations and methods may be combined with the configurations and methods and the like for realizing the multiply-accumulate operation shown in fig. 9 described above.

Fig. 14 is a schematic diagram showing a configuration example of a neural network. For example, as shown in fig. 14, the neural network is realized by performing a plurality of multiply-accumulate operations, a plurality of normalization processes, and a plurality of pooling processes.

Here, the multiply-accumulate operation corresponds to outputting a plurality of multiply-accumulate results through the arithmetic apparatus 100 including a plurality of analog circuits 3. The normalization processing is processing of normalizing an input signal for input of a multiply-accumulate operation of the next stage. The pooling process is a process of reducing the number of input signals according to the number of inputs of the multiply-accumulate operation of the next stage. By the normalization processing and the pooling processing, the processing can be simplified and the processing time can be shortened.

It should be noted that, in fig. 14, a case is shown where the arithmetic device 100 that performs each of the multiply-accumulate operations 1 to 8 is constituted by a plurality of analog circuits 3 designed with a common time constant. That is, charging according to the common time constant is performed in the common charging mode in each arithmetic device 100.

In each arithmetic device 100, the common input period T and the common threshold θ are set based on a common time constant curve. On the other hand, in the example shown in fig. 14, different input periods T and different thresholds are set for different arithmetic devices 100. The technique of the present invention is not limited to this, and the common input period T and the common threshold θ may be set for all the arithmetic devices 100.

Of course, the arithmetic device 100 is constituted by analog circuits 3 each having another configuration and capable of performing a multiply-accumulate operation. Also in this case, efficient and high-speed arithmetic processing can be realized by setting the common charge mode and the common threshold in each analog circuit 3.

As described above, in the arithmetic device 100 according to the present embodiment, the common charging mode is executed for one or more analog circuits 3 and the common threshold value is set. Therefore, efficient and high-speed arithmetic processing can be realized in an analog circuit that performs a multiply-accumulate operation. That is, by arranging a plurality of sets of a plurality of analog circuits 3 in parallel, it is possible to simultaneously perform parallel operations by one input, and to realize high-speed operations and efficient operations.

< other examples >

The present technology is not limited to the above-described embodiments, and various other embodiments may be implemented.

Fig. 15 is a schematic circuit diagram showing another example of the analog circuit 3 according to the PWM method. In the analog circuit 3 shown in fig. 15, two current sources 25a and 25b are provided as the charging unit 15.

The current source 25a is connected to the side of the capacitor 13a connected to the positive charge output line 7a (the side opposite to GND) via the switch 16 c. The current source 25b is connected to the side of the capacitor 13b connected to the negative charge output line 7b (the side opposite to GND) via the switch 16 d.

In the analog circuit 3 shown in fig. 15, the capacitors 13a and 13b are charged by the current sources 25a and 25b at the same charging speed. Therefore, the potential V of the positive charge output line 7a⁺(voltage held by capacitor 13 a) and potential V of negative charge output line 7b^-(the voltage held by the capacitor 13b) is raised. The specific configuration of the current source 25 is not limited and may be designed arbitrarily.

Even in the case of adopting such a configuration, charging according to the common charging mode and threshold determination using the common threshold can be performed for one or more analog circuits 3. For example, in the case where a plurality of analog circuits 3 are arranged in parallel, charging according to a common charging mode and threshold determination using a common threshold are performed. Therefore, efficient and high-speed arithmetic processing can be realized.

Fig. 16 is a schematic circuit diagram showing another example of the analog circuit 3 according to the PWM method. Fig. 17 is a diagram for describing an example of calculation of the multiply-accumulate signal of the analog circuit 3 shown in fig. 16.

In the analog circuit 3 shown in fig. 16, the differential amplification circuit 26 outputs the electric charges (V) corresponding to the difference between the total amount of the positive-weight electric charges and the total amount of the negative-weight electric charges⁺-V^-) And an electric charge (V)⁺-V^-) Is stored in the capacitor 13 included in the accumulation unit 11. The specific structure of the differential amplifier circuit 26 is not limited and may be designed arbitrarily.

At the start timing of the input period T, the switches 16a, 16b, and 16c are turned on and the switch 16d is turned off. Then, the input signal is input for an input period T. The electric charge output from the differential amplifier circuit 26(V⁺-V^-) Accumulated in the capacitor 13. It should be noted that illustration of the charge accumulation state in the input period T is omitted in fig. 17.

At the end timing T of the input period T_nThe switch 16c is turned off and the switch 16d is turned on. Then, as shown in fig. 17, at the end timing T of the input period T, the timing T_nThe charging of the charging unit 15 (current source 25) is started.

Further, the comparator 22 of the signal output unit 12 detects the timing at which the voltage held by the capacitor 13 exceeds the threshold θ. Based on the detected timing, the signal generation unit 23 calculates a multiply-accumulate signal (PWM signal) "S_n(t)”。

Therefore, the difference (V) between the total amount of charge and the total amount of charge can be calculated by comparing the sum of the positive weight and the total amount of charge⁺-V^-) Outputting multiply-accumulate signal 'S' by threshold determination of corresponding charges_n(t) ". Further, charging according to a common charging mode and threshold determination using a common threshold may be performed for one or more analog circuits 3. For example, in the case where a plurality of analog circuits 3 are arranged in parallel, charging according to a common charging mode and threshold determination using a common threshold are performed. Therefore, efficient and high-speed arithmetic processing can be realized.

In the above description, the case where a plurality of analog circuits are arranged in parallel is mainly described. The present technique is not limited thereto, and may be applied to a single analog circuit. For example, the positive weight value accumulation unit and the negative weight value accumulation unit are charged in a common charging mode. Then, the positive weight charges and the negative weight charges are thresholded using a common threshold. Therefore, efficient and high-speed arithmetic processing can be realized.

In the above description, the case where the multiply-accumulate signal is output based on the timing at which the voltage held by the accumulation unit increases beyond the threshold has been exemplified. However, a configuration may be adopted in which the multiply-accumulate signal is output based on the timing at which the voltage held by the accumulation unit decreases by more than the threshold voltage. For example, charging is performed in advance until the voltage of the capacitor serving as the accumulation unit reaches a predetermined preset value. After the sum of the electric charges each corresponding to the product value of the signal value and the weight value is accumulated, the capacitor is discharged at a predetermined rate. In this case, the multiply-accumulate signal may be output based on the timing at which the voltage held by the capacitor decreases by more than the threshold. Of course, the present technique is not limited to this configuration. It should be noted that in the present disclosure, negatively charging the capacitor includes discharging the capacitor.

In the above description, the case of using a pair of output lines has been described. The present technology is not limited thereto, and three or more output lines may be provided. That is, the above-described technique of the present invention can also be applied to a case where one or a plurality of arbitrary number of output lines are used. For example, the multiplication unit includes a resistor that is connected between an associated input line and any one of one or more output lines and defines a weight value, and outputs a charge corresponding to the product value to the output line to which the resistor is connected. Of course, the present technology is not limited thereto.

The configurations of the arithmetic apparatus, the multiply-accumulate device, the analog circuit, the synapse circuit, the neuron circuit, and the like, the method of generating the multiply-accumulate signal, and the like described above with reference to the drawings belong only to embodiments, and may be arbitrarily modified without departing from the gist of the present technology. That is, any other configurations, methods, etc. for performing the techniques of the present invention may be employed.

In the present disclosure, the terms "identical," "equal," "orthogonal," "parallel," and the like, include "substantially identical," "substantially equal," "substantially orthogonal," "substantially parallel," "and the like. For example, states within a predetermined range (e.g., a range of ± 10%) with reference to "identical", "completely orthogonal", "completely parallel", and the like are also included.

At least two of the features of the present technology described above may also be combined. In other words, various features described in the respective embodiments may be arbitrarily combined regardless of the embodiments. Further, the above-described various effects are not restrictive but merely illustrative, and other effects may be provided.

It should be noted that the present technology can also adopt the following configuration.

(1) An arithmetic device comprising:

a plurality of input lines to each of which an electric signal corresponding to an input value is input in a predetermined input period; and

one or more multiply-accumulate units, each multiply-accumulate unit comprising

A plurality of multiplication units that generate charges corresponding to product values obtained by multiplying the input values by weight values based on the electric signals input to each of the plurality of input lines,

an accumulation unit that accumulates charges corresponding to the product value generated by each of the plurality of multiplication units,

a charging unit that charges the accumulation unit in which the electric charge corresponding to the product value is accumulated after the input period, and

an output unit that outputs a multiply-accumulate signal representing a sum of the product values by performing threshold determination on the voltage held by the accumulation unit using a predetermined threshold after charging is started by the charging unit, wherein

In the one or more multiply-accumulate devices, the charging by the charging unit is performed in a common charging mode, and a common threshold is set to the predetermined threshold.

(2) The arithmetic device according to (1), wherein

The one or more multiply-accumulate devices are a plurality of multiply-accumulate devices connected in parallel to the plurality of input lines.

(3) The arithmetic device according to (1) or (2), wherein

The common charging mode includes charging supplied with the same charging signal during a common charging period.

(4) The arithmetic device according to any one of (1) to (3), wherein

The common charging mode includes charging at a common charging speed.

(5) The arithmetic device according to any one of (1) to (4), wherein

The common charging mode includes charging according to a common time constant.

(6) The arithmetic device according to any one of (1) to (5), wherein

Defining a sum of absolute values of the weight values set in the plurality of multiplication units as a weight sum value, the common charge mode including charge based on a maximum value of the weight sum value in the one or more multiply-accumulate devices.

(7) The arithmetic device according to (5) or (6), wherein

Each of the one or more multiply-accumulate devices includes a charge output line,

the plurality of multiplication units output charges corresponding to the product values to the charge output lines, an

The common charging mode includes charging in which a time constant associated with outputting the electric charge corresponding to the product value to the electric charge output line by the plurality of multiplication units whose sum value of weights is a maximum value is used as the common time constant.

(8) The arithmetic device according to any one of (1) to (7), wherein

The common threshold is set based on a duration of the input period.

(9) The arithmetic device according to any one of (1) to (8), wherein

Defining a sum of absolute values of the weight values set in the plurality of multiplication units as a weight sum value, the common threshold being set based on a maximum value of the weight sum values in the one or more multiply-accumulate devices.

(10) The arithmetic device according to any one of (1) to (9), wherein

The common charging mode includes charging supplied with the same charging signal during the common charging period, and

the charging unit includes a charging line connected to the accumulation unit and supplying the same charging signal to the accumulation unit during the common charging period.

(11) The arithmetic device according to any one of (1) to (9), wherein

The common charging mode includes charging supplied with the same charging signal during the common charging period, and

the charging unit supplies the same charging signal to the accumulation unit via the plurality of input lines during the common charging period.

(12) The arithmetic device according to any one of (1) to (11), wherein

The plurality of multiplication units include at least one of a positive weight multiplication unit that generates a positive weight charge corresponding to a product value obtained by multiplying the input value by a positive weight value and a negative weight multiplication unit that generates a negative weight charge corresponding to a product value obtained by multiplying the input value by a negative weight value,

the accumulation unit includes a positive charge accumulation unit capable of accumulating the positive weight charges generated by the positive weight multiplication unit and a negative charge accumulation unit capable of accumulating the negative weight charges generated by the negative weight multiplication unit,

the charging unit charges the positive charge accumulation unit and the negative charge accumulation unit in the common charging mode, and

the output unit outputs the multiply-accumulate signal by thresholding each of the positive charge accumulation unit and the negative charge accumulation unit using the common threshold.

(13) The arithmetic device according to (12), wherein

Defining a sum of the positive weight values set in the plurality of multiplication units as a positive sum value, and defining a sum of absolute values of the negative weight values as a negative sum value, the common charging pattern including charging based on a maximum value of the positive sum value and the negative sum value in the one or more multiply-accumulate means.

(14) The arithmetic device according to (13), wherein

Each of the one or more multiply-accumulate devices includes a positive charge output line and a negative charge output line,

the positive charge multiplying unit outputs the positive weight charges to the positive charge output line,

the negative charge multiplying unit outputs the negative weight charges to the negative charge output line, an

Assuming that the maximum value of the positive sum value and the negative sum value in the one or more multiply-accumulate devices is a maximum sum value

The positive weight charge or the negative weight charge associated with the maximum sum value is the maximum weight charge, an

The positive charge output line or the negative charge output line from which the maximum weight charge is output is a maximum charge output line,

defining a time constant associated with output of the maximum weight charges to the maximum charge output line as a common time constant, the common charging mode including charging according to the common time constant.

(15) The arithmetic device according to any one of (12) to (14), wherein

Defining a sum of the positive weight values set in the plurality of multiplication units as a positive sum value, and defining a sum of absolute values of the negative weight values as a negative sum value, the common threshold being set based on a maximum value of the positive sum value and the negative sum value in the one or more multiply-accumulate means.

(16) The arithmetic device according to any one of (12) to (15), wherein

Absolute values of the positive weight value and the negative weight value are fixed to the same value, set to any one of a plurality of values different from each other, or randomly set, and

in the one or more multiply-accumulate means, a value obtained by adding the positive sum value and the negative sum value is a common value.

(17) The arithmetic device according to any one of (12) to (15), wherein

Absolute values of the positive weight value and the negative weight value are fixed to the same value, set to any one of a plurality of values different from each other, or randomly set, and

in the one or more multiply-accumulate means, a value obtained by adding the positive sum value and the negative sum value is a random value.

(18) The arithmetic device according to any one of (12) to (17), wherein

The common charging mode includes charging supplied with the same charging signal during the common charging period, and

the charging unit includes charging lines connected to the positive charge accumulation unit and the negative charge accumulation unit and supplying the same charging signal to the positive charge accumulation unit and the negative charge accumulation unit during the common charging period.

(19) The arithmetic device according to any one of (12) to (18), wherein

The common charging mode includes charging supplied with the same charging signal during the common charging period, and

the charging unit supplies the same charging signal to the positive charge accumulating unit and the negative charge accumulating unit via the plurality of input lines during the common charging period.

(20) A multiply-accumulate system comprising:

a plurality of input lines to each of which an electric signal corresponding to an input value is input in a predetermined input period;

one or more analog circuits, each analog circuit comprising

A plurality of multiplication units that generate charges corresponding to product values obtained by multiplying the input values by weight values based on the electric signals input to each of the plurality of input lines,

an accumulation unit that accumulates charges corresponding to the product value generated by each of the plurality of multiplication units,

a charging unit that charges the accumulation unit in which the electric charge corresponding to the product value is accumulated after the input period, and

an output unit that outputs a multiply-accumulate signal representing a sum of the product values by performing threshold determination on the voltage held by the accumulation unit using a predetermined threshold after charging is started by the charging unit; and

a network circuit configured by connecting a plurality of analog circuits, wherein

In the one or more analog circuits, charging by the charging unit is performed in a common charging mode, and a common threshold is set to the predetermined threshold.

(21) The arithmetic device according to any one of (1) to (19), wherein

The electric signal corresponding to the input value is a pulse signal whose ON time with respect to the input period corresponds to the input value.

(22) The arithmetic device according to any one of (1) to (19) and (21), wherein

The duration of the common charging period is equal to the input period.

List of reference numerals

T input period

Threshold value of theta

1 signal line

3 analog circuit

6 input signal line

7a pair of output lines

7a positive charge output line

7b negative charge output line

8 synaptic electrical circuits (multiplication units)

8a synaptic electrical circuit (positive weight multiplication unit)

8b synaptic electrical circuit (negative weight multiplication unit)

9 neuron circuit

10 output signal line

11 accumulation unit

12 signal output unit

13 capacitor

15 charging unit

17 resistor

17a positive resistor

17b negative resistor

19 charging wire

20, 20a, 20b resistor in the charging unit

22, 22a, 22b comparator

23 Signal generating Unit

25, 25a, 25b current source

26 differential amplifier circuit

100 arithmetic devices.