A kind of highly linear variable gain amplifier
阅读说明：本技术 一种高线性可变增益放大器 (A kind of highly linear variable gain amplifier ) 是由 李翔宇 胡建平 于 2019-08-07 设计创作，主要内容包括：本发明公开了一种可变增益放大器,所述增益放大器包括输入PMOS差分晶体管MP1和MP2,负载电流源I<Sub>L1</Sub>、I<Sub>L2</Sub>和I<Sub>R</Sub>,负载晶体管MP3、MP4、MP5和MP6,共源共栅晶体管MN1、MN2、MN3和MN4。本发明采用负载跨导降低技术,使得输出阻抗显著增加,基于单级运放结构能够获得高增益的特性。本发明结合时间增益补偿技术,能够实现高线性的可变增益放大器。本发明相对于传统的可变增益放大器而言,电压增益范围更大,结构简单,功耗较低。(The invention discloses a kind of variable gain amplifier, the gain amplifier includes input PMOS difference transistor MP1 and MP2, load current source I L1 、I L2 And I R , load transistor MP3, MP4, MP5 and MP6, cascode transistors MN1, MN2, MN3 and MN4.The present invention, which reduces technology using load mutual conductance, can obtain the characteristic of high-gain based on single-stage amplifier structure so that output impedance is dramatically increased.Binding time gain compensation technology of the present invention, can be realized the variable gain amplifier of High Linear.The present invention is for traditional variable gain amplifier, and voltage gain range is bigger, and structure is simple, and power consumption is lower.)
1. a kind of variable gain amplifier, it is characterised in that the gain amplifier include input PMOS difference transistor MP1 and MP2, load current source IL1、IL2And IR, load transistor MP3, MP4, MP5 and MP6, cascode transistors MN1, MN2, MN3 And MN4, in which:
The load current source IL1A termination power VCC, the source electrode of another termination input PMOS difference transistor MP1, simultaneously Connect the source electrode of input PMOS difference transistor MP2；
The grid of the input PMOS difference transistor MP1 meets input signal Vip, and drain electrode connects the source of cascode transistors MN1 Pole, while connecing the drain electrode of cascode transistors MN3；
The grid of the input PMOS difference transistor MP2 meets input signal Vin, and drain electrode connects the source of cascode transistors MN2 Pole, while connecing the drain electrode of cascode transistors MN4；
The source electrode of the cascode transistors MN3 is grounded, and grid is connected with the grid of cascode transistors MN4, while with The drain electrode of cascode transistors MN1, the grid of load transistor MP3 and drain electrode, the drain electrode of load transistor MP4 and MP5 Grid is connected；
The source electrode of the cascode transistors MN4 is grounded, and drain electrode is connected with the source electrode of cascode transistors MN2；
The grid of the cascode transistors MN1 is connected with the grid of cascode transistors MN2, while connecing bias voltage Vb；
The drain electrode of the cascode transistors MN2 meets output Vout, at the same with the grid of load transistor MP6 and drain electrode, negative The drain electrode for carrying transistor MP5 is connected with the grid of MP4；
The source electrode of the load transistor MP3 with load transistor MP6 source electrode be connected, while with load current source IROne end It is connected；
The load current source IRAnother termination power VCC；
The source electrode of the load transistor MP4 with load transistor MP5 source electrode be connected, while with load current source IL2One end It is connected；
The load current source IL2Another termination power VCC.
2. variable gain amplifier according to claim 1, it is characterised in that the load current source IRFor fixed current value Current source.
3. variable gain amplifier according to claim 1, it is characterised in that the load current source IL1And IL2Being can The current source of power transformation flow valuve.
4. variable gain amplifier according to claim 1, it is characterised in that described load transistor MP3, MP4, MP5 and The breadth length ratio of MP6 is equal.
5. variable gain amplifier according to claim 1, it is characterised in that the gain of the gain amplifier is expressed as:
In formula, gmp1For the mutual conductance of input pipe, gmp3For the mutual conductance of load transistor MP3, gmp4For the mutual conductance of load transistor MP4, WinFor the grid width of input pipe, WoutFor the grid width of output transistor, IL=IL1=IL2。
Technical field
The invention belongs to IC design and manufacturing technology field, it is related to a kind of linear highly linear variable gain of single-stage and puts Big device circuit.
Background technique
In wireless communication receiver system, the major function of variable gain amplifier is amplification small-signal, to keep Signal power level appropriate, to reduce the dynamic range for receiving circuit.Since the acquisition signal of reception circuit is largely Exponential damping, therefore variable gain amplifier is needed with linear gain characteristics.The gain of general variable gain amplifier is logical Often passed through by the rate control of circuit parameter, such as general open loop structure by inputting the mutual conductance rate control with load transistor Electric current is controlled to adjust voltage gain, it then follows approximate exponential gain functions.The variable gain amplifier level-one of general structure can The gain ranging of realization is in 30dB or so.Cascading multiple stages structure is then needed in order to obtain the voltage gain of 40dB or more, this can show It writes and increases chip power-consumption and area.
Summary of the invention
For problem above of the existing technology, the present invention provides a kind of variable gains with simple circuit structure Amplifier.
The purpose of the present invention is what is be achieved through the following technical solutions:
A kind of variable gain amplifier, including input PMOS difference transistor MP1 and MP2, load current source IL1、IL2With IR, load transistor MP3, MP4, MP5 and MP6, cascode transistors MN1, MN2, MN3 and MN4, in which:
The load current source IL1A termination power VCC, the source electrode of another termination input PMOS difference transistor MP1, The source electrode of input PMOS difference transistor MP2 is connect simultaneously；
The grid of the input PMOS difference transistor MP1 meets input signal Vip, and drain electrode meets cascode transistors MN1 Source electrode, while connecing the drain electrode of cascode transistors MN3；
The grid of the input PMOS difference transistor MP2 meets input signal Vin, and drain electrode meets cascode transistors MN2 Source electrode, while connecing the drain electrode of cascode transistors MN4；
The source electrode of the cascode transistors MN3 is grounded, and grid is connected with the grid of cascode transistors MN4, together When with the drain electrode of cascode transistors MN1, the grid of load transistor MP3 and drain electrode, the drain electrode of load transistor MP4 and The grid of MP5 is connected；
The source electrode of the cascode transistors MN4 is grounded, and drain electrode is connected with the source electrode of cascode transistors MN2；
The grid of the cascode transistors MN1 is connected with the grid of cascode transistors MN2, while connecing biased electrical Press Vb；
The drain electrode of the cascode transistors MN2 connect output Vout, while with the grid of load transistor MP6 and leakage Pole, the drain electrode of load transistor MP5 are connected with the grid of MP4；
The source electrode of the load transistor MP3 with load transistor MP6 source electrode be connected, while with load current source IR's One end is connected；
The load current source IRAnother termination power VCC；
The source electrode of the load transistor MP4 with load transistor MP5 source electrode be connected, while with load current source IL2's One end is connected；
The load current source IL2Another termination power VCC.
Compared with the prior art, the present invention has the advantage that
1, the present invention reduces technology using load mutual conductance, so that output impedance dramatically increases, is based on single-stage amplifier structure energy Enough obtain the characteristic of high-gain.
2, binding time gain compensation technology of the present invention, can be realized the variable gain amplifier of High Linear, linear gain Range is about 40dB.
3, the present invention is for traditional variable gain amplifier, and voltage gain range is bigger, and structure is simple, power consumption It is lower.
Detailed description of the invention
Fig. 1 is highly linear variable gain amplifier schematic block circuit diagram.
Specific embodiment
Further description of the technical solution of the present invention with reference to the accompanying drawing, and however, it is not limited to this, all to this Inventive technique scheme is modified or replaced equivalently, and without departing from the spirit and scope of the technical solution of the present invention, should all be covered Within the protection scope of the present invention.
The present invention provides a kind of highly linear variable gain amplifiers, as shown in Figure 1, the variable gain amplifier includes Input PMOS difference transistor MP1 and MP2, load current source IL1、IL2And IR, load transistor MP3, MP4, MP5 and MP6, altogether Source is total to gate transistor MN1, MN2, MN3 and MN4, in which:
The load current source IL1A termination power VCC, the source electrode of another termination input PMOS difference transistor MP1, The source electrode of input PMOS difference transistor MP2 is connect simultaneously；
The grid of the input PMOS difference transistor MP1 meets input signal Vip, and drain electrode meets cascode transistors MN1 Source electrode, while connecing the drain electrode of cascode transistors MN3；
The grid of the input PMOS difference transistor MP2 meets input signal Vin, and drain electrode meets cascode transistors MN2 Source electrode, while connecing the drain electrode of cascode transistors MN4；
The source electrode of the cascode transistors MN3 is grounded, and grid is connected with the grid of cascode transistors MN4, together When with the drain electrode of cascode transistors MN1, the grid of load transistor MP3 and drain electrode, the drain electrode of load transistor MP4 and The grid of MP5 is connected；
The source electrode of the cascode transistors MN4 is grounded, and drain electrode is connected with the source electrode of cascode transistors MN2；
The grid of the cascode transistors MN1 is connected with the grid of cascode transistors MN2, while connecing biased electrical Press Vb；
The drain electrode of the cascode transistors MN2 connect output Vout, while with the grid of load transistor MP6 and leakage Pole, the drain electrode of load transistor MP5 are connected with the grid of MP4；
The source electrode of the load transistor MP3 with load transistor MP6 source electrode be connected, while with load current source IR's One end is connected；
The load current source IRAnother termination power VCC；
The source electrode of the load transistor MP4 with load transistor MP5 source electrode be connected, while with load current source IL2's One end is connected；
The load current source IL2Another termination power VCC.
In the present invention, the load current source IRFor the current source of fixed current value, generally produced by band gap current reference Raw, any type of mutation belongs to protection category of the invention.
In the present invention, the load current source IL1And IL2It is the current source of variable current value, generally by with negative-feedback Voltage-controlled current source structure composition, any type of mutation belong to protection category of the invention.
In the present invention, the highly linear variable gain amplifier uses single step arrangement, and core circuit is by input difference to crystalline substance The compositions such as body pipe, cascode transistors, low mutual conductance load, variable tail current source.Load current source IL2With amplifier gain Increase and increase.The load current source I of diode type of attachmentRFor constant current source.The highly linear variable gain amplifier Gain may be expressed as:
It should be noted that load current source IL1=IL2, gmp1For the mutual conductance of input pipe, gmp3For transistor MP3 across It leads, gmp4For the mutual conductance of transistor MP4.WinFor the grid width of input pipe, WoutFor the grid width of output transistor.Input transistors and defeated The grid length of transistor is equal out.The breadth length ratio of load transistor MP3, MP4, MP5 and MP6 are equal, the gain arrived as available from the above equation By variable current source IL(IL=IL1=IL2) control, gain variation range is larger, AV/ILCurvilinear intermediate zone with dB be measure Approximately linear when unit.Binding time gain compensation technology, can be realized the variable gain amplifier of High Linear.Time gain is mended The technology of repaying is more mature gamma correction technology, is not belonging to elaboration content of the invention.
Highly linear variable gain amplifier of the invention can be applied in ultrasonic image-forming system, in this application for receiving The dynamic range requirement of circuit is higher, directly determines the resolution ratio of imaging system.It can be generated in ultrasound echo signal transmission Decaying, it is therefore desirable to real-time control voltage gain changes over time generated decaying to compensate ultrasound echo signal, and Voltage gain compensation should be increased in the form of logarithm with the time, meet the skill of highly linear variable gain amplifier of the invention Art feature.
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