阅读说明：本技术 封装结构的形成方法 (The forming method of encapsulating structure ) 是由 陶玉娟 戴颖 于 2019-07-25 设计创作，主要内容包括：一种封装结构的形成方法,提供具有第一塑封层的若干芯片,由于第一塑封层一般是通过注塑或转塑工艺形成,使得形成的第一塑封层具有平坦的表面,从而使得每一个半导体芯片表面均具有平坦的表面,在将若干分立的半导体芯片上的第一塑封层与载板进行粘合时,从而使得每一个半导体芯片与载板之间均具有较高的粘附力,当在载板上形成包覆若干半导体芯片的第二塑封层时,在受到注塑或转塑的压力冲击时,所有的半导体芯片在载板上位置都不会产生偏移,从而后续在去除载板后,在预封面板的背面形成与焊盘连接的再布线层时,再布线层与对应的焊盘的连接位置不会产生偏移,从而提高了再布线层与焊盘之间的电学连接性能。(A kind of forming method of encapsulating structure, several chips for having the first plastic packaging layer are provided, since the first plastic packaging layer is formed generally by injection molding or turn modeling technique, so that the first plastic packaging layer formed has flat surface, so that each semiconductor chip surface all has flat surface, when the first plastic packaging layer on several discrete semiconductor chips is bonded with support plate, so that all having higher adhesion strength between each semiconductor chip and support plate, when forming the second plastic packaging layer for coating several semiconductor chips on support plate, when being molded or turning the compression shock of modeling, all semiconductor chips position on support plate will not all generate offset, to subsequent after removing support plate, when the back side of preformed cover plate forms the wiring layer again connecting with pad, wiring layer will not with the link position of corresponding pad again Offset is generated, is electrically connected performance between wiring layer and pad again to improve.)

1. a kind of forming method of encapsulating structure characterized by comprising

There is provided several semiconductor chips, each semiconductor chip includes functional surfaces and the non-functional surface opposite with functional surfaces, described There are several pads on functional surfaces, metal coupling is formed in the bond pad surface, also there is the first plastic packaging on the functional surfaces Layer, the first plastic packaging layer cover the metal coupling；

Support plate is provided；

The first plastic packaging layer on the functional surfaces of several semiconductor chips is bonded on support plate；

The second plastic packaging layer of the non-functional surface and sidewall surfaces that coat the semiconductor chip is formed on the support plate；

The support plate is removed, preformed cover plate is formed, the preformed cover back exposes the first plastic packaging layer；

Part the first plastic packaging layer and the second plastic packaging layer for removing the preformed cover back, expose the metal coupling Top surface；

The external contact structure connecting with metal coupling is formed at the back side of the preformed cover plate.

2. the forming method of encapsulating structure as described in claim 1, which is characterized in that the forming process of the semiconductor chip Are as follows: wafer is provided, is formed with several semiconductor chips on the wafer, the semiconductor chip includes functional surfaces, the function There is pad on face；Metal coupling is formed on the pad；Form the first plastic packaging for covering the metal coupling and functional surfaces Layer；After forming the first plastic packaging layer, the wafer is cut, forms several discrete semiconductor chips.

3. the forming method of encapsulating structure as claimed in claim 2, which is characterized in that the first plastic packaging layer and the second plastic packaging The material of layer is resin, and the formation process of the first plastic packaging layer and the second plastic packaging layer is to be molded or turn modeling technique.

4. the forming method of encapsulating structure as claimed in claim 3, which is characterized in that material granule in the first plastic packaging layer Size less than material granule in the second plastic packaging layer size.

5. the forming method of encapsulating structure as described in claim 1, which is characterized in that removed by chemical mechanical milling tech The part of the preformed cover back the first plastic packaging layer and the second plastic packaging layer, expose the metal coupling top surface.

6. the forming method of encapsulating structure as claimed in claim 1 or 2, which is characterized in that the top table of the metal coupling Face or top and sidewall surfaces are formed with isolation sacrificial layer, and the first plastic packaging layer also covers the isolation sacrificial layer.

7. the forming method of encapsulating structure as claimed in claim 6, which is characterized in that removed using chemical mechanical milling tech The part of the preformed cover back the first plastic packaging layer and the second plastic packaging layer, expose the isolation sacrificial layer surface；It adopts With the isolation sacrificial layer on etching technics removal metal coupling top surface, the top table of the metal coupling is exposed Face.

8. the forming method of encapsulating structure as claimed in claim 7, which is characterized in that the etching technics be wet etching or Dry etching.

9. the forming method of encapsulating structure as claimed in claim 6, which is characterized in that the material of the isolation sacrificial layer is oxygen SiClx, silicon nitride or silicon oxynitride.

10. the forming method of encapsulating structure as described in claim 1, which is characterized in that the external contact structure includes position It is connect in the wiring layer again being connect on the preformed cover version back side with metal coupling and on wiring layer again with wiring layer again External contacts.

11. the forming method of encapsulating structure as claimed in claim 11, which is characterized in that the wiring layer again and external contact The forming process of part includes: to form wiring layer again on the back side of the preformed cover plate after removing the support plate；It is being routed again Insulating layer is formed on the back side of layer and preformed cover version, forms the opening for exposing wiring layer part of the surface again in the insulating layer； External contacts are formed in said opening.

12. the forming method of encapsulating structure as described in claim 1, which is characterized in that the external contact structure is being formed, Further include: the preformed cover plate is cut, several discrete encapsulating structures are formed.

Technical field

The present invention relates to field of semiconductor fabrication more particularly to a kind of forming methods of fan-out package structure.

Background technique

The encapsulation of chip fan-in type is to be routed to prepare with solder ball salient point again in whole wafer, is finally cut into list again A kind of production method of chips.The final encapsulation size of this kind encapsulation is suitable with chip size, and the small-sized of encapsulation may be implemented Change and lightweight, have a wide range of applications in a portable device.After although encapsulation can be greatly reduced in the encapsulation of chip fan-in type Chip size, but the plant ball limited amount in single chip, the wafer level packaging form are dfficult to apply to the port high density I/O On several chips.Thus, chip higher for I/O density ratio, if carrying out wafer level packaging, in order to ensure chip to be packaged It is capable of forming the packaging pin that interconnects and highdensity I/O must be fanned out to as low-density with printed wiring board, that is, carries out chip Fan-out package is encapsulated relative to traditional chip fan-in type, the available smaller package dimension of chip fan-out package, more Good electricity thermal property and higher packaging density.

Currently, the main process of chip fan-out package includes: first that several semiconductor chips after segmentation are positive (just Face is the one side for being formed with pad) it is bonded on support plate by adhesive tape or adhesive layer；Covering semiconductor chip is formed on support plate Plastic packaging layer, on support plate several semiconductor chips carry out plastic packaging；Remove the support plate, then semiconductor chip front into Row is routed again, forms the wiring layer again connecting with pad；The tin ball connecting with wiring layer again is formed on wiring layer again；It is most laggard Row cutting, forms several discrete encapsulating structures.

But the encapsulating structure that existing chip fan-out package technique is formed, then the electricity company of wiring layer and semiconductor chip It connects and is easy unstable, affect the performance of encapsulating structure.

Summary of the invention

Cloth again in the encapsulating structure formed the technical problem to be solved by the present invention is to improve chip fan-out package technique Line layer and semiconductor chip are electrically connected stability, improve the performance of encapsulating structure.

The present invention provides a kind of forming methods of encapsulating structure, comprising:

Several semiconductor chips are provided, each semiconductor chip includes functional surfaces and the non-functional surface opposite with functional surfaces, There are several pads on the functional surfaces, metal coupling is formed in the bond pad surface, also has first on the functional surfaces Plastic packaging layer, the first plastic packaging layer cover the metal coupling；

Support plate is provided；

The first plastic packaging layer on the functional surfaces of several semiconductor chips is bonded on support plate；

The second plastic packaging layer of the non-functional surface and sidewall surfaces that coat the semiconductor chip is formed on the support plate；

The support plate is removed, preformed cover plate is formed, the preformed cover back exposes the first plastic packaging layer；

Part the first plastic packaging layer and the second plastic packaging layer for removing the preformed cover back, it is convex to expose the metal The top surface of block；

The external contact structure connecting with metal coupling is formed at the back side of the preformed cover plate.

Optionally, the forming process of the semiconductor chip are as follows: wafer is provided, if being formed with dry semiconductor on the wafer Chip, the semiconductor chip include functional surfaces, have pad on the functional surfaces；Metal coupling is formed on the pad； Form the first plastic packaging layer for covering the metal coupling and functional surfaces；After forming the first plastic packaging layer, the wafer, shape are cut At several discrete semiconductor chips.

Optionally, the material of the first plastic packaging layer and the second plastic packaging layer is resin, the first plastic packaging layer and the second modeling The formation process of sealing is to be molded or turn modeling technique.

Optionally, in the first plastic packaging layer material granule size less than material granule in the second plastic packaging layer size.

Optionally, the part for the preformed cover back being removed by chemical mechanical milling tech the first plastic packaging layer and Second plastic packaging layer exposes the metal coupling top surface.

Optionally, the top surface of the metal coupling or top and sidewall surfaces are formed with isolation sacrificial layer, described First plastic packaging layer also covers the isolation sacrificial layer.

Optionally, the part for the preformed cover back being removed using chemical mechanical milling tech the first plastic packaging layer and Second plastic packaging layer exposes the isolation sacrificial layer surface；Described on etching technics removal metal coupling top surface Sacrificial layer is isolated, exposes the top surface of the metal coupling.

Optionally, the etching technics is wet etching or dry etching.

Optionally, the material of the isolation sacrificial layer is silica, silicon nitride or silicon oxynitride.

Optionally, the external contact structure includes the cloth again connecting on the preformed cover version back side with metal coupling Line layer and the external contacts being connect on wiring layer again with wiring layer again.

Optionally, the forming process of the wiring layer again and external contacts includes: after removing the support plate, described Wiring layer again is formed on the back side of preformed cover plate；Insulating layer, the insulation are formed on the back side of wiring layer again and preformed cover version The opening for exposing wiring layer part of the surface again is formed in layer；External contacts are formed in said opening.

Optionally, the external contact structure is being formed, further includes: cut the preformed cover plate, formed several discrete Encapsulating structure.

Compared with prior art, technical solution of the present invention has the advantage that

The forming method of encapsulating structure of the invention provides several semiconductor chips, the functional surfaces of each semiconductor chip It is upper that there is pad, it is formed with metal coupling in the bond pad surface, also there is the first plastic packaging layer on the functional surfaces, described first Plastic packaging layer covers the metal coupling；The first plastic packaging layer on the functional surfaces of several semiconductor chips is bonded in support plate On；The second plastic packaging layer of the non-functional surface and sidewall surfaces that coat the semiconductor chip is formed on the support plate.Due to One plastic packaging layer is formed generally by injection molding or turn modeling technique, so that the first plastic packaging layer formed has flat surface, thus So that each semiconductor chip surface all has flat surface, by the first plastic packaging on several discrete semiconductor chips When layer is bonded with support plate so that all have higher adhesion strength between each semiconductor chip and support plate, when When forming the second plastic packaging layer for coating several semiconductor chips on support plate, when being molded or turning the compression shock of modeling, own Semiconductor chip will not all generate offset in position on support plate, thus subsequent after removing support plate, preformed cover plate is formed, pre- When the back side of cover board forms the wiring layer again connecting with pad, then wiring layer will not be generated with the link position of corresponding pad Offset, be electrically connected performance between wiring layer and pad again to improve, thus improve encapsulating structure stability and Reliability.

Further, before forming the first plastic packaging layer, at the top surface of the metal coupling or top and side wall table Face is formed with isolation sacrificial layer, then forms the first plastic packaging layer of the covering isolation sacrificial layer, thus by aforementioned specific Structure it is subsequent can by chemical mechanical milling tech and etching both combine special process remove part the first plastic packaging layer and Second plastic packaging layer is to expose metal coupling, specifically, first removing part first plastic packaging using chemical mechanical milling tech Layer and the second plastic packaging layer, expose isolation sacrificial layer surface, then using on etching technics removal metal coupling top surface The isolation sacrificial layer, exposes the top surface of metal coupling, thus not only by aforementioned specific structure and specific technique The top surface of metal coupling can be exposed, and due to removing part the first plastic packaging layer using chemical mechanical milling tech When with the second plastic packaging layer, exposure is isolation sacrificial layer surface, and the grinding pad in milling apparatus will not be contacted with metal coupling, because Without bringing abrasive power to metal coupling, loosens or fall off from pad to preferably prevent metal coupling from generating, into One step improves the precision of link position between the wiring layer again and corresponding metal coupling being subsequently formed, and further improves cloth again Line layer and metal coupling are electrically connected performance.

Further, the forming process of the semiconductor chip are as follows: wafer is provided, if being formed with dry semiconductor on the wafer Chip, the semiconductor chip include functional surfaces, have pad on the functional surfaces；Metal coupling is formed on the pad； The first plastic packaging layer of the covering metal coupling and functional surfaces is formed by being molded or turning modeling technique；Form the first plastic packaging layer Afterwards, the wafer is cut, several discrete semiconductor chips are formed.When be molded or turn modeling technique, bottom is solid Due in mold, since the area of bottom is larger, wafer will not move in the mold for being molded or turning modeling equipment, so that The the first plastic packaging layer formed has flat surface, after being cut wafer, several discrete semiconductor chips of formation Flat surface is all had, and the thickness of several semiconductor chips is able to maintain unanimously, by several discrete semiconductor chips On the first plastic packaging layer and support plate when being bonded, since the first plastic packaging layer has flat surface, so that each semiconductor Higher adhesion strength is all had between chip and support plate.

Further, the size of material granule is less than material in the second plastic packaging layer being subsequently formed in the first plastic packaging layer The size of grain enables the first plastic packaging layer more preferably to fill between metal coupling and the gap of two sides, so that the first plastic packaging layer and gold Belong to the contact of the side of convex block more closely so that the first plastic packaging layer is more preferable to the fixed effect of metal coupling, it is subsequent When chemical mechanical milling tech being used to planarize the top surface of the first plastic packaging layer and the second plastic packaging layer to expose metal coupling, It can preferably prevent from metal coupling from generating to loosen or fall off from pad, and can prevent from grinding crossing for metal coupling.

Detailed description of the invention

Fig. 1-Figure 19 is the structural schematic diagram of the forming process of encapsulating structure of the embodiment of the present invention.

Specific embodiment

As described in the background art, the encapsulating structure that existing chip fan-out package technique is formed, then wiring layer and semiconductor Being electrically connected of chip is easy unstable, affects the performance of encapsulating structure.

The study found that in existing fan-out package structure again wiring layer and semiconductor chip be electrically connected be easy it is unstable Producing reason are as follows: the link position of the pad of wiring layer and semiconductor chip produces offset again.

Further study show that then the link position of pad of wiring layer and semiconductor chip the reason of producing offset Are as follows: when carrying out being fanned out to encapsulation, several semiconductor chips are be bonded in load by adhesive tape or adhesive layer on one side with pad It is different especially when being also formed with metal coupling on pad since different semiconductor chip surface flatness is different on plate The surface smoothness difference of chip can be bigger, so that different semiconductor chips and support plate pass through adhesive tape or adhesive layer is Nian Jie is glued When connecing, the bonding force between different semiconductor chips and support plate be it is different, when forming plastic packaging layer, part semiconductor chip due to Bonding force is insufficient, which can generate offset, After removing support plate, when forming wiring layer again on the front of plastic packaging layer and semiconductor chip so that again wiring layer with there are positions The link position for setting the pad of the semiconductor core on piece of offset generates offset, to influence in the fan-out packaging structure to be formed cloth again Line layer and pad are electrically connected performance.

For this purpose, the present invention provides a kind of encapsulating structure and forming method thereof, the forming method, if providing dry semiconductor Chip has pad on the functional surfaces of each semiconductor chip, is formed with metal coupling, the functional surfaces in the bond pad surface On also there is the first plastic packaging layer, the first plastic packaging layer covers the metal coupling；By the function of several semiconductor chips The first plastic packaging layer on face is bonded on support plate；Non-functional surface and the side for coating the semiconductor chip are formed on the support plate Second plastic packaging layer of wall surface.Since the first plastic packaging layer is formed generally by injection molding or turn modeling technique, so that formed first Plastic packaging layer has flat surface, so that each semiconductor chip surface all has flat surface, by several points When first plastic packaging layer of vertical semiconductor core on piece and support plate are bonded so that each semiconductor chip and support plate it Between all have higher adhesion strength, when forming the second plastic packaging layer for coating several semiconductor chips on support plate, infused When the compression shock of modeling or turn modeling, all semiconductor chips position on support plate will not all generate offset, so that subsequent going After support plate, formed preformed cover plate, preformed cover plate the back side formed connect with pad wiring layer again when, then wiring layer with it is right The link position for the pad answered will not generate offset, be electrically connected performance between wiring layer and pad again to improve, from And improve the stability and reliability of encapsulating structure.

In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing to the present invention Specific embodiment be described in detail.When describing the embodiments of the present invention, for purposes of illustration only, schematic diagram can disobey general ratio Example makees partial enlargement, and the schematic diagram is example, should not be limited the scope of the invention herein.In addition, in reality It should include the three-dimensional space of length, width and depth in the production of border.

Fig. 1-Figure 19 is the structural schematic diagram of the forming process of encapsulating structure of the embodiment of the present invention.

With reference to Fig. 1-6, several semiconductor chips 160 (with reference to Fig. 6) are provided, each semiconductor chip 160 includes functional surfaces 11 and the non-functional surface 12 opposite with functional surfaces 11, there is several pads 101,101 surface of pad on the functional surfaces 11 On be formed with metal coupling 102, also there is the first plastic packaging layer 103, the first plastic packaging layer 103 covers institute on the functional surfaces 11 State metal coupling 102.

The semiconductor chip 160 has functional surfaces 11 and the non-functional surface 12 opposite with functional surfaces 11, the functional surfaces For the one side for being formed with integrated circuit and pad, the integrated circuit is formed in the semiconductor chip 160, several pads 101 are formed on the functional surfaces of the semiconductor chip 160, the pad 101 and the integrated circuit electricity in semiconductor chip 160 Connection, port of the pad 101 as integrated circuit and external electrical connections in semiconductor chip 160.In one embodiment, Integrated circuit in the semiconductor chip 160 may include several semiconductor devices (such as transistor, memory, sensor, Diode and/or triode etc.) and by semiconductor devices connect interconnection structure (including metal connecting line and metal plug).It needs It is noted that surrounded surface is semiconductor chip between the functional surfaces 11 and non-functional surface 12 of the semiconductor chip 160 160 side wall.

The semiconductor chip 160 is formed by semiconductor integration making technology, the tool that the semiconductor chip 160 is formed Body process is described in detail below with reference to Fig. 1-6.

Firstly, please referring to Fig. 1 and Fig. 2, Fig. 2 is Fig. 1 along the schematic diagram of the section structure in the direction cutting line AB, provides wafer 100, the chip area and the Cutting Road region between chip area that the wafer 100 includes several ranks arrangement；Institute Several chip areas for stating wafer 100 are correspondingly formed several semiconductor chips 160；In the functional surfaces of the semiconductor chip 160 It is upper to form several pads 101.

In one embodiment, the material of the wafer 100 can be monocrystalline silicon (Si), monocrystalline germanium (Ge) or SiGe (GeSi), silicon carbide (SiC)；It is also possible to silicon-on-insulator (SOI), germanium on insulator (GOI)；It or can also be others III-V compounds of group such as material, such as GaAs.The material of the pad 101 can be in aluminium, nickel, tin, tungsten, platinum, copper, titanium One kind.

It is the enlarged structure schematic diagram for forming metal coupling in Fig. 3 on a pad with reference to Fig. 3 and Fig. 4, Fig. 4, described Metal coupling 102 is formed on 101 surface of pad.

The metal coupling 102 protrudes from the surface of pad 101 and functional surfaces, and in one embodiment, the metal is convex One or more of the materials of aluminum of block 102, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold, silver form the mesh of metal coupling 102 Be pad 101 is drawn into height, be convenient for subsequent wiring, and the metal coupling 102 also has protection pad and heat transfer Effect.

In one embodiment, the process that the metal coupling 102 is formed includes: the function in the semiconductor chip 160 Insulating layer 150 is formed on face 11, and there is the first opening for exposing 101 part of the surface of pad in the insulating layer 150, it is described exhausted Edge layer 150 can be single-layer or multi-layer stacked structure, and the material of the insulating layer 150 can be silicon nitride, silica, resinous wood One or more of material；Convex lower metal layer is formed in the side wall and bottom surface of 150 surface of insulating layer and the first opening (UBM), the convex lower metal layer can be single-layer or multi-layer stacked structure；Being formed on the convex lower metal layer has second to open The mask layer of mouth, second opening at least expose the convex lower metal layer surface in the first opening；It is being told by electroplating technology Metal coupling 102 is formed in the opening of Sohu second；Remove the mask layer；The insulating layer of etching removal 102 two sides of metal coupling The convex lower metal layer on surface.

With reference to Fig. 5, the first plastic packaging layer 103, institute are formed on the surface of wafer 100 (functional surfaces of semiconductor chip 160) It states the first plastic packaging layer 103 and covers the metal coupling 102.

The first plastic packaging layer 103 covers top and the sidewall surfaces of the metal coupling 102, the first plastic packaging layer 103 have flat surface, and the formation process of the first plastic packaging layer 103 is to be molded or turn modeling technique, the first plastic packaging layer 103 material is resin, and the resin can be epoxy resin, polyimide resin, benzocyclobutane olefine resin, polybenzoxazoles Resin, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, gathers polybutylene terephthalate One of urethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol are several Kind.

Specifically, 100 bottom of wafer is fixed in mold, when be molded or turn modeling technique due to bottom Area it is larger, wafer will not move in the mold for being molded or turning modeling equipment so that the first plastic packaging layer 103 formed have it is flat Smooth surface, after being cut wafer, several discrete semiconductor chips 160 of formation all have flat surface, and And the thickness of several semiconductor chips 160 is able to maintain unanimously, it is subsequent to be moulded by first on several discrete semiconductor chips 160 When sealing 103 and support plate are bonded, since the first plastic packaging layer 103 has flat surface, so that each semiconductor chip Higher adhesion strength is all had between 160 and support plate, so that subsequent formed on support plate coats the of several semiconductor chips 160 When two plastic packaging layers, when being molded or turning the compression shock of modeling, all semiconductor chips 160 all will not position on support plate Offset is generated, thus it is subsequent after removing support plate, preformed cover plate is formed, is formed at the back side of preformed cover plate and is connect again with pad When wiring layer, then wiring layer will not generate offset with the link position of corresponding pad, to improve wiring layer again and pad Between be electrically connected performance, to improve the stability and reliability of encapsulating structure.

In addition, the first plastic packaging layer 103 of the formation is also used to fix the metal coupling 102, prevent subsequent flat again When changing the first plastic packaging layer and the second plastic packaging layer, prevent metal coupling 102 generated by lateral abrasive power loosening or It falls off from pad 101.

First plastic packaging layer 103 of the formation can be also used for protecting the metal coupling 102, prevent metal coupling 102 It is contaminated or damages in the subsequent process.

In one embodiment, the size of material granule is less than the second plastic packaging being subsequently formed in the first plastic packaging layer 103 The size of material granule in layer enables the first plastic packaging layer 103 more preferably to fill between metal coupling 102 with the gap of two sides, makes The first plastic packaging layer 103 and the contact of the side of metal coupling 102 more closely so that 103 pairs of metal of the first plastic packaging layer The fixed effect of convex block 102 is more preferable, subsequent to planarize the first plastic packaging layer and the second plastic packaging layer using chemical mechanical milling tech When top surface to expose metal coupling 102, it can preferably prevent metal coupling 102 from generating and loosen or from pad 101 On fall off, and can prevent to metal coupling 102 cross grind.

With reference to Fig. 6, the wafer 100 (referring to Fig. 5) is cut along Cutting Road region, formation is several discrete to mould with first The semiconductor chip 160 of sealing 103.

In other embodiments, referring to FIG. 7, after forming metal coupling 102, before forming the first plastic packaging layer 103, Isolation sacrificial layer 120 is formed in the top surface of the metal coupling 102 or top and sidewall surfaces；Isolation is formed to sacrifice After layer 120, the first plastic packaging layer 103 of the covering isolation sacrificial layer 120 and the semiconductor chip 160 is formed.

The study found that if the first plastic packaging layer 103 formed directly covers the surface of metal coupling 102, it is subsequent to be formed After coating the non-functional surface of the semiconductor chip and the second plastic packaging layer of sidewall surfaces and removing the support plate, need by flat Smoothization (chemical mechanical milling tech) removes part the first plastic packaging layer and the second plastic packaging layer to expose metal coupling 102 Top surface, during planarization (chemical mechanical milling tech), abrasive power is likely to generate part metals convex block 102 It loosens or falls off from pad 101.Thus in the present embodiment, before forming the first plastic packaging layer 103, in the metal coupling 102 top surface or top and sidewall surfaces are formed with isolation sacrificial layer 120, subsequent to pass through chemical mechanical grinding work Technique removal the first plastic packaging of the part layer 103 and the second plastic packaging layer that both skill and etching combine are to expose metal coupling, tool Body, first using chemical mechanical milling tech removal part the first plastic packaging layer and the second plastic packaging layer, exposes isolation and sacrifice It is convex to expose metal then using the isolation sacrificial layer on etching technics removal 102 top surface of metal coupling for layer surface The top surface of block can not only expose the top surface of metal coupling, and due to being removed using chemical mechanical milling tech When part the first plastic packaging layer and the second plastic packaging layer, exposure is isolation sacrificial layer surface, and the grinding pad in milling apparatus is not It can be contacted with metal coupling, because without bringing abrasive power to metal coupling, to preferably prevent metal coupling 102 from generating pine It moves or falls off from pad 101, further increase connection position between the wiring layer again and corresponding metal coupling being subsequently formed The precision set, further improve again wiring layer and metal coupling 102 is electrically connected performance.

In addition, the formation isolation sacrificial layer 120 can also improve between the first plastic packaging layer 103 and metal coupling 102 Adhesion strength.

In one embodiment, the material of the isolation sacrificial layer 120 is silica, silicon nitride or silicon oxynitride.

With reference to Fig. 8, the wafer 100 (referring to Fig. 7) is cut along Cutting Road region, several discrete having of formation are isolated sacrificial The semiconductor chip 160 of domestic animal layer 120 and the first plastic packaging layer 103.

With reference to Fig. 9 or Figure 11, support plate 107 is provided；By the first plastic packaging on the functional surfaces of several semiconductor chips 160 Layer 103 is bonded on support plate 107.

Offer support platform of the support plate 107 as subsequent technique, the support plate 107 can carry for glass support plate, silicon The support plate of plate or metal support plate, the support plate 107 or other suitable materials.

The first plastic packaging layer 103 on the semiconductor chip 160 is bonded in the surface of support plate 107, institute by an adhesive layer State the adhesive surface of functional surfaces (or pad 101) towards support plate 107 of semiconductor chip 160.

There are many available materials of adhesive layer, and in one embodiment, adhesive layer uses UV glue.UV glue is a kind of energy To the aitiogenic glueing material of the ultraviolet light of special wavelength.UV glue can be divided into according to variation sticky after ultraviolet light Two kinds, one is UV solidification glue, i.e. photoinitiator in material or photosensitizer produces after absorbing ultraviolet light under ultraviolet irradiation Liveliness proof free radical or cation cause monomer polymerization, are crosslinked and connect branch chemical reaction, make ultraviolet cured adhesive within the several seconds Solid-state is converted by liquid, so that the body surface being in contact with it be bonded；Another UV glue without ultraviolet light when irradiating Viscosity is very high, and the crosslinking chemical bond after ultraviolet light in material is interrupted viscosity is caused to decline to a great extent or disappear.This In adhesive layer used by UV glue be the latter.It can be formed by film coating process, print adhesive process or plastic roll technique described viscous Close layer.

In other embodiments, the adhesion-layer materials can also for epoxide-resin glue, polyimides glue, polyethylene glue, Benzocyclobutene glue or polybenzoxazoles glue.

Several semiconductor chips 160 are uniformly bonded on support plate 107 in ranks arrangement.

With reference to Figure 10 or Figure 11, non-functional surface and the side for coating the semiconductor chip 160 are formed on the support plate 107 Second plastic packaging layer 109 of wall surface.

The second plastic packaging layer 109 is for sealing and fixing the semiconductor chip 160, to be subsequently formed preformed cover Plate.The second plastic packaging layer 109 also covers 103 sidewall surfaces of 107 surface of support plate and the first plastic packaging layer.

The material of the second plastic packaging layer 109 can be epoxy resin, polyimide resin, benzocyclobutane olefine resin, gather Benzoxazoles resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, In polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol It is one or more of.

Forming the second plastic packaging layer 109 can be using Shooting Technique (injection molding) or turn modeling technique (transfer molding) or other suitable techniques.

When forming the second plastic packaging layer 109, the presence of the first plastic packaging layer 103, so that each 160 surface of semiconductor chip Flat surface is all had, is bonded by the first plastic packaging layer 103 on several discrete semiconductor chips 160 with support plate When, due to the first plastic packaging layer 103 have flat surface so that all had between each semiconductor chip 160 and support plate compared with High adhesion strength, to infused when forming the second plastic packaging layer 109 for coating several semiconductor chips 160 on support plate 107 Modeling or turn modeling compression shock when, all semiconductor chips 160 position on support plate will not all generate offset, thus it is subsequent After removing support plate 107, preformed cover plate is formed, when the back side of preformed cover plate forms the wiring layer again connecting with pad, then is routed Layer will not generate offset with the link position of corresponding pad, to improve the being electrically connected property between wiring layer and pad again Can, to improve the stability and reliability of encapsulating structure.

It is carried out on the basis of Figure 10 with reference to Figure 12 or Figure 13, Figure 12, Figure 13 is carried out on the basis of Figure 11, described in removing Support plate 107 (refers to Figure 10 or Figure 11), forms preformed cover plate 21, and the first plastic packaging layer is exposed at 21 back side of preformed cover plate 103。

By removal adhesive layers such as chemical attack, mechanical stripping, CMP, mechanical lapping, heat bakings, so that 107 quilt of support plate Removing.

Figure 15 and Figure 16 is referred to reference to Figure 14 or combination, Figure 14 is carried out on the basis of Figure 12, base of the Figure 15 in Figure 14 It is carried out on plinth, Figure 16 is carried out on the basis of Figure 15, removes part the first plastic packaging layer 103 at 21 back side of preformed cover plate With the second plastic packaging layer 109, the top surface of the metal coupling 102 is exposed.

In one embodiment, it when not formed isolation sacrificial layer, is directly removed by chemical mechanical milling tech described pre- The part at 21 back side of cover version the first plastic packaging layer 103 and the second plastic packaging layer 109, expose the metal coupling 102.

In another embodiment, when forming isolation sacrificial layer 120, with reference to Figure 15, chemical mechanical milling tech is first used Part the first plastic packaging layer 103 and the second plastic packaging layer 109 are removed, isolation 120 surface of sacrificial layer is exposed；With reference to Figure 16, adopt With the isolation sacrificial layer 120 (referring to Figure 15) on etching technics removal 102 top surface of metal coupling, it is convex to expose metal The top surface of block 102, specifically, the position of the removal isolation sacrificial layer 120 is correspondingly formed in the first plastic packaging layer 103 Opening 121, the top surface that the opening 121 exposes the metal coupling 102.It is sacrificial by forming isolation in the present embodiment Domestic animal layer 120, can first using chemical mechanical milling tech removal part the first plastic packaging layer and the second plastic packaging layer, expose every From sacrificial layer surface, then using the isolation sacrificial layer on etching technics removal 102 top surface of metal coupling, expose The top surface of metal coupling 102, thus gold can not only be exposed by the combination of aforementioned specific structure and specific technique Belong to the top surface of convex block, and due to using chemical mechanical milling tech removal part the first plastic packaging layer and the second plastic packaging When layer, exposure is isolation sacrificial layer surface, and the grinding pad in milling apparatus will not be contacted with metal coupling, because without to gold Belong to convex block and bring abrasive power, loosens or fall off from pad 101 to preferably prevent metal coupling 102 from generating, further The precision for improving link position between the wiring layer again and corresponding metal coupling being subsequently formed, further improves wiring layer again Performance is electrically connected with metal coupling 102.

The etching technics for removing the isolation sacrificial layer 120 is wet etching or dry etching.In one embodiment, work as institute When the material for stating isolation sacrificial layer 120 is silicon nitride, the isolation sacrificial layer 120 is removed using wet etching, wet etching is adopted Etching solution is phosphoric acid solution.

With reference to Figure 17 and Figure 18, the external contact connecting with metal coupling 102 is formed at the back side of the preformed cover plate 21 Structure.

The external contact structure includes being routed again of being connect on 21 back side of preformed cover plate with metal coupling 102 Layer 110 and the external contacts 112 being connect on wiring layer 110 again with wiring layer 110 again, each semiconductor chip Metal coupling 102 on 160 is connected with corresponding external contact structure.The external contacts 112 are soldered ball or described External contacts 112 also may include metal column and the soldered ball positioned at metal column surface.

In a specific embodiment, the forming process of the wiring layer again 110 and external contacts 112 includes: to shell After the support plate, wiring layer 110 again are formed on the back side of the preformed cover plate 21；In wiring layer 110 again and preformed cover version Insulating layer 111 is formed on 21 back side, forms the opening for exposing again 110 part of the surface of wiring layer, institute in the insulating layer 111 Stating 121 material of insulating layer can be with silicon nitride, Pyrex, phosphorosilicate glass or boron-phosphorosilicate glass；It is formed in said opening external Contact 112.

With reference to Figure 19, after forming the external contact structure, further includes: cut the preformed cover plate, form several points Vertical encapsulating structure 22.

It should be noted that it is outer to form formation in the process and Figure 17-Figure 18 of external contact structure on the basis of Figure 16 The process of portion's contact structures is essentially identical, and details are not described herein.

One embodiment of the invention additionally provides a kind of encapsulating structure, please refers to Figure 10 or Figure 11, comprising:

Support plate 107；

Several semiconductor chips 160 being bonded on the support plate 107, each semiconductor chip 160 include functional surfaces 11 The non-functional surface 12 opposite with functional surfaces 11, has several pads 101 on the functional surfaces 11, on 101 surface of pad It is formed with metal coupling 102, also there is the first plastic packaging layer 103 on the functional surfaces 11, the first plastic packaging layer 103 covers described Metal coupling 102, the first plastic packaging layer 103 on the functional surfaces of the semiconductor chip 160 are bonded on support plate 107；

The non-functional surface of the semiconductor chip 160 and the second plastic packaging of sidewall surfaces are coated on the support plate 107 Layer 109.

In one embodiment, the semiconductor chip 160 is formed by integration making technology, comprising steps of providing brilliant It is round, several semiconductor chips are formed on the wafer, the semiconductor chip includes functional surfaces, has weldering on the functional surfaces Disk；Metal coupling is formed on the pad；Form the first plastic packaging layer for covering the metal coupling and functional surfaces；Described in formation After first plastic packaging layer, the wafer is cut, forms several discrete semiconductor chips.

In one embodiment, the material of the first plastic packaging layer 103 and the second plastic packaging layer 109 is resin, first modeling The formation process of sealing and the second plastic packaging layer is to be molded or turn modeling technique.

In one embodiment, in the first plastic packaging layer 103 size of material granule less than material in the second plastic packaging layer 109 The size of particle.

In one embodiment, Figure 11, the top surface of the metal coupling 102 or top and sidewall surfaces shape are please referred to At there is isolation sacrificial layer 120, the first plastic packaging layer 103 also covers the isolation sacrificial layer 120.

The material of the isolation sacrificial layer 120 is silica, silicon nitride or silicon oxynitride.

It should be noted that please referring to aforementioned encapsulation knot about other restrictions or description of encapsulating structure in the present embodiment The corresponding restriction or description of the forming process part of structure, are not repeating in the present embodiment.

The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as Protection scope of the present invention.