阅读说明：本技术 一种基于cnfet的三值sram-puf电路 (A kind of three value SRAM-PUF circuits based on CNFET ) 是由 张麟 张跃军 于 2019-07-18 设计创作，主要内容包括：本发明公开了一种基于CNFET的三值SRAM-PUF电路,包括4个D触发器、4-16译码器、16个读字行驱动器和16个三值PUF数据生成及输出模块,4-16译码器用于将其4位输入端接入的4位二进制数据转换为16位二进制数据在其16位输出端输出,每个读字行驱动器分别用于输出读使能信号,每个三值PUF数据生成及输出模块分别在一个读字行驱动器的控制下生成响应数据并输出；优点是在保证随机性的基础上,输出响应速度快,电路开销小。(The invention discloses a kind of three value SRAM-PUF circuits based on CNFET, including 4 d type flip flops, 4-16 decoder, 16 reading word line drivers and 16 three value PUF data generate and output module, 4-16 decoder is used to be converted to 4 bit binary datas that its 4 input terminals access 16 bit binary datas in its 16 output end outputs, each reading word line driver is respectively used to output and reads enable signal, and response data is generated under the control that each three values PUF data generate and output module reads word line driver at one respectively and is exported；Advantage is on the basis of guaranteeing randomness, and output response speed is fast, and circuit overhead is small.)

1. a kind of three value SRAM-PUF circuits based on CNFET, it is characterised in that including 4 d type flip flops, 4-16 decoder, 16 A reading word line driver and 16 three value PUF data generations and output module, each d type flip flop are respectively provided with clock End, input terminal and output end, the 4-16 decoder have 4 input terminals and 16 output ends, the 4-16 decoder 4 bit binary datas for accessing its 4 input terminals are converted to 16 bit binary datas in its 16 output end outputs, often A reading word line driver is respectively provided with input terminal, the reading control terminal for exporting read control signal, reads control for exporting The reverse phase of the inversion signal of signal processed reads control terminal and for exporting the output end for reading enable signal, each three value PUF Data generate and output module be respectively provided with clock end, input terminal, read control terminal, reverse phase reads control terminal, the first output end and the D type flip flop described in 4 is referred to as the first d type flip flop, the second d type flip flop, third d type flip flop and the 4th D by two output ends Trigger, the clock end of first d type flip flop, the clock end of second d type flip flop, the third d type flip flop Clock end, three value PUF data described in the clock end of the four d flip-flop and 16 generate and the clock of output module End connection and its connecting pin are the clock end of the three value SRAM-PUF circuits, are used for incoming clock signal；First D The output end of trigger is connected with the 1st input terminal in 4 input terminals of the 4-16 decoder, the 2nd D touching The output end of hair device is connected with the 2nd input terminal in 4 input terminals of the 4-16 decoder, the 3rd D triggering The output end of device is connected with the 3rd input terminal in 4 input terminals of the 4-16 decoder, the four d flip-flop Output end connected with the 4th input terminal in 4 input terminals of the 4-16 decoder, the 16 of the 4-16 decoder Jth position output end in the output end of position is connect with the input terminal for reading word line driver described in j-th, j=1, and 2 ..., 16；Jth Three value PUF data described in the readings control terminal of a reading word line driver and j-th generate and the reading of output module controls End connection, the reverse phase that word line driver is read described in j-th are read three value PUF data described in control terminal and j-th and are generated and defeated Out module reverse phase read control terminal connection, described in j-th read word line driver output end and j-th described in three value PUF Data generate and the connection of the input terminal of output module.

2. a kind of three value SRAM-PUF circuits based on CNFET according to claim 1, it is characterised in that described in each Three value PUF data generate and output module respectively includes three value SRAM-PUF units, the first phase inverter, the second phase inverter, third Phase inverter, the 4th phase inverter, the 5th phase inverter, hex inverter, the first NMOS tube, the second NMOS tube, the 5th d type flip flop and Six d type flip flops, the three value SRAM-PUF units have input terminal, inverting input terminal and output end, the 5th D triggering Device and the 6th d type flip flop are respectively provided with clock end, input terminal and output end, the three value SRAM-PUF units it is defeated Enter the reading control terminal that end is the generation of three value PUF data and output module, the reverse phase of the three value SRAM-PUF units Input terminal is that the three value PUF data generate and the reverse phase of output module reads control terminal, the three value SRAM-PUF units Output end, first phase inverter input terminal connected with the input terminal of second phase inverter, described first is anti- The output end of phase device is connected with the drain electrode of first NMOS tube, the output end of second phase inverter and described second The drain electrode of NMOS tube connects, and the source electrode of first NMOS tube is connected with the input terminal of the third phase inverter, described The output end of third phase inverter is connected with the input terminal of the 5th phase inverter, the output end of the 5th phase inverter and institute The input terminal for the 5th d type flip flop stated connects, the input terminal of the source electrode of second NMOS tube and the 4th phase inverter Connection, the output end of the 4th phase inverter are connected with the input terminal of the hex inverter, the hex inverter Output end connected with the input terminal of the 6th d type flip flop, the output end of the 5th d type flip flop is three values PUF data generate and the first output end of output module, and the output end of the 6th d type flip flop is the three value PUF numbers According to generation and the second output terminal of output module, the grid of the grid of first NMOS tube and second NMOS tube connects It connects and its connecting pin is the input terminal of the generation of three value PUF data and output module, the clock of the 5th d type flip flop End is connected with the clock end of the 6th d type flip flop and its connecting pin is the generation of three value PUF data and output module Clock end.

3. a kind of three value SRAM-PUF circuits based on CNFET according to claim 2, it is characterised in that three values SRAM-PUF unit is managed including the first CNFET pipe, the 2nd CNFET pipe, the 3rd CNFET pipe, the 4th CNFET, the 5th CNFET is managed, 6th CNFET pipe, the 7th CNFET pipe, the 8th CNFET pipe, the 9th CNFET pipe and the tenth CNFET pipe；First CNFET Pipe, the 3rd CNFET pipe, the 5th CNFET pipe, the 8th CNFET pipe and the 9th CNFET pipe are equal For p-type CNFET pipe, the 2nd CNFET pipe, the 4th CNFET pipe, the 6th CNFET pipe, the described the 7th CNFET pipe and the tenth CNFET pipe are N-type CNFET pipe；The source electrode of the first CNFET pipe, the third The source electrode of the source electrode of CNFET pipe and the 5th CNFET pipe accesses the first supply voltage, the leakage of the 7th CNFET pipe Second source voltage is accessed in pole, and the second source voltage is the half of first supply voltage；Described first The grid of CNFET pipe, the grid of the 2nd CNFET pipe, the grid of the 3rd CNFET pipe, the 4th CNFET The grid of pipe, the drain electrode of the 5th CNFET pipe, the drain electrode of the 6th CNFET pipe, the 8th CNFET pipe Drain electrode, the drain electrode of the 9th CNFET pipe are connected with the drain electrode of the tenth CNFET pipe, the first CNFET pipe Drain electrode, the drain electrode of the 2nd CNFET pipe, the grid of the 6th CNFET pipe and the grid of the 8th CNFET pipe Connection, the source electrode ground connection of the 2nd CNFET pipe, the drain electrode of the 3rd CNFET pipe, the 4th CNFET pipe Drain electrode, the 5th CNFET pipe grid connected with the grid of the 7th CNFET pipe, the 4th CNFET pipe Source electrode ground connection, the source electrode ground connection of the 6th CNFET pipe, the source electrode and the 8th CNFET of the 7th CNFET pipe The source electrode of pipe connects, and the source electrode of the 9th CNFET pipe is connected with the source electrode of the tenth CNFET pipe and its connecting pin is The output end of the three value SRAM-PUF units, the grid of the 9th CNFET pipe are that the three value SRAM-PUF are mono- The inverting input terminal of member, the grid of the tenth CNFET pipe are the input terminal of the three value SRAM-PUF units；

The chiral vector of the first CNFET pipe is (11,0), and the chiral vector of the 2nd CNFET pipe is (16,0), The chiral vector of the 3rd CNFET pipe is (19,0), and the chiral vector of the 4th CNFET pipe is (10,0), described The chiral vector of the 5th CNFET pipe be (13,0), the chiral vector of the 6th CNFET pipe is (13,0), described the The chiral vector of seven CNFET pipes is (19,0), and the chiral vector of the 8th CNFET pipe is (19,0), the described the 9th The chiral vector of CNFET pipe is (10,0), and the chiral vector of the tenth CNFET pipe is (10,0).

4. a kind of three value SRAM-PUF circuits based on CNFET according to claim 2, it is characterised in that described first D type flip flop include the first PMOS tube, the second PMOS tube, third PMOS tube, the 4th PMOS tube, the 5th PMOS tube, the 6th PMOS tube, Third NMOS tube, the 4th NMOS tube, the 5th NMOS tube, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube, the 7th phase inverter, 8th phase inverter, the 9th phase inverter, the tenth phase inverter, the 11st phase inverter and the 12nd phase inverter；First PMOS tube Source electrode and the third PMOS tube source electrode access the first supply voltage, first PMOS tube drain electrode and it is described The source electrode of second PMOS tube connects, the grid of first PMOS tube, the grid of the 6th PMOS tube, the described the 5th The grid of NMOS tube, the 7th NMOS tube grid connected with the output end of the 8th phase inverter, described second The grid of PMOS tube is connected with the grid of the third NMOS tube and connecting pin is the input terminal of first d type flip flop, The drain electrode of second PMOS tube, the drain electrode of the third NMOS tube, the drain electrode of the 4th PMOS tube, described The drain electrode of five NMOS tubes is connected with the input terminal of the 9th phase inverter, the drain electrode of the third PMOS tube and described the The source electrode of four PMOS tube connects, and the grid of the third PMOS tube, the grid of the 6th NMOS tube, the described the 9th are instead The drain electrode of the output end of phase device, the 5th PMOS tube is connected with the drain electrode of the 7th NMOS tube, and the described the 4th The grid of PMOS tube, the grid of the 4th NMOS tube, the grid of the 5th PMOS tube, the 8th NMOS tube Grid, the 7th phase inverter output end connected with the input terminal of the 8th phase inverter, the 5th PMOS tube Source electrode, the source electrode of the 7th NMOS tube, the drain electrode of the 6th PMOS tube, the drain electrode of the 8th NMOS tube and The input terminal of tenth phase inverter connects, the source electrode of the 6th PMOS tube, the source electrode of the 8th NMOS tube and The output end of 11st phase inverter connects, the drain electrode of the source electrode of the third NMOS tube and the 4th NMOS tube Connection, the source electrode ground connection of the 4th NMOS tube, the source electrode of the 5th NMOS tube and the leakage of the 6th NMOS tube Pole connection, the source electrode ground connection of the 6th NMOS tube, the input terminal of the 7th phase inverter is first d type flip flop Clock end, the output end of the tenth phase inverter, the input terminal of the 11st phase inverter and the described the 12nd are anti- The input terminal of phase device connects, and the output end of the 12nd phase inverter is the output end of first d type flip flop；Described Second d type flip flop, the third d type flip flop, the four d flip-flop, the 5th d type flip flop and the described the 6th The structure of d type flip flop is identical as the structure of the first d type flip flop.

5. a kind of three value SRAM-PUF circuits based on CNFET according to claim 1, it is characterised in that described in each It reads word line driver and respectively includes the 9th NMOS tube, the 13rd phase inverter, the 14th phase inverter, the 15th phase inverter, the 16th Phase inverter, the 17th phase inverter, eighteen incompatibilities phase device, the 19th phase inverter and the 20th phase inverter；9th NMOS tube Drain electrode access the first supply voltage, the source electrode of the 9th NMOS tube connects with the input terminal of the 13rd phase inverter And its connecting pin is the input terminal of the reading word line driver, the grid of the 9th NMOS tube, the described the 14th are instead The output end of phase device is connected with the input terminal of the 15th phase inverter, the output end of the 13rd phase inverter and described The 14th phase inverter input terminal connection, the output end of the 15th phase inverter, the tenth hex inverter it is defeated Enter that end connect with the input terminal of the 17th phase inverter and its connecting pin is the described control terminal for reading word line driver, institute The output end for the tenth hex inverter stated is the inverted control terminals of the reading word line driver, the 17th phase inverter Output end is connected with the input terminal of the eighteen incompatibilities phase device, the output end and the described the tenth of the eighteen incompatibilities phase device The input terminal of nine phase inverters connects, and the output end of the 19th phase inverter and the input terminal of the 20th phase inverter connect It connects, the output end of the 20th phase inverter is the output end of the reading word line driver.

Technical field

The present invention relates to a kind of three value SRAM-PUF circuits, more particularly, to a kind of three value SRAM-PUF based on CNFET Circuit.

Background technique

Physics unclonable function (Physical Unclonable Functions, PUF) circuit is chip field " DNA (Deoxyribonucleic acid, DNA) feature identification technique " has uniqueness, randomness and can not It is Clonal.The above-mentioned characteristic of PUF circuit allows to for defensive attack.In multi-level security mechanism, PUF circuit is used for The key generation of public key encryption system, secrete key of smart card identifying system, radio frequency identification (Radio Frequency IDentification, RFID) system and digital intellectual property protection etc..Meanwhile the PUF circuit of high robust can be effective It completes authentication and key generates, realize the normal work of PUF circuit under various circumstances.PUF circuit is also information security The important supplement of field hardware identification technology, it is ensured that the health of safety chip uses.

A kind of existing three value PUF element circuit of delaying type is mainly by input module, delay chain, decision device and output module This four part composition.The three value PUF element circuit structure of delaying type is complex, and element used is more, therefore expense is larger. In terms of circuit performance, which needs to generate three-valued inverter by delay chain random inclined Difference amplification, therefore the quantity of its randomness and the delay cell for constituting delay chain is closely related, delay cell quantity is more, with Machine is better, but with the increase of delay Board Lot, the speed for generating the response of three value random outputs is also slower, accordingly Its expense can also increase with it.

Summary of the invention

Technical problem to be solved by the invention is to provide one kind on the basis of guaranteeing randomness, output response speed Fastly, the small three value SRAM-PUF circuits based on CNFET of circuit overhead.

The technical scheme of the invention to solve the technical problem is: a kind of three value SRAM-PUF based on CNFET Circuit, including 4 d type flip flops, 4-16 decoder, 16 reading word line drivers and 16 three value PUF data generate and output mould Block, each d type flip flop are respectively provided with clock end, input terminal and output end, and the 4-16 decoder has 4 inputs End and 16 output ends, the 4-16 decoder are used to 4 bit binary datas that its 4 input terminals access being converted to 16 Binary data is respectively provided with input terminal, reads for exporting in its 16 output end outputs, each reading word line driver Control the readings control terminal of signal, the reverse phase of inversion signal for exporting read control signal reads control terminal and reads to enable for exporting The output end of signal, each three value PUF data generate and output module is respectively provided with clock end, input terminal, reads control End, reverse phase read control terminal, the first output end and second output terminal, by d type flip flop described in 4 be referred to as the first d type flip flop, Second d type flip flop, third d type flip flop and four d flip-flop, the clock end of first d type flip flop, the 2nd D touching Described in the hair clock end of device, the clock end of the third d type flip flop, the clock end of the four d flip-flop and 16 Three value PUF data generate and the clock end of output module connects and its connecting pin is the clock of the three value SRAM-PUF circuits End is used for incoming clock signal；In 4 input terminals of the output end of first d type flip flop and the 4-16 decoder The connection of the 1st input terminal, in 4 input terminals of the output end of second d type flip flop and the 4-16 decoder The 3rd in 4 input terminals of the 2nd input terminal connection, the output end of the third d type flip flop and the 4-16 decoder The 4th in 4 input terminals of position input terminal connection, the output end of the four d flip-flop and the 4-16 decoder Input terminal connection, jth position output end and the driving of reading word row described in j-th in 16 output ends of the 4-16 decoder The input terminal of device connects, j=1, and 2 ..., 16；Described in j-th read word line driver reading control terminal and j-th described in three Value PUF data generate and output module reading control terminal connection, described in j-th read word line driver reverse phase read control terminal and Three value PUF data described in j-th generate and the reverse phase of output module reads control terminal connection, the driving of reading word row described in j-th Three value PUF data described in the output end of device and j-th generate and the connection of the input terminal of output module.

Each three value PUF data generate and output module respectively includes three value SRAM-PUF units, the first reverse phase Device, the second phase inverter, third phase inverter, the 4th phase inverter, the 5th phase inverter, hex inverter, the first NMOS tube, the 2nd NMOS Pipe, the 5th d type flip flop and the 6th d type flip flop, the three value SRAM-PUF units have input terminal, inverting input terminal and output End, the 5th d type flip flop and the 6th d type flip flop are respectively provided with clock end, input terminal and output end, and described three The input terminal of value SRAM-PUF unit is the reading control terminal of the generation of three value PUF data and output module, three values The inverting input terminal of SRAM-PUF unit is that the three value PUF data generate and the reverse phase of output module reads control terminal, described The output end of three value SRAM-PUF units, the input terminal of first phase inverter and second phase inverter input terminal Connection, the output end of first phase inverter are connected with the drain electrode of first NMOS tube, second phase inverter Output end is connected with the drain electrode of second NMOS tube, the source electrode of first NMOS tube and the third phase inverter Input terminal connection, the output end of the third phase inverter are connected with the input terminal of the 5th phase inverter, and the described the 5th The output end of phase inverter is connected with the input terminal of the 5th d type flip flop, the source electrode of second NMOS tube and described The input terminal of 4th phase inverter connects, and the output end of the 4th phase inverter and the input terminal of the hex inverter connect It connects, the output end of the hex inverter is connected with the input terminal of the 6th d type flip flop, the 5th d type flip flop Output end be that the three value PUF data generate and the first output end of output module, the output of the 6th d type flip flop End is that the three value PUF data generate and the second output terminal of output module, the grid of first NMOS tube and described The second NMOS tube grid connection and its connecting pin be that the three value PUF data generate and the input terminal of output module, institute The clock end for the 5th d type flip flop stated is connected with the clock end of the 6th d type flip flop and its connecting pin is three values PUF data generate and the clock end of output module.In the circuit, it is defeated at random that three values are generated by three value SRAM-PUF element circuits It responds, then output signal is handled out by phase inverter and d type flip flop, exciter response in three value PUF data that treated Pair information content be 1.58 times of two-value PUF data, improve the complexity and safety of key, while chip is effectively reduced Area.

The three value SRAM-PUF units include the first CNFET pipe, the 2nd CNFET pipe, the 3rd CNFET pipe, the 4th CNFET pipe, the 5th CNFET pipe, the 6th CNFET pipe, the 7th CNFET pipe, the 8th CNFET pipe, the 9th CNFET pipe and the tenth CNFET pipe；First CNFET is managed, the 3rd CNFET pipe, the 5th CNFET are managed, the 8th CNFET Pipe and the 9th CNFET pipe are p-type CNFET pipe, and the 2nd CNFET pipe, the 4th CNFET are managed, are described The 6th CNFET pipe, described 7th CNFET pipe and the tenth CNFET pipe be N-type CNFET pipe；Described first The source electrode of the source electrode of CNFET pipe, the source electrode of the 3rd CNFET pipe and the 5th CNFET pipe accesses the first power supply electricity Pressure, the drain electrode of the 7th CNFET pipe access second source voltage, and the second source voltage is first power supply The half of voltage；The grid of the first CNFET pipe, the grid of the 2nd CNFET pipe, the 3rd CNFET pipe Grid, the grid of the 4th CNFET pipe, the drain electrode of the 5th CNFET pipe, the leakage of the 6th CNFET pipe Pole, the drain electrode of the 8th CNFET pipe, the drain electrode of the 9th CNFET pipe and the drain electrode of the tenth CNFET pipe connect Connect, the drain electrode of the first CNFET pipe, the drain electrode of the 2nd CNFET pipe, the 6th CNFET pipe grid and The grid of the 8th CNFET pipe connects, the source electrode ground connection of the 2nd CNFET pipe, the leakage of the 3rd CNFET pipe Pole, the drain electrode of the 4th CNFET pipe, the grid of the 5th CNFET pipe and the 7th CNFET pipe grid connect It connects, the source electrode ground connection of the 4th CNFET pipe, the source electrode ground connection of the 6th CNFET pipe, the 7th CNFET pipe Source electrode connected with the source electrode of the 8th CNFET pipe, the source electrode and the tenth CNFET of the 9th CNFET pipe The source electrode of pipe connects and its connecting pin is the output end of the three value SRAM-PUF units, the grid of the 9th CNFET pipe The extremely inverting input terminal of the three value SRAM-PUF units, the grid of the tenth CNFET pipe are three values The input terminal of SRAM-PUF unit；The chiral vector of the first CNFET pipe is (11,0), the 2nd CNFET pipe Chiral vector is (16,0), and the chiral vector of the 3rd CNFET pipe is (19,0), the chirality of the 4th CNFET pipe Vector is (10,0), and the chiral vector of the 5th CNFET pipe is (13,0), the chiral vector of the 6th CNFET pipe Chiral vector for (13,0), the 7th CNFET pipe is (19,0), and the chiral vector of the 8th CNFET pipe is (19,0), the chiral vector of the 9th CNFET pipe are (10,0), the chiral vector of the tenth CNFET pipe be (10, 0).In the circuit, three value SRAM-PUF element circuits can be with by cross-coupling three-valued inverter using three value buffer circuits Generate random current, available random and unclonable 0,1,2 three value output signal, using three value text computing circuits, Basic 0,1,2 ternary algebra operation is reduced to basic 0,1 binary algebra operation, then binary algebra operation is converted to three Value algebra operation finally obtains the random output response of three values, and circuit structure is simple, and contained component number is less, therefore The expense of circuit cost is less, and in terms of circuit performance, randomness directly depends on the threshold voltage and tubes pipe of each pipe It is relatively simple to adjust randomness compared to delaying type circuit for number, and after parameter is adjusted in place, and has preferable random Property, in terms of circuit operation speeds, since its circuit structure is simple, circuit operation speeds are exceedingly fast, with 100 Monte Carlo simulations For, existing delaying type PUF element circuit probably needs 8 hours or more, and circuit probably only needs 15 minutes, using this electricity The three value PUF circuits that road is realized, compared to traditional two-value PUF circuit, by realize PUF circuit output state diversity, Excitation-response pair complexity improves chip to improve the safety of PUF circuit, and its uniline message bearing capacity The utilization rate of room and time is advantageously implemented high information density safety chip.

First d type flip flop includes the first PMOS tube, the second PMOS tube, third PMOS tube, the 4th PMOS tube, the 5th PMOS tube, the 6th PMOS tube, third NMOS tube, the 4th NMOS tube, the 5th NMOS tube, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube, the 7th phase inverter, the 8th phase inverter, the 9th phase inverter, the tenth phase inverter, the 11st phase inverter and the 12nd reverse phase Device；The source electrode of first PMOS tube and the source electrode of the third PMOS tube the first supply voltage of access, described first The drain electrode of PMOS tube is connected with the source electrode of second PMOS tube, the grid of first PMOS tube, the described the 6th The grid of PMOS tube, the grid of the 5th NMOS tube, the 7th NMOS tube grid and the 8th phase inverter Output end connection, the grid of second PMOS tube is connected with the grid of the third NMOS tube and connecting pin is described The first d type flip flop input terminal, the drain electrode of second PMOS tube, the drain electrode of the third NMOS tube, described The drain electrode of four PMOS tube, the drain electrode of the 5th NMOS tube are connected with the input terminal of the 9th phase inverter, and described The drain electrode of three PMOS tube is connected with the source electrode of the 4th PMOS tube, the grid of the third PMOS tube, the described the 6th The grid of NMOS tube, the output end of the 9th phase inverter, the drain electrode of the 5th PMOS tube and the 7th NMOS The drain electrode of pipe connects, the grid of the 4th PMOS tube, the grid of the 4th NMOS tube, the 5th PMOS tube Grid, the grid of the 8th NMOS tube, the 7th phase inverter output end and the 8th phase inverter input End connection, the source electrode of the 5th PMOS tube, the source electrode of the 7th NMOS tube, the 6th PMOS tube drain electrode, The drain electrode of 8th NMOS tube is connected with the input terminal of the tenth phase inverter, the source electrode of the 6th PMOS tube, The source electrode of 8th NMOS tube is connected with the output end of the 11st phase inverter, the source electrode of the third NMOS tube It is connected with the drain electrode of the 4th NMOS tube, the source electrode ground connection of the 4th NMOS tube, the source of the 5th NMOS tube Pole is connected with the drain electrode of the 6th NMOS tube, the source electrode ground connection of the 6th NMOS tube, the 7th phase inverter Input terminal is the clock end of first d type flip flop, output end, the 11st phase inverter of the tenth phase inverter Input terminal connected with the input terminal of the 12nd phase inverter, the output end of the 12nd phase inverter is described the The output end of one d type flip flop；It is second d type flip flop, the third d type flip flop, the four d flip-flop, described The 5th d type flip flop and the 6th d type flip flop structure it is identical as the structure of the first d type flip flop.The circuit is logical It crosses metal-oxide-semiconductor and phase inverter is constituted, the fast response time when sampling PUF output data, and the signal generated can be applied directly In other digital display circuits.

The reading word line driver respectively includes the 9th NMOS tube, the 13rd phase inverter, the 14th phase inverter, the 15 phase inverters, the tenth hex inverter, the 17th phase inverter, eighteen incompatibilities phase device, the 19th phase inverter and the 20th phase inverter； The drain electrode of 9th NMOS tube accesses the first supply voltage, and the source electrode of the 9th NMOS tube and the described the 13rd is instead The input terminal of phase device connects and its connecting pin is the input terminal of the reading word line driver, the grid of the 9th NMOS tube Pole, the 14th phase inverter output end connected with the input terminal of the 15th phase inverter, the described the 13rd is anti- The output end of phase device is connected with the input terminal of the 14th phase inverter, the output end of the 15th phase inverter, described The tenth hex inverter input terminal connected with the input terminal of the 17th phase inverter and its connecting pin be the reading word The control terminal of line driver, the output end of the tenth hex inverter are the inverted control terminals of the reading word line driver, The output end of 17th phase inverter is connected with the input terminal of the eighteen incompatibilities phase device, the eighteen incompatibilities phase device Output end connected with the input terminal of the 19th phase inverter, the output end of the 19th phase inverter and described The input terminal of 20 phase inverters connects, and the output end of the 20th phase inverter is the output of the reading word line driver End.The reading word line driver is realized by the way of the phase inverter for increasing driving capability step by step, be can effectively improve and is read word row letter Number driving capability, increase the reliability of circuit.

Compared with the prior art, the advantages of the present invention are as follows driven by 4 d type flip flops, 4-16 decoder, 16 reading word rows Dynamic device and 16 three value PUF data generate and output module constitutes three value SRAM-PUF circuits, when each d type flip flop is respectively provided with Zhong Duan, input terminal and output end, 4-16 decoder have 4 input terminals and 16 output ends, and 4-16 decoder is used for its 4 4 bit binary datas of input terminal access are converted to 16 bit binary datas in its 16 output end outputs, and each reading word row drives Dynamic device is respectively provided with input terminal, the reading control terminal for exporting read control signal, the inversion signal for exporting read control signal Reverse phase read control terminal and for export the output end for reading enable signal, each three values PUF data are generated and output module is distinguished With clock end, input terminal, control terminal, reverse phase reading control terminal, the first output end and second output terminal are read, by 4 d type flip flops point It is also known as the first d type flip flop, the second d type flip flop, third d type flip flop and four d flip-flop, the clock end of the first d type flip flop, the The clock end of 2-D trigger, the clock end of third d type flip flop, the clock end of four d flip-flop and 16 three value PUF data are raw At and output module clock end connection and its connecting pin be three value SRAM-PUF circuits clock end, for incoming clock believe Number；The output end of first d type flip flop is connected with the 1st input terminal in 4 input terminals of 4-16 decoder, the second d type flip flop Output end connected with the 2nd input terminal in 4 input terminals of 4-16 decoder, the output end and 4-16 of third d type flip flop The 3rd input terminal connection in 4 input terminals of decoder, 4 inputs of the output end and 4-16 decoder of four d flip-flop The 4th input terminal in end connects, and the jth position output end and j-th of reading word row in 16 output ends of 4-16 decoder drive The input terminal of device connects, j=1, and 2 ..., 16；The reading control terminal and j-th of three value PUF data generations of j-th of reading word line driver And the reading control terminal connection of output module, the reverse phase of j-th of reading word line driver reads control terminal and j-th of three value PUF data are raw At and the reverse phase of output module read control terminal connection, the output end of j-th reading word line driver and j-th three value PUF data are raw At and output module input terminal connection, circuit structure is simple, and contained component number is less, therefore the expense of circuit cost It is less, in terms of circuit performance: randomness of the invention directly depend on 16 three value PUF data generate and output module it is interior It is relatively simple to adjust randomness compared to delaying type circuit for portion's circuit structure and parameter, and after parameter is adjusted in place, tool Standby preferable randomness, in terms of circuit operation speeds, since its circuit structure is simple, circuit operation speeds are exceedingly fast, with 100 times For Monte Carlo simulation, existing delaying type PUF circuit probably needs 8 hours or more, and circuit of the invention probably only needs 15 minutes, compared to traditional two-value PUF circuit, the present invention passed through the diversity for realizing PUF circuit output state, excitation-sound The complexity of reply, so that the safety of PUF circuit is improved, meanwhile, the present invention also increases the uniline message bearing capacity of circuit, The utilization rate for improving chip space and time is advantageously implemented high information density safety chip.

Detailed description of the invention

Fig. 1 is the structural block diagram of the three value SRAM-PUF circuits of the invention based on CNFET；

Fig. 2 is the generation of three value PUF data and the output module of the three value SRAM-PUF circuits of the invention based on CNFET Structural block diagram；

Fig. 3 is the circuit diagram of three value SRAM-PUF units of the three value SRAM-PUF circuits of the invention based on CNFET；

Fig. 4 is the circuit diagram of the first d type flip flop of the three value SRAM-PUF circuits of the invention based on CNFET；

Fig. 5 is the circuit diagram of the reading word line driver of the three value SRAM-PUF circuits of the invention based on CNFET；

Fig. 6 is that the illiteracy of three value SRAM-PUF element circuits of the three value SRAM-PUF circuits of the invention based on CNFET is special Carlow simulation waveform.

Specific embodiment

The present invention will be described in further detail below with reference to the embodiments of the drawings.