阅读说明：本技术 用于电控扫描天线的四路可调电源模块 (four-way adjustable power module for electric control scanning antenna ) 是由 蒋迪 李潇雨 于 2019-08-29 设计创作，主要内容包括：本发明公开了一种用于电控扫描天线的四路可调电源模块,所述FPGA芯片,用于向内部逻辑电路和PLL数字电路提供1.2V电压,向PLL模拟电路提供2.5V电压以及IO电压向每个电路提供3.3V电压；所述电源电路,用于将输入电压30V降压至5V,并将5V电压转换为供内部逻辑电路和PLL数字电路使用的1.2V电压、供PLL模拟电路使用的2.5V电压以及供每个电路使用的3.3V电压；所述时钟电路,用于向所述FPGA芯片提供精准的时钟源；所述接口电路,用于对所述FPGA芯片内容进行编程；所述运算放大单元,用于调节放大所述FPGA芯片内的模拟电压。达到可实现对天线阵列的多路程控可调电压馈电,同时有效解决馈电系统体积过大问题,提升天线阵列的实用度的目的。(The invention discloses a four-path adjustable power supply module for an electric control scanning antenna, wherein an FPGA chip is used for providing 1.2V voltage for an internal logic circuit and a PLL digital circuit, providing 2.5V voltage for a PLL analog circuit and providing 3.3V voltage for each circuit by IO voltage; the power supply circuit is used for reducing the input voltage of 30V to 5V and converting the 5V voltage into a 1.2V voltage for the internal logic circuit and the PLL digital circuit, a 2.5V voltage for the PLL analog circuit and a 3.3V voltage for each circuit; the clock circuit is used for providing an accurate clock source for the FPGA chip; the interface circuit is used for programming the content of the FPGA chip; and the operation amplifying unit is used for adjusting and amplifying the analog voltage in the FPGA chip. The multi-path program-controlled adjustable voltage feed to the antenna array can be realized, the problem of overlarge volume of a feed system is effectively solved, and the practicability of the antenna array is improved.)

1. a four-way adjustable power supply module for an electric control scanning antenna is characterized in that,

the FPGA-based power supply circuit comprises an FPGA chip, a power supply circuit, a clock circuit, an interface circuit and an operational amplification unit, wherein the power supply circuit, the clock circuit, the interface circuit and the operational amplification unit are all electrically connected with the FPGA chip;

the FPGA chip is used for providing 1.2V voltage for the internal logic circuit and the PLL digital circuit, providing 2.5V voltage for the PLL analog circuit and providing 1.2V, 1.5V, 1.8V, 2.5V, 3.0V or 3.3V voltage for each circuit by IO voltage;

the power supply circuit is used for reducing the input voltage of 30V to 5V and converting the 5V voltage into a 1.2V voltage for the internal logic circuit and the PLL digital circuit, a 2.5V voltage for the PLL analog circuit and a 3.3V voltage for each circuit;

The clock circuit is used for providing an accurate clock source for the FPGA chip;

The interface circuit is used for programming the content of the FPGA chip and configuring data;

And the operation amplification unit is used for adjusting and amplifying the analog voltage in the FPGA chip to realize continuous and adjustable output amplitude.

2. the four-way adjustable power supply module for an electronically controlled scanning antenna of claim 1,

The power supply circuit comprises a voltage reduction unit, wherein the voltage reduction unit comprises a 30V power supply end, a capacitor C5, a capacitor C6, a capacitor C7, a voltage reduction type management power supply chip, an inductor L1, a Schottky diode D1, a 5V power supply end and a capacitor C, one end of the capacitor C5, one end of the capacitor C6 and one end of the capacitor C7 are electrically connected with the 30V power input end and the VIN terminal of the buck management power chip respectively, the other ends of the capacitor C5, the capacitor C6 and the capacitor C7 are grounded, one end of the inductor L1 is electrically connected to the OUT terminal of the buck management power chip and one end of the schottky diode D1, the other end of the inductor L1 is electrically connected with the FB end of the buck management power supply chip, the 5V power supply end and one end of the capacitor C, the other end of the capacitor C, the GND end of the buck management power supply chip and the other end of the Schottky diode D1 are all grounded.

3. The four-way adjustable power supply module for an electronically controlled scanning antenna of claim 2,

the power circuit further comprises a first conversion unit, the first conversion unit comprises a voltage stabilizing chip, a capacitor C9, a 3.3V power supply end, a capacitor C8, a capacitor C10, a resistor R1 and a light emitting diode D2, a VIN end of the voltage stabilizing chip and one end of the capacitor C9 are electrically connected with the 5V power supply end, a Vo end of the voltage stabilizing chip is electrically connected with the 3.3V power supply end, the 3.3V power supply end is electrically connected with one end of the capacitor C8, the capacitor C10 and one end of the resistor R1 respectively, the other end of the resistor R1 is electrically connected with a positive electrode end of the light emitting diode D2, and the negative electrode end of the light emitting diode D2, the GND end of the voltage stabilizing chip, the capacitor C8, the capacitor C9 and the other end of the capacitor C10 are all grounded.

4. The four-way adjustable power supply module for an electronically controlled scanning antenna of claim 3,

The power circuit further comprises a second conversion unit, wherein the second conversion unit comprises a capacitor C3, a 2.5V power supply end, a capacitor C2 and a capacitor C4, one end of the capacitor C3 and a VIN end of the voltage stabilizing chip are both electrically connected with the 5V power supply end, a Vo end of the voltage stabilizing chip is electrically connected with one ends of the capacitor C2 and the 2.5V power supply end, the other end of the 2.5V power supply end is electrically connected with one end of the capacitor C4, and the capacitor C3, the capacitor C2, the other end of the capacitor C4 and the GND end of the voltage stabilizing chip are all grounded.

5. The four-way adjustable power supply module for an electronically controlled scanning antenna of claim 4,

the power circuit further comprises a third conversion unit, wherein the third conversion unit comprises a capacitor C12, a capacitor C11, a 1.2V power supply end and a capacitor C13, one end of the capacitor C12 and the VIN end of the voltage stabilizing chip are both electrically connected with the 5V power supply end, the Vo end of the voltage stabilizing chip is electrically connected with one ends of the capacitor C11 and the 1.2V power supply end, the other end of the 1.2V power supply end is electrically connected with one end of the capacitor C13, and the capacitor C12, the capacitor C11, the other end of the capacitor 13 and the GND end of the voltage stabilizing chip are all grounded.

6. the four-way adjustable power supply module for an electronically controlled scanning antenna of claim 2,

The clock circuit comprises a capacitor C1 and an active crystal oscillator clock, one end of the capacitor C1 is respectively electrically connected with the 3.3V power supply end and the FPGA chip, the other end of the capacitor C1 is grounded, the CLK end of the FPGA chip is electrically connected with the OUT end of the active crystal oscillator clock, and the GND end of the active crystal oscillator clock is grounded.

7. The four-way adjustable power supply module for an electronically controlled scanning antenna of claim 4,

The interface circuit comprises a JTAG interface, a FLASH and an R5, the JTAG interface comprises a HEADER pin HEADER, a resistor R2, a resistor R3 and a resistor R4, a pin 1 of the HEADER pin HEADER is electrically connected with a TCK end of the FPGA chip and one end of the resistor R4 respectively, the other end of the resistor R4 is grounded, a pin 5 of the HEADER pin HEADER is electrically connected with a TMS end of the FPGA chip and a resistor R3 respectively, a pin 5 of the HEADER pin HEADER is electrically connected with a TMS end of the FPGA chip and one end of the resistor R3 respectively, a pin 9 of the HEADER pin HEADER is electrically connected with a TDI end of the FPGA chip and one end of the resistor R4 respectively, the resistor R4, the other end of the resistor R3 and a pin 4 of the HEADER pin HEADER power supply terminal are electrically connected with the 2.5V power supply terminal respectively, and a pin 2 and a pin 10 of the HEADER pin HEADER pin are grounded;

the NCS end of the FLASH memory is electrically connected with the NCSO end of the FPGA chip, the DATA end of the FLASH memory is electrically connected with the DATA end of the FPGA chip through the resistor R5, the VCC end of the FLASH memory is electrically connected with the VCC end of the FPGA chip, the GND end of the FLASH memory is electrically connected with the GND end of the FPGA chip, the DCLK end of the FLASH memory is electrically connected with the DCLK end of the FPGA chip, and the ASDI end of the FLASH memory is electrically connected with the ASDO end of the FPGA chip.

8. the four-way adjustable power supply module for an electronically controlled scanning antenna of claim 3,

The operational amplification unit comprises a resistor R11, a resistor R13, a first amplifier, a capacitor C42, a capacitor C44, a resistor R21, a resistor R17, a J3 output port, a second amplifier, a relay, a resistor R18, a resistor R23, a diode D5, a triode V3 and a resistor R20, wherein one end of the resistor R11 is electrically connected with an I/O end of the FPGA chip, the other end of the resistor R11 is electrically connected with the resistor R13 and a first end of the first amplifier, the other end of the resistor R13 is grounded, the first end of the first amplifier is electrically connected with one ends of the capacitor C42 and the capacitor C44, the other ends of the capacitor C42 and the capacitor C44 are grounded, the second end of the first amplifier is electrically connected with one ends of the resistor R21 and the resistor R17, the other end of the resistor R21 is grounded, and the other end of the resistor R17 is electrically connected with a third end of the first amplifier, The first end of the second amplifier and the output port of the J3 are electrically connected, the second end and the third end of the second amplifier are electrically connected to the normally closed end of the relay, one end of the resistor R18 is electrically connected to the normally closed end of the relay, the other end of the resistor R18 is electrically connected to the normally open end of the relay and one end of the resistor R23, the other end of the resistor R23 is grounded, the 5V power supply end is electrically connected to one end of the diode D5, the other end of the diode D5 is electrically connected to the emitter of the triode V3, the base of the triode V3 is electrically connected to the resistor R20, and the collector of the triode V3 is grounded.

9. the four-way adjustable power supply module for an electronically controlled scanning antenna of claim 8,

The four-channel adjustable power supply module for the electric control scanning antenna further comprises a voltage display circuit, the voltage display circuit comprises a four-channel analog-to-digital conversion unit, a processing unit and a display unit, and the four-channel analog-to-digital conversion unit, the processing unit and the display unit are electrically connected with the FPGA chip;

the four-channel analog-to-digital conversion unit is used for converting the analog voltage value amplified in the operational amplification unit into digital control quantity, and sending the digital control quantity to the FPGA chip for analysis and processing to obtain each path of voltage value;

The processing unit is used for receiving the voltage values of all paths analyzed and processed by the FPGA chip and driving the display unit;

And the display unit is used for displaying the voltage values of all the channels.

10. The four-way adjustable power supply module for an electronically controlled scanning antenna of claim 9,

The processing unit comprises a single chip microcomputer, a capacitor C49 and a capacitor C50, the VA end of the single chip microcomputer is electrically connected with the 3.3V power supply end, the capacitor C49 and one end of the capacitor C50, and the other ends of the capacitor C49 and the capacitor C50 are grounded.

Technical Field

The invention relates to the technical field of antennas, in particular to a four-path adjustable power supply module for an electric control scanning antenna.

background

with the development of modern electronic information technology, the requirements for antenna characteristics such as beam adjustability, miniaturization, high performance, etc. are increasing, wherein the beam adjustability of the antenna is particularly emphasized. The phased array antenna is a common scheme for realizing a scanning antenna, and phase compensation is realized by changing characteristic parameters of an array element such as length, a rotation angle, corresponding parameters of tunable materials and the like, so that the direction of a main beam of the antenna is changed, and a beam scanning function is further realized. However, the traditional mechanical phased array antenna with heavier mass, complex beam adjustment mode and long response time delay is more and more difficult to meet the requirements of the modern electronic information technology on low time delay and high precision of a communication system, so that the related research of the electrically-controlled phased array antenna is deepened day by day. The electrically tunable phased array antenna has the characteristics of convenient and fast beam adjustment, program control and relatively low mass size, and is the advantage selection for realizing the antenna beam adjustment. One of the key points for realizing the electrically-tunable phased array is the independent tunable feed to each array element of the phased array antenna. The increase of the number of the antenna elements can correspondingly improve the gain of the electric control scanning antenna, but the following problems are that the complexity of a feed system is obviously improved, and the volume of the feed system is also obviously increased, which affects the practical value of the antenna array.

Disclosure of Invention

Aiming at the defects in the prior art, the invention aims to provide a four-way adjustable power supply module for an electric control scanning antenna, which can realize multi-path program control adjustable voltage feed to an antenna array, effectively solve the problem of overlarge volume of a feed system and improve the practicability of the antenna array.

In order to achieve the above object, the four-way adjustable power module for an electronically controlled scanning antenna adopted by the present invention comprises an FPGA chip, a power circuit, a clock circuit, an interface circuit and an operational amplification unit, wherein the power circuit, the clock circuit, the interface circuit and the operational amplification unit are all electrically connected with the FPGA chip;

The FPGA chip is used for providing 1.2V voltage for the internal logic circuit and the PLL digital circuit, providing 2.5V voltage for the PLL analog circuit and providing 1.2V, 1.5V, 1.8V, 2.5V, 3.0V or 3.3V voltage for each circuit by IO voltage;

The power supply circuit is used for reducing the input voltage of 30V to 5V and converting the 5V voltage into a 1.2V voltage for the internal logic circuit and the PLL digital circuit, a 2.5V voltage for the PLL analog circuit and a 3.3V voltage for each circuit;

The clock circuit is used for providing an accurate clock source for the FPGA chip;

the interface circuit is used for programming the content of the FPGA chip and configuring data;

And the operation amplification unit is used for adjusting and amplifying the analog voltage in the FPGA chip to realize continuous and adjustable output amplitude.

Wherein the power circuit comprises a voltage reduction unit, the voltage reduction unit comprises a 30V power supply end, a capacitor C5, a capacitor C6, a capacitor C7, a voltage reduction type management power chip, an inductor L1, a Schottky diode D1, a 5V power supply end and a capacitor C, one end of the capacitor C5, one end of the capacitor C6 and one end of the capacitor C7 are electrically connected with the 30V power input end and the VIN terminal of the buck management power chip respectively, the other ends of the capacitor C5, the capacitor C6 and the capacitor C7 are grounded, one end of the inductor L1 is electrically connected to the OUT terminal of the buck management power chip and one end of the schottky diode D1, the other end of the inductor L1 is electrically connected with the FB end of the buck management power supply chip, the 5V power supply end and one end of the capacitor C, the other end of the capacitor C, the GND end of the buck management power supply chip and the other end of the Schottky diode D1 are all grounded.

The power circuit further comprises a first conversion unit, the first conversion unit comprises a voltage stabilizing chip, a capacitor C9, a 3.3V power supply end, a capacitor C8, a capacitor C10, a resistor R1 and a light emitting diode D2, a VIN end of the voltage stabilizing chip and one end of the capacitor C9 are both electrically connected with the 5V power supply end, a Vo end of the voltage stabilizing chip is electrically connected with the 3.3V power supply end, the 3.3V power supply end is respectively electrically connected with one end of the capacitor C8, the capacitor C10 and one end of the resistor R1, the other end of the resistor R1 is electrically connected with a positive end of the light emitting diode D2, and the negative end of the light emitting diode D2, a GND end of the voltage stabilizing chip, the capacitor C8, the capacitor C9 and the other end of the capacitor C10 are all grounded.

The power circuit further comprises a second conversion unit, the second conversion unit comprises a capacitor C3, a 2.5V power supply end, a capacitor C2 and a capacitor C4, one end of the capacitor C3 and a VIN end of the voltage stabilizing chip are electrically connected with the 5V power supply end, a Vo end of the voltage stabilizing chip is electrically connected with one end of the capacitor C2 and one end of the 2.5V power supply end, the other end of the 2.5V power supply end is electrically connected with one end of the capacitor C4, and the other ends of the capacitor C3, the capacitor C2, the capacitor C4 and the GND end of the voltage stabilizing chip are all grounded.

The power circuit further comprises a third conversion unit, the third conversion unit comprises a capacitor C12, a capacitor C11, a 1.2V power supply end and a capacitor C13, one end of the capacitor C12 and the VIN end of the voltage stabilizing chip are both electrically connected with the 5V power supply end, the Vo end of the voltage stabilizing chip is electrically connected with one end of the capacitor C11 and the 1.2V power supply end, the other end of the 1.2V power supply end is electrically connected with one end of the capacitor C13, and the capacitor C12, the capacitor C11, the other end of the capacitor 13 and the GND end of the voltage stabilizing chip are all grounded.

The clock circuit comprises a capacitor C1 and an active crystal oscillator clock, one end of the capacitor C1 is electrically connected with the 3.3V power supply end and the FPGA chip respectively, the other end of the capacitor C1 is grounded, the CLK end of the FPGA chip is electrically connected with the OUT end of the active crystal oscillator clock, and the GND end of the active crystal oscillator clock is grounded.

the interface circuit comprises a JTAG interface, a FLASH memory and R5, wherein the JTAG interface comprises a HEADER pin HEADER, a resistor R2, a resistor R3 and a resistor R4, a pin 1 of the HEADER pin HEADER is electrically connected with a TCK end of the FPGA chip and one end of the resistor R4 respectively, the other end of the resistor R4 is grounded, a pin 5 of the HEADER pin HEADER is electrically connected with a TMS end of the FPGA chip and a resistor R3 respectively, a pin 5 of the HEADER pin HEADER is electrically connected with a TMS end of the FPGA chip and one end of the resistor R3 respectively, a pin 9 of the HEADER pin HEADER is electrically connected with a TDI end of the FPGA chip and one end of the resistor R4 respectively, the resistor R4, the other end of the resistor R3 and a pin 4 of the HEADER pin HEADER are electrically connected with the 2.5V power supply terminal respectively, and a pin 2 and a pin 10 of the HEADER pin HEADER pin;

the NCS end of the FLASH memory is electrically connected with the NCSO end of the FPGA chip, the DATA end of the FLASH memory is electrically connected with the DATA end of the FPGA chip through the resistor R5, the VCC end of the FLASH memory is electrically connected with the VCC end of the FPGA chip, the GND end of the FLASH memory is electrically connected with the GND end of the FPGA chip, the DCLK end of the FLASH memory is electrically connected with the DCLK end of the FPGA chip, and the ASDI end of the FLASH memory is electrically connected with the ASDO end of the FPGA chip.

The operational amplification unit comprises a resistor R11, a resistor R13, a first amplifier, a capacitor C42, a capacitor C44, a resistor R21, a resistor R17, a J3 output port, a second amplifier, a relay, a resistor R18, a resistor R23, a diode D5, a triode V3 and a resistor R20, wherein one end of the resistor R11 is electrically connected with an I/O terminal of the FPGA chip, the other end of the resistor R11 is electrically connected with the resistor R13 and a first end of the first amplifier, the other end of the resistor R13 is grounded, the first end of the first amplifier is electrically connected with one ends of the capacitor C42 and the capacitor C44, the other ends of the capacitor C42 and the capacitor C44 are grounded, the second end of the first amplifier is electrically connected with one ends of the resistor R21 and the resistor R17, the other end of the resistor R21 is grounded, and the other end of the resistor R17 is electrically connected with a third end of the first amplifier, The first end of the second amplifier and the output port of the J3 are electrically connected, the second end and the third end of the second amplifier are electrically connected to the normally closed end of the relay, one end of the resistor R18 is electrically connected to the normally closed end of the relay, the other end of the resistor R18 is electrically connected to the normally open end of the relay and one end of the resistor R23, the other end of the resistor R23 is grounded, the 5V power supply end is electrically connected to one end of the diode D5, the other end of the diode D5 is electrically connected to the emitter of the triode V3, the base of the triode V3 is electrically connected to the resistor R20, and the collector of the triode V3 is grounded.

The four-channel adjustable power supply module for the electric control scanning antenna further comprises a voltage display circuit, the voltage display circuit comprises a four-channel analog-to-digital conversion unit, a processing unit and a display unit, and the four-channel analog-to-digital conversion unit, the processing unit and the display unit are electrically connected with the FPGA chip;

The four-channel analog-to-digital conversion unit is used for converting the analog voltage value amplified in the operational amplification unit into digital control quantity, and sending the digital control quantity to the FPGA chip for analysis and processing to obtain each path of voltage value;

The processing unit is used for receiving the voltage values of all paths analyzed and processed by the FPGA chip and driving the display unit;

and the display unit is used for displaying the voltage values of all the channels.

the processing unit comprises a single chip microcomputer, a capacitor C49 and a capacitor C50, the VA end of the single chip microcomputer is electrically connected with the 3.3V power supply end, the capacitor C49 and one end of the capacitor C50, and the other ends of the capacitor C49 and the capacitor C50 are grounded.

The invention has the beneficial effects that: the FPGA chip is combined with the operational amplification unit, so that the voltage of 0-25V can be continuously adjusted, and the amplitude can be controlled independently and manually. Compared with the traditional feed system, the volume of the power supply is obviously reduced, the gain, the scanning precision and the working frequency of the electric control scanning antenna array are improved, and the practicability of the antenna is obviously improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic diagram of a four-way adjustable power supply module for an electronically controlled scanning antenna of the present invention.

Fig. 2 is a schematic diagram of an operational amplifier unit according to the present invention.

Fig. 3 is a schematic diagram of a processing unit of the present invention.

fig. 4 is a functional block diagram of a four-channel analog-to-digital conversion unit of the present invention.

Fig. 5 is a schematic diagram of a voltage reducing unit of the present invention.

fig. 6 is a schematic diagram of a first conversion unit of the present invention.

fig. 7 is a schematic diagram of a second conversion unit of the present invention.

Fig. 8 is a schematic diagram of a third conversion unit of the present invention.

fig. 9 is a schematic diagram of the clock circuit of the present invention.

FIG. 10 is a schematic diagram of the JTAG interface of the present invention.

Fig. 11 is a schematic diagram of a FLASH memory of the present invention.

100-four-path adjustable power supply module for electric control scanning antenna, 10-FPGA chip, 20-power supply circuit, 21-voltage reduction unit, 22-first conversion unit, 23-second conversion unit, 24-third conversion unit, 30-clock circuit, 40-interface circuit, 41-JTAG interface, 42-FLASH memory, 50-operation amplification unit, 60-voltage display circuit, 61-four-channel analog-digital conversion unit, 62-processing unit and 63-display unit.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.

in the description of the present invention, it is to be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on the orientations or positional relationships illustrated in the drawings, and are used merely for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be construed as limiting the present invention. Further, in the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

referring to fig. 1 to 11, the present invention provides a four-way adjustable power module 100 for an electronically controlled scanning antenna, including an FPGA chip 10, a power circuit 20, a clock circuit 30, an interface circuit 40, and an operational amplification unit 50, where the power circuit 20, the clock circuit 30, the interface circuit 40, and the operational amplification unit 50 are all electrically connected to the FPGA chip 10;

the FPGA chip 10 is configured to provide a voltage of 1.2V to the internal logic circuit and the PLL digital circuit, provide a voltage of 2.5V to the PLL analog circuit, and provide a voltage of 1.2V, 1.5V, 1.8V, 2.5V, 3.0V, or 3.3V to each circuit through the IO voltage;

The power supply circuit 20 is used for reducing the input voltage of 30V to 5V and converting the 5V voltage into a 1.2V voltage for the internal logic circuit and the PLL digital circuit, a 2.5V voltage for the PLL analog circuit and a 3.3V voltage for each circuit;

The clock circuit 30 is configured to provide a precise clock source to the FPGA chip 10;

The interface circuit 40 is configured to program the content of the FPGA chip 10 and configure data;

The operational amplification unit 50 is configured to adjust and amplify the analog voltage in the FPGA chip 10, so as to achieve continuous and adjustable output amplitude.

In the present embodiment, the FPGA chip 10 uses EP4CE6E22C8 by intel as a control core. The working voltage of the FPGA chip 10 is 1.15V-3.465V, the QFN144 is adopted for packaging, 92I/O ports are included, logic resources are 6272, the operation amplification unit 50 achieves continuous adjustable output amplitude by adjusting and amplifying the analog voltage in the FPGA chip 10, and the power circuit 20 is the most basic circuit which can work normally on an EP4CE6E22C8 board. EP4CE6E22C8 requires 1.0V/1.2V for supplying internal logic circuits (VCCINT) and PLL digital circuits (VCCD _ PLL), 2.5V for supplying PLL analog circuits (VCCA), and IO Voltage (VCCIO) can be accessed to different voltages of 1.2V, 1.5V, 1.8V, 2.5V, 3.0V, and 3.3V to provide different voltage standards for each tile. Therefore, in design, the input 30V voltage is first reduced to 5V, and the 5V voltage is converted to 3.3V, 2.5V, 1.2V to maintain the normal operation of the board, 3.3V is used to supply the clock circuit 30, the operational amplifier circuit, etc. and the high level of the special function pin, 2.5V is used to supply the VCCA voltage, and 1.2V is used to supply VCCINT, VCC _ PLL. Then, the clock circuit 30 controls each time sequence device in the design through a single master clock driven by a dedicated global clock input pin according to the fact that the FPGA chip 10 has the dedicated global clock pin, so as to provide a precise clock source for the FPGA chip 10; the interface circuit 40 is a process for programming the FPGA contents. The requirement for configuration after each power-up is based on one feature of the SRAM process FPGA. Inside the FPGA, a plurality of programmable multiplexers, logics, interconnection line nodes, RAM initialization content and the like are arranged, and digital data are needed to be configured for control. The configuration RAM in the FPGA serves as a means for storing the configuration data. After receiving the analog voltage after the configuration data of the FPGA chip 10, the operational amplification unit 50 adjusts and amplifies the voltage, and then realizes that the output amplitude is continuously adjustable.

The voltage of 0-25V can be continuously adjusted and controlled independently by combining the FPGA chip 10 and the operational amplification unit 50. The design can realize high-precision voltage regulation and control while ensuring 4 independent programmable feeds. Compared with the traditional feed system, the volume of the power supply is obviously reduced, the gain, the scanning precision and the working frequency of the electric control scanning antenna are improved, and the practicability of the antenna is obviously improved.

Further, the power circuit 20 includes a voltage-reducing unit 21, the voltage-reducing unit 21 includes a 30V power supply terminal, a capacitor C5, a capacitor C6, a capacitor C7, a voltage-reducing type management power chip, an inductor L1, a Schottky diode D1, a 5V power supply terminal, and a capacitor C, one end of the capacitor C5, one end of the capacitor C6 and one end of the capacitor C7 are electrically connected with the 30V power input end and the VIN terminal of the buck management power chip respectively, the other ends of the capacitor C5, the capacitor C6 and the capacitor C7 are grounded, one end of the inductor L1 is electrically connected to the OUT terminal of the buck management power chip and one end of the schottky diode D1, the other end of the inductor L1 is electrically connected with the FB end of the buck management power supply chip, the 5V power supply end and one end of the capacitor C, the other end of the capacitor C, the GND end of the buck management power supply chip and the other end of the Schottky diode D1 are all grounded.

in this embodiment, the unit values of the capacitor C5, the capacitor C6 and the capacitor C7 are all 1 μ F, the unit values of the capacitor C are 4.7 μ F and are all decoupling capacitors, the model of the buck management power supply chip is LM2596, the model of the inductor L1 is MSS1210-683MEB, the unit value is 68 μ H, the model of the schottky diode D1 is B560C-13-F, the unit value is 700mv, after the current of the 30V power supply end enters the buck unit 21, the current of the 30V power supply end passes through the capacitor C5, the capacitor C6 and the capacitor C7, the current of the circuit can be subjected to the functions of filtering OUT ripples and decoupling in the current, so as to provide a stable power supply for the power supply circuit 20, then the power supply enters the VIN terminal of the buck management power supply chip, then the power supply is output from the OUT terminal of the buck management power supply chip and respectively flows through the schottky diode D1, The inductor L1 and the capacitor C are grounded, and the power supply drops to the 5V power supply terminal after flowing through the inductor L1,

and then the 5V power supply end is grounded in parallel through a capacitor C1 and a capacitor C2, and the 5V voltage in the 5V power supply end is filtered again to ensure the stability of the circuit power supply.

Further, the power circuit 20 further includes a first converting unit 22, the first converting unit 22 includes a voltage stabilizing chip, a capacitor C9, a 3.3V power end, a capacitor C8, a capacitor C10, a resistor R1, and a light emitting diode D2, a VIN end of the voltage stabilizing chip and one end of the capacitor C9 are both electrically connected to the 5V power end, a Vo end of the voltage stabilizing chip is electrically connected to the 3.3V power end, the 3.3V power end is respectively electrically connected to the capacitor C8, the capacitor C10, and one end of the resistor R1, the other end of the resistor R1 is electrically connected to a positive end of the light emitting diode D2, and the negative end of the light emitting diode D2, the negative end of the voltage stabilizing chip, the capacitor C8, the capacitor C9, and the other end of the capacitor C10 are all grounded.

In this embodiment, the capacitor C9 is 0.1 μ F, the capacitor C8 is 10 μ F, the capacitor C102 is 0.1 μ F, and the voltage regulation chip is AMS117, and after the voltage is reduced from 30V to 5V by the buck management power supply chip, the voltage of 5V enters the VIN terminal of the voltage regulation chip, and after the conversion processing by the voltage regulation chip, the voltage is output from the Vo terminal of the voltage regulation chip and is converted into the power supply terminal of 3.3V, where the power supply terminal is used for supplying the high level to the clock circuit 30, the configuration circuit, and other voltages and the special function pin. The capacitor C9, the capacitor C8 and the capacitor C10 play a role of filtering, and the working state of the power supply can be conveniently checked through the on or off of the light-emitting diode D2. It is to be understood that the resistor employed in the present embodiment may be a fine adjustment resistor.

Further, the power circuit 20 further includes a second converting unit 23, the second converting unit 23 includes a capacitor C3, a 2.5V power end, a capacitor C2, and a capacitor C4, one end of the capacitor C3 and a VIN end of the voltage stabilizing chip are both electrically connected to the 5V power end, a Vo end of the voltage stabilizing chip is electrically connected to one end of the capacitor C2 and the 2.5V power end, the other end of the 2.5V power end is electrically connected to one end of the capacitor C4, and the capacitor C3, the capacitor C2, the other end of the capacitor C4, and a GND end of the voltage stabilizing chip are all grounded.

In this embodiment, the capacitor C3 is 0.1 μ F, the capacitor C2 is 10 μ F, the capacitor C4 is 0.1 μ F, the voltage stabilizing chip is in the model of AMS117, the voltage is reduced from 30V to 5V by the buck management power chip, the voltage of 5V enters the VIN end of the voltage stabilizing chip, and after the conversion processing by the voltage stabilizing chip, the voltage is output from the Vo end of the voltage stabilizing chip and is converted into the power end of 2.5V, so as to supply the VCCA voltage, wherein the capacitor C3, the capacitor C2 and the capacitor C4 play a role in filtering.

Further, the power circuit 20 further includes a third converting unit 24, the third converting unit 24 includes a capacitor C12, a capacitor C11, a 1.2V power end and a capacitor C13, one end of the capacitor C12 and a VIN end of the voltage stabilizing chip are both electrically connected to the 5V power end, a Vo end of the voltage stabilizing chip is electrically connected to one end of the capacitor C11 and the 1.2V power end, the other end of the 1.2V power end is electrically connected to one end of the capacitor C13, and the capacitor C12, the capacitor C11, the other end of the capacitor 13 and the GND end of the voltage stabilizing chip are all grounded.

In this embodiment, the capacitor C12 is 0.1 μ F, the capacitor C11 is 10 μ F, the capacitor C13 is 0.1 μ F, the voltage regulator chip is model AMS117, the voltage is reduced from 30V to 5V by the buck management power supply chip, a voltage of 5V enters the VIN terminal of the voltage regulator chip, the voltage is converted by the voltage regulator chip, the voltage is output from the Vo terminal of the voltage regulator chip and converted into the 1.2V power supply terminal with a voltage of 1.2V, and thereby the VCCINT and the VCC _ PLL voltage are supplied, wherein the capacitor C12, the capacitor C11 and the capacitor C13 perform a filtering function.

further, the clock circuit 30 includes a capacitor C1 and an active crystal oscillator clock, one end of the capacitor C1 is electrically connected to the 3.3V power supply terminal and the FPGA chip 10, the other end of the capacitor C1 is grounded, the CLK terminal of the FPGA chip 10 is electrically connected to the VCC terminal of the active crystal oscillator clock, and the GND terminal of the active crystal oscillator clock is grounded.

In this embodiment, the best solution for the clock in the FPGA design is: a single master clock driven by a dedicated global clock input pin controls each sequential device in the design, should try to use the global clock in the design project whenever possible, the FPGA has a dedicated global clock pin that is directly connected to each register in the device. In the device, the global clock can provide the shortest delay and the highest precision. In the design, a global clock port CLK is used, and the active crystal clock is used as an external clock source because the global clock port CLK is a single clock port. The active crystal oscillator clock adopts crystal oscillator 5070 chip, can produce 50MHz clock, the 3.3V voltage that the 3.3V power end produced passes through FPGA chip 10, later follow the CLK end of FPGA chip 10 passes through the VCC end of active crystal oscillator clock gets into, after the crystal oscillator, follows the OUT end output of active crystal oscillator clock to this provides accurate clock source for the system, wherein electric capacity C1 is 0.1 mu F, can play the filtering action to the circuit.

further, the interface circuit 40 includes a JTAG interface 41, a FLASH memory 42 and a R5, the JTAG interface 41 includes a HEADER pin, a resistor R2, a resistor R3 and a resistor R4, the pin 1 of the HEADER pin is electrically connected to the TCK terminal of the FPGA chip 10 and one end of the resistor R4 respectively, the other end of the resistor R4 is grounded, the pin 5 of the HEADER pin is electrically connected to the TMS terminal of the FPGA chip 10 and the resistor R3 respectively, the pin 5 of the HEADER pin is electrically connected to the TMS terminal of the FPGA chip 10 and one end of the resistor R3 respectively, the pin 9 of the HEADER pin is electrically connected to the TDI terminal of the FPGA chip 10 and one end of the resistor R4 respectively, the other ends of the resistor R4, the resistor R3 and the pin 4 of the HEADER pin are electrically connected to the power supply terminal 2.5V respectively, and the pin 2 and the pin 10 of the HEADER pin are grounded;

The NCS end of the FLASH memory 42 is electrically connected to the NCSO end of the FPGA chip 10, the DATA end of the FLASH memory 42 is electrically connected to the DATA end of the FPGA chip 10 through the resistor R5, the VCC end of the FLASH memory 42 is electrically connected to the VCC end of the FPGA chip 10, the GND end of the FLASH memory 42 is electrically connected to the GND end of the FPGA chip 10, the DCLK end of the FLASH memory 42 is electrically connected to the DCLK end of the FPGA chip 10, and the ASDI end of the FLASH memory 42 is electrically connected to the ASDO end of the FPGA chip 10.

In this embodiment, the interface circuit 40 is a process for programming the FPGA content. The requirement for configuration after each power-up is based on one feature of the SRAM process FPGA. Within the FPGA there are many programmable multiplexers, logic, interconnect nodes and RAM initialization content, all of which require configuration data to control. The configuration RAM in the FPGA serves as a means for storing the configuration data. Depending on the role of the FPAG in configuring the circuit, its configuration data can be loaded (downloaded) to the target device using 3 ways, three of which are: an FPGA Active (Active) mode, an FPGA Passive (Passive) method and a JTAG mode. The JTAG interface 41 is an industry standard interface, the Altera FPGA can basically support JTAG commands to configure the FPGA, and the JTAG configuration mode has higher priority than any other configuration mode, so the board provides the JTAG configuration mode, and in addition, in order to enable the FPGA to still maintain program data after power down, the FPGA needs to be externally connected with a configuration chip, here, the model of the FLASH memory 42 of the Altera company is selected as EPCS16, and the FLASH memory 42 belongs to an enhanced configuration device, the capacity is up to 16Mbit, and supports monolithic configuration of the large-capacity FPGA, which can be programmed in the system by the JTAG interface 41.

Further, the operational amplification unit 50 includes a resistor R11, a resistor R13, a first amplifier, a capacitor C42, a capacitor C44, a resistor R21, a resistor R17, a J3 output port, a second amplifier, a relay, a resistor R18, a resistor R23, a diode D5, a transistor V3, and a resistor R20, one end of the resistor R11 is electrically connected to the I/O terminal of the FPGA chip 10, the other end of the resistor R11 is electrically connected to the resistor R13 and the first end of the first amplifier, the other end of the resistor R13 is grounded, the first end of the first amplifier is electrically connected to one end of the capacitor C42 and the capacitor C44, the other end of the capacitor C42 and the capacitor C44 is grounded, the second end of the first amplifier is electrically connected to one end of the resistor R21 and the resistor R17, the other end of the resistor R21 is grounded, and the other end of the resistor R17 is electrically connected to the first end of the first amplifier, The first end of the second amplifier and the output port of the J3 are electrically connected, the second end and the third end of the second amplifier are electrically connected to the normally closed end of the relay, one end of the resistor R18 is electrically connected to the normally closed end of the relay, the other end of the resistor R18 is electrically connected to the normally open end of the relay and one end of the resistor R23, the other end of the resistor R23 is grounded, the 5V power supply end is electrically connected to one end of the diode D5, the other end of the diode D5 is electrically connected to the emitter of the triode V3, the base of the triode V3 is electrically connected to the resistor R20, and the collector of the triode V3 is grounded.

In this embodiment, the first amplifier with the model of second amplifier is LM358, resistance R11 resistance is 100 Ω, resistance R13 resistance value is 1K Ω, electric capacity C42 value is 10 μ F, electric capacity C440 value is 104 μ F, resistance R21 resistance value is 100 Ω, resistance R17 resistance value is 1K Ω, the relay model is JRC-5M, resistance R18 resistance value is 9K Ω, resistance R23 resistance value is 1K Ω, triode V3 is PNP type triode, and the value is 855 Ω, and resistance R20 is 1K Ω.

the analog voltage generation part is realized by adopting the first amplifier and the second amplifier, the first amplifier and the second amplifier are a double operational amplifier, two high-gain independent double operational amplifiers with internal frequency compensation are arranged in the double operational amplifier, and the double operational amplifier is suitable for a single power supply with a wide voltage range. CH1_ In is the 3.3V square wave or the direct current signal of the I/O mouth output of FPGA chip 10, and preceding one-level is resistance partial pressure and forward proportional amplifier, constitute resistance partial pressure by resistance R11 with resistance R13, through adjusting resistance R13 can change the voltage value of LM358 signal input end, electric capacity C42, electric capacity C44 is the decoupling capacitance of LM358 power supply pin, filters out the power ripple, resistance R17 is the gain resistance, can change the magnification through adjusting resistance R17, then J3 delivery outlet is the output interface, therefore we only need adjust resistance R13 and resistance R17, can make the output In the scope of 0 ~ 25V. Then another operational amplifier is used as a voltage follower to isolate the output end from the voltage sampling end, so that the output voltage instability caused by the interference of sampling on the output is avoided.

Further, the four-channel adjustable power module 100 for the electronically controlled scanning antenna further includes a voltage display circuit 60, the voltage display circuit 60 includes a four-channel analog-to-digital conversion unit 61, a processing unit 62 and a display unit 63, and the four-channel analog-to-digital conversion unit 61, the processing unit 62 and the display unit 63 are all electrically connected to the FPGA chip 10;

The four-channel analog-to-digital conversion unit 61 is configured to convert the analog voltage value amplified in the operational amplification unit 50 into a digital control quantity, and send the digital control quantity to the FPGA chip 10 for analysis and processing to obtain voltage values of each channel;

The processing unit 62 is configured to receive the voltage values of the channels analyzed and processed by the FPGA chip 10, and drive the display unit 63;

the display unit 63 is configured to display the voltage values of the channels.

the processing unit 62 comprises a single chip microcomputer, a capacitor C49 and a capacitor C50, wherein a VA end of the single chip microcomputer is electrically connected with the 3.3V power supply end, the capacitor C49 and one end of the capacitor C50, and the other ends of the capacitor C49 and the capacitor C50 are grounded.

in this embodiment, the four-channel analog-to-digital conversion unit 61 is a 12-bit, four-channel, analog-to-digital conversion chip with model of ADC104S101, the processing unit 62 is a single chip with model of STC15W408S, the capacitor C49 and the capacitor C50, wherein the capacitor C49 and the capacitor C50 play a role of filtering and stabilizing current, the display unit 63 is a display with model of LCD12864, for the voltage display portion in the voltage display circuit 60, analog-to-digital conversion is implemented by using the ADC104S101, since the range of the ADC104S101 is 0 to 3.3V and the output voltage range is 0 to 25V, in order to satisfy precision and implement the range of 0 to 25V, the relay and the resistor are used for dividing voltage, when the voltage value is within 0 to 3V, a low level is provided to the base of the triode V3, the triode V3 is turned on, and the coil of the relay has current flowing through it, at the moment, the relay is attracted, the normally closed end is disconnected, the normally open end is attracted, the switch is switched to a 0-3V gear, and the relay is directly sent to the ADC104S101 for analog-to-digital conversion; when the voltage is within the range of 3V-25V, a high level is provided for the base electrode of the triode V3, the triode V3 is disconnected, no current flows through the relay, the normally closed end is pulled in, a sampling signal is divided through the resistor R18 and the resistor R23, and one tenth of the sampling signal is sent to the ADC104S101 for analog-to-digital conversion. The four-channel analog-to-digital conversion unit 61 communicates with the FPGA chip 10 through an SPI interface, an 8-bit control register is arranged in the four-channel analog-to-digital conversion unit 61, the ADC104S101 can convert the selected channel by writing in each bit of the register, the display module adopts an LCD12864 with a serial interface to display, and after the FPGA chip 10 processes the sampled ADC data, the ADC data is sent to the single-chip microcomputer STC15W408S through the SPI interface, and then the STC15W408S drives the LCD12864 to display each voltage value.

In summary, the following steps: by combining the FPGA chip 10 with the 4-path adjustable power supply module of the operational amplification unit 50, the voltage of 0-25V can be continuously adjusted and independently controlled for the electric control scanning antenna, the problems that a traditional electric control scanning antenna power supply module is complex in control system, the voltage cannot be continuously adjusted, the voltage is unstable, the voltage range is low and the like are effectively solved, the application range of the electric control scanning antenna is expanded, support is provided for high-performance design of the electric control scanning antenna, meanwhile, compared with a traditional feed system, the power supply size is remarkably reduced, the miniaturization and the light weight of the electric control scanning antenna can be supported, the gain, the scanning precision and the working frequency of the electric control scanning antenna are improved, the application range of the electric control scanning antenna is enlarged, the practical degree of the electric control scanning antenna is improved, and the development trend of power supply design is met.

while the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.