阅读说明：本技术 三相四线制pfc母线均压控制方法及装置 (voltage-sharing control method and device for three-phase four-wire system PFC bus ) 是由 刘钧 冯颖盈 姚顺 石倩 于 2019-09-29 设计创作，主要内容包括：本发明涉及一种三相四线制PFC母线均压控制方法及装置,通过比较上电容电压和下电容电压,在任一相线路的AC电压处于正半周时,根据上电容电压与下电容电压的差值,调整任一相线路对应的下开关管的导通时间,以使上电容电压与下电容电压的差值减小；或,在任一相线路的AC电压处于负半周时,根据上电容电压与下电容电压的差值,调整任一相线路对应的上开关管的导通时间,以使上电容电压与下电容电压的差值减小。基于此,减小上电容电压与下电容电压的差值,使母线电压趋于平衡。(the invention relates to a voltage-sharing control method and a device for a three-phase four-wire system PFC bus, which are characterized in that the voltage-sharing control method and the device adjust the conduction time of a lower switch tube corresponding to any phase line according to the difference value of the voltage of an upper capacitor and the voltage of a lower capacitor when the AC voltage of any phase line is in a positive half cycle so as to reduce the difference value of the voltage of the upper capacitor and the voltage of the lower capacitor; or when the AC voltage of any phase of line is in the negative half cycle, adjusting the conduction time of the upper switching tube corresponding to any phase of line according to the difference value of the upper capacitor voltage and the lower capacitor voltage, so that the difference value of the upper capacitor voltage and the lower capacitor voltage is reduced. Therefore, the difference value of the upper capacitor voltage and the lower capacitor voltage is reduced, and the bus voltage tends to be balanced.)

1. a voltage-sharing control method for a three-phase four-wire system PFC bus is applied to a three-phase four-wire system PFC bus topology circuit, and is characterized by comprising the following steps:

Acquiring the AC voltage, the upper capacitor voltage and the lower capacitor voltage of any phase line;

judging whether the AC voltage of any phase line is in a positive half cycle or a negative half cycle according to the change of the AC voltage of any phase line;

when the AC voltage of any phase line is in a positive half cycle, adjusting the conduction time of a lower switch tube corresponding to any phase line according to the difference value of the upper capacitor voltage and the lower capacitor voltage so as to reduce the difference value of the upper capacitor voltage and the lower capacitor voltage;

And when the AC voltage of any phase of line is in a negative half cycle, adjusting the conduction time of an upper switching tube corresponding to any phase of line according to the difference value of the upper capacitor voltage and the lower capacitor voltage so as to reduce the difference value of the upper capacitor voltage and the lower capacitor voltage.

2. The three-phase four-wire system PFC bus voltage-sharing control method according to claim 1, wherein the process of adjusting the conduction time of the lower switching tube corresponding to any phase line according to the difference value between the upper capacitor voltage and the lower capacitor voltage comprises the steps of:

And when the difference value is larger than zero, reducing the conduction time of the lower switching tube corresponding to any phase of line.

3. the three-phase four-wire system PFC bus voltage-sharing control method according to claim 1, wherein the process of adjusting the conduction time of the lower switching tube corresponding to any phase line according to the difference value between the upper capacitor voltage and the lower capacitor voltage comprises the steps of:

and when the difference value is less than zero, increasing the conduction time of the lower switching tube corresponding to the line of any phase.

4. The three-phase four-wire system PFC bus voltage-sharing control method according to claim 1, wherein the process of adjusting the conduction time of the upper switching tube corresponding to any phase line according to the difference value between the upper capacitor voltage and the lower capacitor voltage comprises the steps of:

And when the difference value is larger than zero, increasing the conduction time of the upper switching tube corresponding to any phase of line.

5. The three-phase four-wire system PFC bus voltage-sharing control method according to claim 1, wherein the process of adjusting the conduction time of the upper switching tube corresponding to any phase line according to the difference value between the upper capacitor voltage and the lower capacitor voltage comprises the steps of:

And when the difference value is less than zero, reducing the conduction time of the upper switching tube corresponding to any phase of line.

6. A three-phase four-wire system PFC bus voltage equalizing control method according to claim 2 or 3, wherein the process of decreasing or increasing the on-time of the lower switching tube corresponding to the line of any phase comprises the steps of:

and adjusting the duty ratio of the grid control signal of the lower switching tube according to the product of the difference value and a set proportionality coefficient.

7. the three-phase four-wire system PFC bus voltage sharing control method according to claim 4 or 5, wherein the process of increasing or decreasing the conduction time of the upper switching tube corresponding to any phase line comprises the steps of:

and adjusting the duty ratio of the grid control signal of the upper switching tube according to the product of the difference value and a set proportionality coefficient.

8. the utility model provides a three-phase four-wire system PFC bus voltage-sharing controlling means which characterized in that includes:

the voltage acquisition module is used for acquiring the AC voltage, the upper capacitor voltage and the lower capacitor voltage of any phase line;

The cycle judgment module is used for judging whether the AC voltage of any phase line is in a positive half cycle or a negative half cycle according to the change of the AC voltage of any phase line;

the first adjusting module is used for adjusting the conduction time of a lower switch tube corresponding to any phase line according to the difference value of the upper capacitor voltage and the lower capacitor voltage when the AC voltage of any phase line is in a positive half cycle, so that the difference value of the upper capacitor voltage and the lower capacitor voltage is reduced;

And the second adjusting module is used for adjusting the conduction time of the upper switching tube corresponding to any phase line according to the difference value of the upper capacitor voltage and the lower capacitor voltage when the AC voltage of any phase line is in a negative half cycle, so that the difference value of the upper capacitor voltage and the lower capacitor voltage is reduced.

9. a computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the method of voltage sharing control for a three-phase four-wire PFC bus according to any of claims 1 to 7 when executing the computer program.

10. A computer storage medium having stored thereon a computer program, characterized in that the program, when executed by a processor, implements a three-phase four-wire PFC bus voltage balancing control method according to any one of claims 1 to 7.

Technical Field

The invention relates to the technical field of charging, in particular to a voltage-sharing control method and device for a three-phase four-wire system PFC bus.

Background

With the application of new energy vehicles, pure electric vehicles or hybrid electric vehicles are gradually accepted and understood. With the increase of the endurance mileage of the new energy vehicle, the capacity of the power battery of the new energy vehicle is increased day by day, and the problem to be solved by the new energy vehicle is to improve the charging efficiency to shorten the charging waiting time.

the vehicle-mounted charger serves as an essential core part of a new energy vehicle, and is rapidly developed along with rapid growth of the new energy vehicle. The vehicle-mounted charger comprises an AC/DC alternating current direct current converter and a DC/DC direct current converter for supplying energy to the power battery of the electric vehicle. Compared with a single-phase alternating-current input charger, the three-phase alternating-current input high-power charger can greatly shorten the charging waiting time and is bound to become the dominant force of the future market.

Fig. 1 is a three-phase four-wire PFC (Power Factor Correction) bus topology circuit diagram, as shown in fig. 1, where a, B, C, and N wires are three-phase four-wire AC inputs. As shown in fig. 1, for each phase line of a line a, a line B, or a line C, the flow of the AC input current from point 1 to point 2 indicates that the AC voltage of the phase line is in a positive half cycle; the AC input current flowing from point 2 to point 1 indicates that the AC voltage of the phase line is at a negative half cycle. C1 is an upper capacitor, C2 is a lower capacitor, and the N line is connected with the middle point of the bus capacitor. L1, L2 and L3 are three-phase six-switch boosting inductors. Q1, Q2, Q3, Q4, Q5 and Q6 are switching tubes of the three-phase six-switch PFC, wherein an upper switching tube corresponding to a line A is Q1, and a lower switching tube corresponding to the line A is Q2; by analogy, the upper switch tube corresponding to the line B is Q3, and the lower switch tube corresponding to the line B is Q4; the upper switch tube corresponding to the line C is Q5, and the lower switch tube corresponding to the line C is Q6. As shown in fig. 1, in a three-phase four-wire AC-DC converter, when N wires are connected to a midpoint of a bus capacitor and three phases are pulse-controlled to implement three-phase PFC, there is an imbalance in bus voltage.

disclosure of Invention

Therefore, it is necessary to provide a method and a device for controlling voltage equalization of a three-phase four-wire PFC bus in order to solve the problem of unbalanced bus voltage in a three-phase four-wire PFC bus topology circuit.

a voltage-sharing control method for a three-phase four-wire system PFC bus is applied to a three-phase four-wire system PFC bus topological circuit and comprises the following steps:

Acquiring the AC voltage, the upper capacitor voltage and the lower capacitor voltage of any phase line;

Judging whether the AC voltage of any phase line is in a positive half cycle or a negative half cycle according to the change of the AC voltage of any phase line;

when the AC voltage of any phase line is in a positive half cycle, adjusting the conduction time of a lower switching tube corresponding to any phase line according to the difference value of the upper capacitor voltage and the lower capacitor voltage so as to reduce the difference value of the upper capacitor voltage and the lower capacitor voltage;

and when the AC voltage of any phase of line is in a negative half cycle, adjusting the conduction time of the upper switching tube corresponding to any phase of line according to the difference value of the upper capacitor voltage and the lower capacitor voltage so as to reduce the difference value of the upper capacitor voltage and the lower capacitor voltage.

according to the voltage-sharing control method for the three-phase four-wire PFC bus, the upper capacitor voltage and the lower capacitor voltage are compared, when the AC voltage of any phase line is in the positive half cycle, the conduction time of the lower switch tube corresponding to any phase line is adjusted according to the difference value of the upper capacitor voltage and the lower capacitor voltage, so that the difference value of the upper capacitor voltage and the lower capacitor voltage is reduced; or when the AC voltage of any phase of line is in the negative half cycle, adjusting the conduction time of the upper switching tube corresponding to any phase of line according to the difference value of the upper capacitor voltage and the lower capacitor voltage, so that the difference value of the upper capacitor voltage and the lower capacitor voltage is reduced. Therefore, the difference value of the upper capacitor voltage and the lower capacitor voltage is reduced, and the bus voltage tends to be balanced.

in one embodiment, the process of adjusting the on-time of the lower switch tube corresponding to any phase line according to the difference between the upper capacitor voltage and the lower capacitor voltage includes the steps of:

and when the difference value is larger than zero, reducing the conduction time of the lower switching tube corresponding to any phase of line.

in one embodiment, the process of adjusting the on-time of the lower switch tube corresponding to any phase line according to the difference between the upper capacitor voltage and the lower capacitor voltage includes the steps of:

and when the difference value is less than zero, increasing the conduction time of the lower switching tube corresponding to any phase line.

In one embodiment, the process of adjusting the on-time of the upper switching tube corresponding to any phase of line according to the difference between the upper capacitor voltage and the lower capacitor voltage includes the steps of:

and when the difference value is larger than zero, increasing the conduction time of the upper switching tube corresponding to any phase of circuit.

In one embodiment, the process of adjusting the on-time of the upper switching tube corresponding to any phase of line according to the difference between the upper capacitor voltage and the lower capacitor voltage includes the steps of:

And when the difference value is less than zero, reducing the conduction time of the upper switching tube corresponding to any phase of circuit.

In one embodiment, the process of decreasing or increasing the on-time of the lower switch tube corresponding to any phase line includes the steps of:

and adjusting the duty ratio of the grid control signal of the lower switching tube according to the product of the difference value and the set proportionality coefficient.

in one embodiment, the process of increasing or decreasing the conduction time of the upper switch tube corresponding to any phase line includes the steps of:

And adjusting the duty ratio of the grid control signal of the upper switching tube according to the product of the difference value and the set proportionality coefficient.

A three-phase four-wire system PFC bus voltage-sharing control device comprises:

the voltage acquisition module is used for acquiring the AC voltage, the upper capacitor voltage and the lower capacitor voltage of any phase line;

The period judgment module is used for judging whether the AC voltage of any phase line is in a positive half cycle or a negative half cycle according to the change of the AC voltage of any phase line;

the first adjusting module is used for adjusting the conduction time of a lower switch tube corresponding to any phase line according to the difference value of the upper capacitor voltage and the lower capacitor voltage when the AC voltage of any phase line is in a positive half cycle, so that the difference value of the upper capacitor voltage and the lower capacitor voltage is reduced;

And the second adjusting module is used for adjusting the conduction time of the upper switching tube corresponding to any phase line according to the difference value of the upper capacitor voltage and the lower capacitor voltage when the AC voltage of any phase line is in a negative half cycle, so that the difference value of the upper capacitor voltage and the lower capacitor voltage is reduced.

According to the three-phase four-wire system PFC bus voltage-sharing control device, the upper capacitor voltage and the lower capacitor voltage are compared, when the AC voltage of any phase line is in the positive half cycle, the conduction time of the lower switch tube corresponding to any phase line is adjusted according to the difference value of the upper capacitor voltage and the lower capacitor voltage, so that the difference value of the upper capacitor voltage and the lower capacitor voltage is reduced; or when the AC voltage of any phase of line is in the negative half cycle, adjusting the conduction time of the upper switching tube corresponding to any phase of line according to the difference value of the upper capacitor voltage and the lower capacitor voltage, so that the difference value of the upper capacitor voltage and the lower capacitor voltage is reduced. Therefore, the difference value of the upper capacitor voltage and the lower capacitor voltage is reduced, and the bus voltage tends to be balanced.

a computer device includes a memory, a processor, and a computer program stored on the memory and executable on the processor, and when the processor executes the computer program, the three-phase four-wire system PFC bus voltage-sharing control method according to any of the embodiments is implemented.

According to the computer equipment, by comparing the upper capacitor voltage with the lower capacitor voltage, when the AC voltage of any phase of line is in the positive half cycle, the conduction time of the lower switch tube corresponding to any phase of line is adjusted according to the difference value of the upper capacitor voltage and the lower capacitor voltage, so that the difference value of the upper capacitor voltage and the lower capacitor voltage is reduced; or when the AC voltage of any phase of line is in the negative half cycle, adjusting the conduction time of the upper switching tube corresponding to any phase of line according to the difference value of the upper capacitor voltage and the lower capacitor voltage, so that the difference value of the upper capacitor voltage and the lower capacitor voltage is reduced. Therefore, the difference value of the upper capacitor voltage and the lower capacitor voltage is reduced, and the bus voltage tends to be balanced.

A computer storage medium having stored thereon a computer program that, when executed by a processor, implements the three-phase four-wire PFC bus voltage balancing control method of any of the above embodiments.

The computer storage medium compares the upper capacitor voltage with the lower capacitor voltage, and adjusts the conduction time of the lower switch tube corresponding to any phase line according to the difference value of the upper capacitor voltage and the lower capacitor voltage when the AC voltage of any phase line is in a positive half cycle, so that the difference value of the upper capacitor voltage and the lower capacitor voltage is reduced; or when the AC voltage of any phase of line is in the negative half cycle, adjusting the conduction time of the upper switching tube corresponding to any phase of line according to the difference value of the upper capacitor voltage and the lower capacitor voltage, so that the difference value of the upper capacitor voltage and the lower capacitor voltage is reduced. Therefore, the difference value of the upper capacitor voltage and the lower capacitor voltage is reduced, and the bus voltage tends to be balanced.

drawings

FIG. 1 is a three-phase four-wire PFC bus topology circuit diagram;

fig. 2 is a flowchart of a voltage-sharing control method for a three-phase four-wire system PFC bus according to an embodiment;

FIG. 3 is a schematic diagram of phase A positive half cycle control;

FIG. 4 is a schematic diagram of phase A negative half cycle control;

Fig. 5 is a flowchart of a voltage-sharing control method for a three-phase four-wire system PFC bus according to another embodiment;

Fig. 6 is a voltage-sharing control block diagram of a three-phase four-wire system PFC bus;

fig. 7 is a block diagram of a three-phase four-wire system PFC bus voltage-sharing control apparatus according to an embodiment.

Detailed Description

for better understanding of the objects, technical solutions and effects of the present invention, the present invention will be further explained with reference to the accompanying drawings and examples. Meanwhile, the following described examples are only for explaining the present invention, and are not intended to limit the present invention.

Fig. 2 is a flowchart of a voltage-sharing control method for a three-phase four-wire system PFC bus according to an embodiment, and as shown in fig. 2, the voltage-sharing control method for the three-phase four-wire system PFC bus according to an embodiment is applied to a topology circuit of the three-phase four-wire system PFC bus shown in fig. 1, and includes steps S100 to S103:

s100, acquiring the AC voltage of any phase line, the voltage of an upper capacitor C1 and the voltage of a lower capacitor C2;

as shown in fig. 2, the three-phase four-wire PFC bus topology circuit includes three-phase lines A, B and C. The AC voltage of the line of any phase is collected. The voltage of the upper capacitor C1 is the voltage of the capacitor C1, and the voltage of the upper capacitor C1 is the voltage of the capacitor C2.

S101, judging whether the AC voltage of any phase line is in a positive half cycle or a negative half cycle according to the change of the AC voltage of any phase line;

as shown in fig. 2, it is determined whether the AC voltage of any one phase line is in a positive half cycle or a negative half cycle, that is, an AC current flows from a point 1 to a point 2 in the positive half cycle, and an AC current flows from a point 2 to a point 1 in the negative half cycle, according to a change in the AC voltage of any one phase line.

S102, when the AC voltage of any phase line is in a positive half cycle, adjusting the conduction time of a lower switch tube Q2 corresponding to any phase line according to the difference value of the voltage of an upper capacitor C1 and the voltage of a lower capacitor C2 so as to reduce the difference value of the voltage of the upper capacitor C1 and the voltage of the lower capacitor C2;

And S103, when the AC voltage of any phase line is in a negative half cycle, adjusting the conduction time of the upper switch tube Q1 corresponding to any phase line according to the difference between the voltage of the upper capacitor C1 and the voltage of the lower capacitor C2, so that the difference between the voltage of the upper capacitor C1 and the voltage of the lower capacitor C2 is reduced.

Fig. 3 is a schematic diagram of the positive half cycle control of the phase a, and as shown in fig. 3, the analysis is performed by controlling the phase a among the three phases ABC, and the analysis is performed when the input AC voltage of the phase a is in the positive half cycle:

When the AC voltage is in a positive half cycle, the Q2 is used as a switching tube to store energy when being switched on, the current flows from L1 to Q2 and then passes through C2, and at the moment, the lower capacitor C2 discharges;

When the AC voltage is in a positive half cycle, Q2 flows as the switch tube is closed, the current flows from L1 to the body diode of Q1 and then passes through C1, and the upper capacitor C1 is charged;

When the AC voltage is in the positive half cycle, the on-time of the lower switching tube Q2 is reduced, and then the C1 is charged more and the C2 is discharged less, because the change rate of the energy storage loop current is faster than that of the freewheeling loop current, the result is: the voltages of C1 and C2 are relatively increased, but the C2 is increased by more than C1, so that the difference between the voltage of C1 and the voltage of C2 is relatively reduced;

when the AC voltage is in the positive half cycle, increasing the on-time of the lower switching tube Q2, the C1 is charged less and the C2 is discharged more, because the change rate of the energy storage loop current is faster than that of the freewheeling loop current, the result is: both the C1 and C2 voltages decreased relatively, but C2 decreased by a greater amount than C1, so the difference between the C1 and C2 voltages increased relatively.

Fig. 4 is a schematic diagram of the negative half cycle control of the phase a, and as shown in fig. 4, the analysis is performed as the control of the phase a in the three phases ABC, and the analysis is performed when the input AC voltage of the phase a is at the negative half cycle:

When the AC voltage is in a negative half cycle, the Q1 is used as a switching tube to store energy when being switched on, the current flows from C1 to Q1 to pass through L1, and at the moment, the upper capacitor C1 discharges;

when the AC voltage is in a negative half cycle, Q1 is used as freewheeling when the switching tube is closed, the current from the body diode of C2 to Q2 passes through L1 again, and the lower capacitor C2 is charged;

When the AC voltage is in the negative half cycle, the on-time of the upper switching tube Q1 is reduced, and then the C2 is charged more and the C1 is discharged less, because the change rate of the energy storage loop current is faster than that of the freewheeling loop current, the result is: the voltages of C1 and C2 are relatively increased, but the C1 is increased by more than C2, so that the difference between the voltage of C1 and the voltage of C2 is relatively increased;

when the AC voltage is in the negative half cycle, increasing the on-time of the upper switching tube Q1, the C2 is charged less and the C1 is discharged more, because the change rate of the energy storage loop is faster than that of the freewheeling loop current, the result is: both the C1 and C2 voltages were relatively reduced, but C1 was reduced by a greater amount than C2, so the difference between the C1 and C2 voltages was relatively reduced.

Based on the above analysis, fig. 5 is a flowchart of a three-phase four-wire system PFC bus voltage-sharing control method according to another embodiment, and as shown in fig. 5, a process of adjusting the on-time of the lower switch tube Q2 corresponding to any phase line according to the difference between the voltage of the upper capacitor C1 and the voltage of the lower capacitor C2 in step S102 includes step S200:

And S200, when the difference value is larger than zero, reducing the conduction time of the lower switching tube Q2 corresponding to any phase line.

When the difference is greater than zero, that is, the voltage of the upper capacitor C1 is greater than the voltage of the lower capacitor C2, the voltage of the lower capacitor C2 is increased by an amount greater than the voltage of the upper capacitor C1 by decreasing the on-time of the lower switch transistor Q2 corresponding to any phase circuit, so as to reduce the difference.

In one embodiment, as shown in fig. 5, the process of adjusting the on-time of the lower switch Q2 corresponding to any phase line according to the difference between the voltage of the upper capacitor C1 and the voltage of the lower capacitor C2 in step S102 includes step S201:

and S201, when the difference is less than zero, increasing the conduction time of the lower switch tube Q2 corresponding to any phase line.

when the difference is less than zero, namely the voltage of the upper capacitor C1 is less than the voltage of the lower capacitor C2, the voltage of the lower capacitor C2 is reduced by more than the voltage of the upper capacitor C1 by increasing the conduction time of the lower switch tube Q2 corresponding to any phase line, so as to reduce the difference.

In one embodiment, as shown in fig. 5, the process of adjusting the on-time of the upper switch Q1 corresponding to any phase of the line according to the difference between the voltage of the upper capacitor C1 and the voltage of the lower capacitor C2 in step S103 includes step S202:

and S202, when the difference value is larger than zero, increasing the conduction time of the upper switching tube Q1 corresponding to any phase line.

When the difference is greater than zero, that is, the voltage of the upper capacitor C1 is greater than the voltage of the lower capacitor C2, the voltage of the upper capacitor C1 is reduced by an amount greater than that of the lower capacitor C2 by increasing the on-time of the upper switch tube Q1 corresponding to any phase of circuit, so as to reduce the difference.

in one embodiment, as shown in fig. 5, the process of adjusting the on-time of the upper switch Q1 corresponding to any phase of the line according to the difference between the voltage of the upper capacitor C1 and the voltage of the lower capacitor C2 in step S103 includes step S203:

and S203, when the difference is less than zero, reducing the conduction time of the upper switching tube Q1 corresponding to any phase line.

When the difference is less than zero, that is, the voltage of the upper capacitor C1 is less than the voltage of the lower capacitor C2, the voltage of the upper capacitor C1 is increased by an amount greater than that of the lower capacitor C2 by reducing the on-time of the upper switch tube Q1 corresponding to any phase of circuit, so as to reduce the difference.

in one embodiment, the process of decreasing the on-time of the lower switch Q2 corresponding to any phase of the line in step S200 or the process of increasing the on-time of the lower switch Q2 corresponding to any phase of the line in step S201 includes step S300:

And S300, adjusting the duty ratio of the grid control signal of the lower switching tube Q2 according to the product of the difference and the set proportionality coefficient.

The duty ratio of the gate control signal of the lower switch tube Q2 is adjusted by taking the product of the difference and the set scaling factor as an adjustment value of the duty ratio of the gate control signal of the lower switch tube Q2.

In one embodiment, as shown in fig. 5, the process of increasing the on-time of the upper switch Q1 corresponding to any phase of the line in step S202 or the process of decreasing the on-time of the upper switch Q1 corresponding to any phase of the line in step S203 includes step S301:

And S301, adjusting the duty ratio of the gate control signal of the upper switching tube Q1 according to the product of the difference and the set proportionality coefficient.

The duty ratio of the gate control signal of the lower switch tube Q2 is adjusted by taking the product of the difference and the set scaling factor as an adjustment value of the duty ratio of the gate control signal of the upper switch tube Q1.

fig. 6 is a three-phase four-wire system PFC bus voltage-sharing control block diagram, where as shown in fig. 6, Δ Duty is an adjustment value of a Duty ratio of a gate control signal of the upper switching tube Q1 or the lower switching tube Q2, Kp is a set proportionality coefficient, vlopout is an output of a voltage loop, ilorpef is a given of a current loop, and sinV is a sinusoidal signal value of an input voltage. The above steps S300 and S301 may be combined as follows:

when Vc1 is greater than Vc2, Delta Duty is (Vc1-Vc2) Kp;

when Vc2 is greater than Vc1, Delta Duty is (Vc2-Vc1) Kp;

IloopRef＝(VloopOut+ΔDuty)*sinV；

as shown in fig. 6, after the current loop current Iloop is determined, the duty ratio of the gate control signal of the upper or lower switching tube Q2 is adjusted.

In the voltage-sharing control method for the three-phase four-wire system PFC bus according to any embodiment, when the AC voltage of any phase line is in a positive half cycle by comparing the voltage of the upper capacitor C1 with the voltage of the lower capacitor C2, the on-time of the lower switch tube Q2 corresponding to any phase line is adjusted according to the difference between the voltage of the upper capacitor C1 and the voltage of the lower capacitor C2, so that the difference between the voltage of the upper capacitor C1 and the voltage of the lower capacitor C2 is reduced; or when the AC voltage of any phase line is in the negative half cycle, the on-time of the upper switch Q1 corresponding to any phase line is adjusted according to the difference between the voltage of the upper capacitor C1 and the voltage of the lower capacitor C2, so that the difference between the voltage of the upper capacitor C1 and the voltage of the lower capacitor C2 is reduced. Therefore, the difference between the voltage of the upper capacitor C1 and the voltage of the lower capacitor C2 is reduced, and the bus voltage tends to be balanced.

The embodiment of the invention also provides a voltage-sharing control device for the three-phase four-wire system PFC bus.

Fig. 7 is a block diagram of a three-phase four-wire system PFC bus voltage-sharing control apparatus according to an embodiment, and as shown in fig. 7, the apparatus includes blocks 100, 101, 102, and 103:

the voltage acquisition module 100 is used for acquiring the AC voltage of any phase line, the voltage of the upper capacitor C1 and the voltage of the lower capacitor C2;

The period judgment module 101 is configured to judge whether the AC voltage of any phase line is in a positive half cycle or a negative half cycle according to a change of the AC voltage of any phase line;

The first adjusting module 102 is configured to, when the AC voltage of the line of any phase is in a positive half cycle, adjust the on-time of the lower switch Q2 corresponding to the line of any phase according to a difference between the voltage of the upper capacitor C1 and the voltage of the lower capacitor C2, so that the difference between the voltage of the upper capacitor C1 and the voltage of the lower capacitor C2 is reduced;

the first adjusting module 102 includes a first lower switch Q2 adjusting module 200 and a second lower switch Q2 adjusting module 201:

the first lower switch Q2 adjusting module 200 is configured to reduce the on-time of the lower switch Q2 corresponding to any phase line when the difference is greater than zero.

The second lower switch Q2 adjusting module 201 is configured to increase the on-time of the lower switch Q2 corresponding to any phase line when the difference is less than zero.

The second adjusting module 103 is configured to adjust the on-time of the upper switch Q1 corresponding to any phase line according to the difference between the voltage of the upper capacitor C1 and the voltage of the lower capacitor C2 when the AC voltage of any phase line is in a negative half cycle, so that the difference between the voltage of the upper capacitor C1 and the voltage of the lower capacitor C2 is reduced.

The second adjusting module 103 includes a first upper switch Q1 adjusting module 202 and a second upper switch Q1 adjusting module 203:

the first upper switch Q1 adjusting module 202 is configured to increase the on-time of the upper switch Q1 corresponding to any phase line when the difference is greater than zero.

The second upper switch Q1 adjusting module 203 is configured to reduce the on-time of the upper switch Q1 corresponding to any phase line when the difference is less than zero.

in the three-phase four-wire system PFC bus voltage-sharing control device according to any of the embodiments, by comparing the voltage of the upper capacitor C1 with the voltage of the lower capacitor C2, when the AC voltage of any phase line is in a positive half cycle, the on-time of the lower switch tube Q2 corresponding to any phase line is adjusted according to the difference between the voltage of the upper capacitor C1 and the voltage of the lower capacitor C2, so that the difference between the voltage of the upper capacitor C1 and the voltage of the lower capacitor C2 is reduced; or when the AC voltage of any phase line is in the negative half cycle, the on-time of the upper switch Q1 corresponding to any phase line is adjusted according to the difference between the voltage of the upper capacitor C1 and the voltage of the lower capacitor C2, so that the difference between the voltage of the upper capacitor C1 and the voltage of the lower capacitor C2 is reduced. Therefore, the difference between the voltage of the upper capacitor C1 and the voltage of the lower capacitor C2 is reduced, and the bus voltage tends to be balanced.

Based on the above examples, in one embodiment, a computer device is further provided, where the computer device includes a memory, a processor, and a computer program stored on the memory and executable on the processor, and when the processor executes the program, the method for controlling voltage equalization of a three-phase four-wire PFC bus according to any one of the above embodiments is implemented.

the computer equipment compares the voltage of the upper capacitor C1 with the voltage of the lower capacitor C2 through a computer program running on a processor, and adjusts the conduction time of the lower switch tube Q2 corresponding to any phase line according to the difference value of the voltage of the upper capacitor C1 and the voltage of the lower capacitor C2 when the AC voltage of any phase line is in a positive half cycle, so that the difference value of the voltage of the upper capacitor C1 and the voltage of the lower capacitor C2 is reduced; or when the AC voltage of any phase line is in the negative half cycle, the on-time of the upper switch Q1 corresponding to any phase line is adjusted according to the difference between the voltage of the upper capacitor C1 and the voltage of the lower capacitor C2, so that the difference between the voltage of the upper capacitor C1 and the voltage of the lower capacitor C2 is reduced. Therefore, the difference between the voltage of the upper capacitor C1 and the voltage of the lower capacitor C2 is reduced, and the bus voltage tends to be balanced.

it can be understood by those skilled in the art that all or part of the processes in the methods for implementing the embodiments described above can be implemented by instructing relevant hardware through a computer program, and the program can be stored in a non-volatile computer-readable storage medium, and as in the embodiments of the present invention, the program can be stored in the storage medium of a computer system and executed by at least one processor in the computer system, so as to implement the processes including the embodiments of the three-phase four-wire system PFC bus voltage-sharing control method described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.

Accordingly, in an embodiment, there is also provided a storage medium having a computer program stored thereon, wherein the program is executed by a processor to implement any one of the three-phase four-wire system PFC bus voltage-sharing control methods in the embodiments described above.

the computer storage medium, through the stored computer program, compares the voltage of the upper capacitor C1 with the voltage of the lower capacitor C2, when the AC voltage of any phase line is in the positive half cycle, according to the difference between the voltage of the upper capacitor C1 and the voltage of the lower capacitor C2, the on-time of the lower switch tube Q2 corresponding to any phase line is adjusted, so that the difference between the voltage of the upper capacitor C1 and the voltage of the lower capacitor C2 is reduced; or when the AC voltage of any phase line is in the negative half cycle, the on-time of the upper switch Q1 corresponding to any phase line is adjusted according to the difference between the voltage of the upper capacitor C1 and the voltage of the lower capacitor C2, so that the difference between the voltage of the upper capacitor C1 and the voltage of the lower capacitor C2 is reduced. Therefore, the difference between the voltage of the upper capacitor C1 and the voltage of the lower capacitor C2 is reduced, and the bus voltage tends to be balanced.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

the above examples only show some embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.