阅读说明：本技术 电子电源 (Electronic power supply ) 是由 M·屈埃卡 C·托马斯 于 2019-05-28 设计创作，主要内容包括：本公开的实施例涉及电子电源。一种电子电路,包括经由第一线性电压调节器为第一负载供电的开关模式电源。第一调节器包括晶体管。晶体管的衬底和栅极能够耦合到电源电压的施加节点。还公开了一种操作电路的方法。(Embodiments of the present disclosure relate to electronic power supplies. An electronic circuit comprises a switched mode power supply for powering a first load via a first linear voltage regulator. The first regulator includes a transistor. The substrate and gate of the transistor can be coupled to an application node of a supply voltage. A method of operating a circuit is also disclosed.)

1. an electronic circuit, comprising:

a switched mode power supply;

A first load; and

A first linear voltage regulator, wherein the switch mode power supply is configured to power the first load via the first linear voltage regulator, the first linear voltage regulator comprising a transistor having a substrate and a gate, the substrate and the gate selectively coupled to a supply voltage node.

2. the circuit of claim 1, wherein the first load comprises a logic circuit.

3. The circuit of claim 1, further comprising a second load, wherein the switched mode power supply is coupled to directly power the second load.

4. The circuit of claim 3, wherein the second load comprises a radio frequency signal transmit/receive circuit.

5. The circuit of claim 3, wherein the circuit is configured to operate in a first operating state in which the substrate of the transistor is connected to an output of the switched mode power supply, the gate of the transistor is not connected to the supply voltage node, and the second load is operating.

6. the circuit of claim 5, wherein the circuit is configured to operate in a second operating state in which the substrate and the gate of the transistor are connected to the supply voltage node and the second load is off.

7. The circuit of claim 3, wherein the circuit is configured to operate in an operating state in which the substrate and the gate of the transistor are connected to the supply voltage node and the second load is off.

8. The circuit of claim 1, wherein the transistor has a current path coupled between an output of the switched mode power supply and the first load.

9. The circuit of claim 8, further comprising an operational amplifier having an output coupled to the gate of the transistor.

10. The circuit of claim 9, wherein the operational amplifier has a first input coupled to a reference voltage node, and a second input coupled to the first load.

11. The circuit of claim 1, wherein the substrate of the transistor is switchable between the supply voltage node and an output of the switch mode power supply.

12. The circuit of claim 1, comprising a second linear voltage regulator in series with a switch, the second linear voltage regulator and the switch coupled between the supply voltage node and the first load.

13. The circuit of claim 12, wherein the second linear voltage regulator comprises a low power linear voltage regulator.

14. an electronic circuit, comprising:

A supply voltage node;

a switched mode power supply;

a first load;

A second load coupled to an output of the switched mode power supply at a switched mode power supply node; and

A first linear voltage regulator having an output coupled to the first load, wherein the first linear voltage regulator comprises:

An operational amplifier;

A transistor having a gate coupled to an output of the operational amplifier;

A first switch having a current path coupled between the supply voltage node and the gate of the transistor; and

A second switch having a first terminal coupled to the body of the transistor, the second switch having a second terminal switchable between the supply voltage node and an output of the switch mode power supply.

15. The circuit of claim 14, wherein the switch-mode power supply is configured to power the first load via the first linear voltage regulator, and wherein the switch-mode power supply is coupled to directly power the second load.

16. The circuit of claim 14, wherein:

The circuit is configured to operate in a first operating state in which the body of the transistor is connected to the output of the switched mode power supply, the gate of the transistor is not connected to the supply voltage node, and the second load is operating; and is

The circuit is configured to operate in a second operating state in which the body and the gate of the transistor are connected to the supply voltage node and the second load is off.

17. The circuit of claim 14, wherein the operational amplifier has a first input coupled to a reference voltage node, and a second input coupled to the first load.

18. The circuit of claim 14, further comprising a second linear voltage regulator in series with a third switch, the second linear voltage regulator and the third switch coupled between the supply voltage node and the first load.

19. A method of operating a circuit comprising a switched mode power supply, a first load, a second load coupled to the switched mode power supply, and a first linear voltage regulator coupled between the switched mode power supply and the first load, the first linear voltage regulator comprising a transistor having a substrate and a control terminal, the substrate and the control terminal being selectively coupled to a supply voltage node, the method comprising:

operating the circuit in a first operating state in which the substrate of the transistor is connected to the output of the switched mode power supply, the control terminal of the transistor is not connected to the supply voltage node, and the second load is operating; and

operating the circuit in a second operating state in which the substrate and the control terminal of the transistor are connected to the supply voltage node and the second load is off.

20. The method of claim 19, wherein in the first operating state, the control terminal of the transistor is driven by an operational amplifier.

Technical Field

The present disclosure relates to electronic circuits, and more particularly to circuits including switched mode power supplies.

Background

A switched mode power supply is a DC/DC converter comprising one or more switching elements. Like other types of power supplies, switched mode power supplies deliver power supplied by a DC source to a load, thereby modifying the current and/or voltage characteristics.

Disclosure of Invention

One embodiment provides an electronic circuit comprising a switched mode power supply for supplying a first load via a first linear voltage regulator. The first regulator includes a transistor. The substrate and gate of the transistor can be coupled to an application node of a supply voltage.

According to one embodiment, the first load comprises a logic circuit.

According to one embodiment, the switched mode power supply directly supplies power to the second load.

According to one embodiment, the second load comprises a radio frequency signal transmission and/or reception circuit.

According to one embodiment, the transistor is connected between the output of the switched mode power supply and the input of the first load by a source and a drain. The transistor is controlled by an operational amplifier that receives as inputs a reference voltage and an input voltage of the first load.

According to one embodiment, the substrate of the transistor can be connected to an application node of a supply voltage or to an output of a switched mode power supply.

According to one embodiment, the circuit comprises the following operating states: in this operating state, the substrate of the transistor is connected to the output of the switch-mode power supply, the gate of the transistor is not connected to the application node of the power supply voltage, and the second load is operating.

According to one embodiment, the circuit includes an operating state in which the substrate and the gate of the transistor are connected to the application node of the power supply voltage and the second load is off.

according to one embodiment, the circuit includes a second linear voltage regulator coupled in series with the switch between an application node of the supply voltage and an input of the first load.

the foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.

Drawings

FIG. 1 is a simplified representation of one embodiment of an electronic circuit; and

Fig. 2 is a more detailed simplified representation of elements of the circuit of fig. 1.

Detailed Description

Like elements in different figures are designated by like reference numerals. In particular, structural and/or functional elements common to different embodiments may be designated with the same reference numerals and may have the same structure, dimensions and material properties.

For clarity, only those steps and elements useful for understanding the described embodiments are shown and described in detail.

Unless otherwise specified, throughout this disclosure, the term "connected" is used to designate a direct electrical connection between circuit elements, while the term "coupled" is used to designate an electrical connection between circuit elements that may be direct, or may be via one or more other elements.

in the following description, when referring to terms defining an absolute position (such as the terms "front", "back", "top", "bottom", "left", "right", etc.), or a relative position (such as the terms "above", "below", "upper", "lower", etc.), or a direction (such as the terms "horizontal", "vertical", etc.), it refers to the orientation of the drawing figures.

Unless otherwise specified, the terms "about," "substantially," and "on the order of …." are used herein to designate a tolerance of plus or minus 10%, preferably plus or minus 5%, of the value in question.

Fig. 1 is a simplified representation of one embodiment of an electronic circuit 100.

The circuit 100 includes a first load, such as a circuit 102 (CORE). The circuit 102 includes, for example, logic elements such as a microprocessor and a memory.

The circuit 100 further comprises a switched mode power supply 104(DC-DC converter). The switched mode power supply 104 is connected at its input to an application node 103 of a supply voltage VDD and at its output to a first terminal of an inductance 106 (L). A second terminal of inductance 106 is connected to node 108. The voltage on node 108 is the voltage VDCDC supplied by the switched mode power supply 104. Node 108 is coupled to ground through capacitor 110 (C).

The circuit 100 may also include a second load, such as a Radio Frequency (RF) signal transmit/receive circuit 112 (i.e., a circuit that can transmit RF signals, receive RF signals, or both transmit and receive RF signals). Circuit 112 is connected between node 108 and ground and is powered by switched mode power supply 104.

The circuit 100 also includes a linear voltage regulator 114 (LDO). Regulator 114 is connected at its inputs to node 108 (voltage VDCDC) and to the application node 103 of voltage VDD, and at its output to node 116. One embodiment of the regulator 114 is described in further detail in conjunction with fig. 2.

Circuit 102 is connected between node 116 and ground. Thus, the circuit 102 is powered by the switched mode power supply 104 in series with the regulator 114.

The circuit 100 may comprise another linear voltage regulator 118 (low power LDO) intended for low power operation modes. The regulator 118 is coupled between the application node 103 of the voltage VDD and a first terminal of a switch 120. A second terminal of switch 120 is connected to node 116.

In the first mode of operation, the switched mode power supply 104 is operating. The switched mode power supply 104 directly powers the circuit 112 and powers the circuit 102 via the regulator 114. In addition, the switch 120 is turned off. Thus, the regulator 118, which may or may not be operated, has no effect on the circuit 100.

In a second mode of operation, called "low power", the switch mode power supply 104 and the regulator 114 are not operating, and the unpowered circuit 112 is not operating. The switch 120 is conductive and the regulator 118 is operating, which enables at least a portion of the components of the circuit 102 to be powered.

In a third mode of operation, called "standby", either the circuit 112 is absent or the circuit 112 is off and the switch 120 is off. The switch mode power supply 104 and the regulator 114 do not operate. The circuit 102 is not powered.

The regulator 118 is configured to supply a relatively low power compared to the power supplied by the regulator 114, e.g., sufficient power to power a portion of the components of the circuit 102 normally in the standby mode. The regulator 118 is configured, for example, to be able to power volatile memory included within the circuit 102.

Fig. 2 is a more detailed simplified representation of one embodiment of the linear regulator 114. As in fig. 1, regulator 114 includes two inputs connected to an application node 103 of supply voltage VDD and node 108. Regulator 114 also includes an output connected to node 116.

the regulator includes a transistor 202 connected between the terminal 116 and the terminal 108. The transistor 202 (e.g., a PMOS type transistor) is controlled by an operational amplifier 204. Operational amplifier 204 is powered by voltage VDD and voltage VDCDC. The positive (+) and negative (-) inputs of the operational amplifier are connected to node 116 and the application node of a reference voltage VREF (e.g., below VDCDC), respectively.

The regulator 114 includes a switch 206 that couples the gate of the transistor (the output of the operational amplifier 204) to the application node 103 of the voltage VDD. Accordingly, the gate of the transistor 202 may or may not be connected to the application node 103 of the voltage VDD, and the voltage VDD may or may not be applied to the gate of the transistor 202.

The regulator 114 may also include a switch 208, the switch 208 coupling the substrate of the transistor 202 to the application node 103 of the voltage VDD, or to the node 108. Thus, the voltage applied to the substrate of transistor 202 may be voltage VDCDC, or voltage VDD.

The linear voltage regulator 114 may optionally be connected in parallel with the switched mode power supply 104, i.e. between the applied node 103 of the voltage VDD and the node 108 forming the output of the switched mode power supply. Circuit 102 will then be connected in parallel with circuit 112 between node 108 and ground.

at this time, however, there is a risk that noise generated by the switched mode power supply 104 will be transmitted to the circuit 112 via a substrate common to the circuit 112 and the circuit 102. In practice, circuit 112 is configured to reject only noise that reaches it directly from node 108, and is therefore sensitive to noise transmitted by circuit 102.

During the previously described first mode of operation in which circuitry 102 and circuitry 112 are powered by switch-mode power supply 104 and regulator 114, switch 206 is turned off and switch 208 (if present) couples the substrate of transistor 202 to node 108. Thus, noise generated by the switched mode power supply 104 is not transmitted to the node 116, and therefore, the noise is not transmitted to the common substrate of the circuit 112 and the circuit 102.

During a second mode of operation, called "low power", switch 206 is conductive and switch 208 couples the substrate of the transistor to the application node 103 of voltage VDD. Thus, the voltage VDD is applied to the substrate and the gate of the transistor 202. This enables current leakage between node 108 and node 116 to be avoided. This thus enables to avoid discharging the capacitor 110 during this mode of operation. In practice, transistor 202 is off and the gate/source and gate/drain voltages of transistor 202 are negative, so leakage between drain and source is negligible.

various embodiments and modifications have been described. These various embodiments and variations may be combined, and others will occur to those skilled in the art.

Finally, the actual implementation of the described embodiments and variants is within the abilities of a person skilled in the art based on the functional indications given above.

Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only and is not intended as limiting. The invention is limited only as defined in the following claims and equivalents thereto.