阅读说明：本技术 基于fpga的多通道雷达回波信号传输方法及系统 (Multi-channel radar echo signal transmission method and system based on FPGA ) 是由 钟山 杨松 许桂文 于 2021-07-30 设计创作，主要内容包括：本公开提供一种基于FPGA的多通道雷达回波信号传输方法,包括：操作S1：将接收的雷达回波数据打包成不同的数据包后按设定周期依次输出；操作S2：将所述不同的数据包经判断后依次存储于不同的缓存区；操作S3：监测数据包的存储状态,根据所述存储状态改变存储位置同时读取已完成存储的缓存区中的数据包；以及操作S4：将读取的数据转换为光信号并通过光纤传输。同时本公开还提供一种基于FPGA的多通道雷达回波信号传输系统。(The utility model provides a multichannel radar echo signal transmission method based on FPGA, comprising: operation S1: packaging the received radar echo data into different data packets and then sequentially outputting the data packets according to a set period; operation S2: the different data packets are judged and then sequentially stored in different cache regions; operation S3: monitoring the storage state of the data packet, changing the storage position according to the storage state, and simultaneously reading the data packet in the cache region which is stored completely; and operation S4: the read data is converted into an optical signal and transmitted through an optical fiber. The utility model also provides a multichannel radar echo signal transmission system based on FPGA simultaneously.)

1. A multi-channel radar echo signal transmission method based on an FPGA comprises the following steps:

operation S1: packaging the received radar echo data into different data packets and then sequentially outputting the data packets according to a set period;

operation S2: the different data packets are judged and then sequentially stored in different cache regions;

operation S3: monitoring the storage state of the data packet, changing the storage position according to the storage state, and simultaneously reading the data packet in the cache region which is stored completely; and

operation S4: the read data is converted into an optical signal and transmitted through an optical fiber.

2. The FPGA-based multi-channel radar echo signal transmitting method of claim 1, operation S1 including:

packing the radar echo data into a ping data packet and a pong data packet according to different initial addresses; and

and sequentially outputting the ping data packet and the pong data packet through a PCIe interface according to a set period.

3. The FPGA-based multi-channel radar echo signal transmitting method of claim 1, operation S2 including:

receiving the ping data packet and the pong data packet through corresponding PCIe interfaces;

judging the qualification of the ping data packet and the pong data packet through the FPGA; and

and respectively and sequentially storing the qualified ping data packet and the pong data packet in different buffer areas.

4. The FPGA-based multi-channel radar echo signal transmitting method of claim 1, operation S3 including:

when the storage of the ping data packet is monitored to be finished through the FPGA, the ping data packet which is stored into different buffer areas, and the ping data packet which is stored is read; and

and when the storage of the pong data packet is monitored to be finished through the FPGA, the ping data packet is stored into different buffer areas, and the pong data packet which is stored is read at the same time.

5. The FPGA-based multichannel radar echo signal transmission method according to claim 4, wherein whether the storage of the ping buffer area or the pong buffer area in the buffer area is completed is obtained by inquiring the state of a ping-pong flag register in the FPGA.

6. The FPGA-based multichannel radar echo signal transmission method of claim 1, wherein in operation S4, the data read according to the set period is transmitted through 4 optical fibers after being checked for correctness by the FPGA.

7. A multichannel radar echo signal transmission system based on FPGA comprises:

the upper computer is used for packaging the received radar echo data into different data packets and then sequentially outputting the data packets according to a set period;

the data cache unit is used for sequentially storing the different data packets in different cache regions after judgment;

one end of the FPGA unit is connected with the upper computer through a PCIe interface module, and the other end of the FPGA unit is connected with the data cache module and used for monitoring the storage state of the data packet, changing the storage position according to the storage state and simultaneously reading the data packet in the cache region which is stored completely; and

and the optical fiber unit is used for converting the data read by the FPGA unit into optical signals and transmitting the optical signals through optical fibers.

8. The FPGA-based multichannel radar echo signaling system of claim 7, the upper computer including:

the ping-pong switching module is used for switching between outputting the ping data packet and outputting the ping data packet;

the PRF setting module is used for setting a data output period; and

and the parameter query module is used for querying the state of the ping-pong flag register in the FPGA unit.

9. The FPGA-based multi-channel radar echo signaling system of claim 7, the FPGA unit comprising:

a power supply module;

the FPGA chip is used for judging the qualification of the ping data packet and the pong data packet, monitoring the storage state of the data packet, changing the storage position according to the storage state and simultaneously reading the data packet in the cache region after the storage is finished; and

and the clock management module is used for providing 100MHz and 125MHz differential clocks.

10. The FPGA-based multichannel radar echo signal transmission system of claim 7, the data buffer unit comprising a ping buffer and a pong buffer, each buffer comprising 4 DDR3 particles.

Technical Field

The disclosure relates to the technical field of radar signal processing, in particular to a multichannel transmission method and system based on an FPGA.

Background

The radar imaging technology is rapidly developed, the real-time imaging speed is faster and faster, and the real-time imaging precision is higher and higher, so that the radar imaging technology plays an increasingly important role in the fields of national defense, land surveying and mapping, weather forecasting and the like. In the development and application of radar real-time imaging algorithms, actually collected radar data needs to be input into a radar processing unit to verify the correctness of the algorithms. In addition, the imaging algorithm often needs to be iterated for many times to reach the final desired result, the flight test cannot be performed for the single verification algorithm in the actual project, and the time and the labor are consumed in doing so, so that the actually measured data acquired in the past by flight need to be transmitted to the processing unit through different interfaces to be processed, the algorithm verification time can be greatly shortened, and the project development efficiency is improved.

However, the conventional data transmission system has low transmission rate and unstable system performance, the device uses an old PCI protocol, and cannot be compatible with the latest computer interface, and the data transmission frequency is not controllable, so that the conventional data transmission system cannot transmit analog signals according to the required frequency, and cannot meet the requirements of the conventional radar signal processing.

Therefore, a radar signal transmission system which can realize multi-channel, high speed, wide application range and stability is needed.

Disclosure of Invention

Technical problem to be solved

Based on the above problems, the present disclosure provides a method and a system for transmitting a multi-channel radar echo signal based on an FPGA, so as to alleviate technical problems in the prior art, such as low data transmission rate of radar signals, uncontrollable data transmission frequency, and incompatible device interfaces.

(II) technical scheme

In one aspect of the present disclosure, a method for transmitting a multi-channel radar echo signal based on an FPGA is provided, which includes: operation S1: packaging the received radar echo data into different data packets and then sequentially outputting the data packets according to a set period; operation S2: the different data packets are judged and then sequentially stored in different cache regions; operation S3: monitoring the storage state of the data packet, changing the storage position according to the storage state, and simultaneously reading the data packet in the cache region which is stored completely; and operation S4: the read data is converted into an optical signal and transmitted through an optical fiber.

According to an embodiment of the present disclosure, operation S1 includes: packing the radar echo data into a ping data packet and a pong data packet according to different initial addresses; and sequentially outputting the ping data packet and the pong data packet through a PCIe interface according to a set period.

According to an embodiment of the present disclosure, operation S2 includes: receiving the ping data packet and the pong data packet through corresponding PCIe interfaces; judging the qualification of the ping data packet and the pong data packet through the FPGA; and respectively and sequentially storing the qualified ping data packet and the pong data packet in different buffer areas.

According to an embodiment of the present disclosure, operation S3 includes: when the storage of the ping data packet is monitored to be finished through the FPGA, the ping data packet which is stored into different buffer areas, and the ping data packet which is stored is read; and monitoring the storage completion of the pong data packet through the FPGA, and starting to store the ping data packet into different buffer areas and simultaneously read the pong data packet which is stored completely.

According to the embodiment of the disclosure, whether the storage of the ping buffer area or the pong buffer area in the buffer area is finished is obtained by inquiring the state of the ping-pong flag register in the FPGA.

According to the embodiment of the present disclosure, in operation S4, the data read according to the set period is transmitted through 4 optical fibers after being checked for correctness by the FPGA.

In another aspect of the present disclosure, a multichannel radar echo signal transmission system based on an FPGA is provided, including: the upper computer is used for packaging the received radar echo data into different data packets and then sequentially outputting the data packets according to a set period; the data cache unit is used for sequentially storing the different data packets in different cache regions after judgment; one end of the FPGA unit is connected with the upper computer through a PCIe interface module, and the other end of the FPGA unit is connected with the data cache module and used for monitoring the storage state of the data packet, changing the storage position according to the storage state and simultaneously reading the data packet in the cache region which is stored completely; and the optical fiber unit is used for converting the data read by the FPGA unit into optical signals and transmitting the optical signals through optical fibers.

According to this disclosed embodiment, the host computer includes: the ping-pong switching module is used for switching between outputting the ping data packet and outputting the ping data packet; the PRF setting module is used for setting a data output period; and the parameter query module is used for querying the state of the ping-pong flag register in the FPGA unit.

According to an embodiment of the present disclosure, the FPGA unit includes: a power supply module; the FPGA chip is used for judging the qualification of the ping data packet and the pong data packet, monitoring the storage state of the data packet, changing the storage position according to the storage state and simultaneously reading the data packet in the cache region after the storage is finished; and the clock management module is used for providing 100MHz and 125MHz differential clocks.

According to the embodiment of the disclosure, the data buffer unit comprises a ping buffer area and a pong buffer area, and each buffer area comprises 4 pieces of DDR3 particles.

(III) advantageous effects

According to the technical scheme, the method and the system for transmitting the multi-channel radar echo signals based on the FPGA have at least one or one part of the following beneficial effects:

(1) high-speed and multi-channel parallel data transmission can be realized;

(2) the method is suitable for computer equipment with PCIe slots, has better universality and wider application range, and can realize the high-speed data transmission function between the computer and the data processing board card;

(3) the reconfigurable hardware of the FPGA is easy to upgrade and develop for the second time, and can meet the requirements of different users.

Drawings

Fig. 1 is a flowchart of a method for transmitting a multi-channel radar echo signal based on an FPGA according to an embodiment of the present disclosure;

fig. 2 is a schematic diagram of a composition architecture of an FPGA-based multi-channel radar echo signal transmission system according to an embodiment of the present disclosure;

fig. 3 is a schematic clock supply diagram of an FPGA-based multi-channel radar echo signal transmission system according to an embodiment of the present disclosure.

Detailed Description

The utility model provides a multichannel radar echo signal transmission method and system based on FPGA, give full play to the nimble reconsitution of FPGA and high-speed parallel advantage, send the data that PC host computer transmitted to the cache of integrated circuit board through the PCIe interface on, reuse ping-pong operation to read the data to FPGA, then carry out the preliminary treatment through FPGA to the data, transmit the data that will process the completion through 4 optical fibers at last.

For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.

The technical scheme provided by the embodiment of the disclosure can realize high-speed and multi-channel parallel transmission of data, has good universality and improves the data transmission efficiency.

In an embodiment of the present disclosure, a method for transmitting a multi-channel radar echo signal based on an FPGA is provided, as shown in fig. 1, where the method includes:

operation S1: packaging the received radar echo data into different data packets and then sequentially outputting the data packets according to a set period;

operation S2: the different data packets are judged and then sequentially stored in different cache regions;

operation S3: monitoring the storage state of the data packet, changing the storage position according to the storage state, and simultaneously reading the data packet in the cache region which is stored completely; and

operation S4: the read data is converted into an optical signal and transmitted through an optical fiber.

According to the embodiment of the disclosure, in operation S1, the PC upper computer periodically transmits data to the FPGA through the PCIe interface, operation S2 indicates that the FPGA chip stores the data in the DDR3 in a ping-pong order after determining the correctness of the data, operation S3 indicates that the output of the FPGA monitoring data is completed, the ping-pong flag register is changed, the PC upper computer switches the start address to send different data packets after monitoring that the ping-pong flag register is changed, and the FPGA reads the data packets in the buffer area in which the storage is completed; operation S4 refers to converting the read data into optical signals through the optical fiber interface module and transmitting the optical signals through the optical fiber.

According to the embodiment of the present disclosure, in operation S1, a PRF setting module (for example, setting an arbitrary PRF value may be implemented by software) is disposed in the PC upper computer, and the PRF module is configured to set a period parameter when the received radar echo data is transmitted. And setting a period parameter of radar echo data to be transmitted and a data start address to be transmitted on an upper computer interface of the PC, and then packaging the data to generate a data packet.

According to the embodiment of the present disclosure, for example, if the starting address of the currently transmitted data is the address of ping, the data packet is the ping data packet, and can be stored in the corresponding ping buffer area; and if the transmitted data starting address is the pong address, the data packet is the pong data packet, and the data packet can be stored in a corresponding pong buffer area.

According to the embodiment of the disclosure, after a data packet is generated, for example, after a ping data packet is generated, the ping data packet is output through a PCIe interface according to a cycle parameter set by a PRF; in operation S2, the ping data packet is transmitted to the FPGA of the FPGA unit on the board, and after the FPGA chip determines the compliance and correctness of the ping data packet, the ping data packet is stored in a ping storage area of the data buffer unit (e.g., DDR 3).

According to the embodiment of the present disclosure, in operation S3, after the FPGA monitors that the transmission of the ping data packet is completed, the ping-pong flag register is negated; when the data packet is transmitted, the ping-pong flag register in the FPGA is inquired through the parameter inquiry module, when the change of the ping-pong flag register is monitored by the PC upper computer, the initial address of the data packet is switched, the next ping-pong data packet is generated and transmitted, and after the compliance and the correctness of the ping-pong data packet are judged by the FPGA chip, the ping-pong data packet is stored in a first buffer area (also called as a ping buffer area) in the data buffer unit. Similarly, while the ping-pong data packet is transmitted, the ping-pong flag register in the FPGA is inquired through the parameter inquiry module, when the FPGA monitors that the output of the ping-pong data packet is finished, the ping-pong flag register is inverted, and after the change of the ping-pong flag register is monitored by the PC upper computer, the initial address is switched to the initial address of ping, so that the data packet is alternately and circularly stored.

According to the embodiment of the present disclosure, in operation S3, for example, when the FPGA detects that the transmission of the ping data packet is completed, the ping flag register is inverted, and the ping data packet is stored, the FPGA starts to read the stored ping data packet, and starts to read data from the DDR3 first buffer memory of one frame according to the PRF period parameter set by the PRF. After checking the correctness of the data packet, the data packet is transmitted to the fiber interface of the fiber unit, and finally the data is transmitted through the 4-way fiber interface in operation S4. After the ping data packet is read, the FPGA switches the ping-pong address, the ping-pong data packet is read from a DDR3 second buffer area (also called a ping-pong buffer area), the data is also transmitted to the optical fiber interface after the correctness of the data is checked, and finally the data is transmitted out through 4 paths of optical fiber interfaces, so that the reading and the transmission are circulated.

According to the embodiment of the present disclosure, based on the same inventive concept, the present disclosure provides a multi-channel radar echo signal transmission system based on FPGA, referring to fig. 2, where the transmission system includes:

the upper computer is used for packaging the received radar echo data into different data packets and then sequentially outputting the data packets according to a set period;

the data cache unit is used for sequentially storing the different data packets in different cache regions after judgment;

one end of the FPGA unit is connected with the upper computer through a PCIe interface, and the other end of the FPGA unit is connected with the data cache module and used for monitoring the storage state of the data packet, changing the storage position according to the storage state and simultaneously reading the data packet in the cache region which is stored completely; and

and the optical fiber unit is used for converting the data read by the FPGA unit into optical signals and transmitting the optical signals through optical fibers.

According to the embodiment of the present disclosure, the PC upper computer may be a computer, including: the ping-pong switching module is used for switching between outputting the ping data packet and outputting the ping data packet; the PRF setting module is used for setting a data output period; and the parameter query module is used for querying the state of the ping-pong flag register in the FPGA.

The PCIE interface module is respectively positioned on the upper computer and the FPGA unit and is connected with PCIe slots on a mainboard of the PC upper computer and the FPGA unit through a PCIe x8 golden finger connector, so that the unidirectional transmission rate can reach 12 Gbps. The PCIE interface module needs to be inserted into a PCIe slot, so that the function of data exchange between the FPGA and the PC upper computer is realized.

The data cache unit comprises a first cache region and a second cache region, each cache region contains 4 pieces of DDR3 particles, the capacity of each piece of DDR3 particle is 512MB, and the total capacity is 4 GB.

The ping-pong switching module can perform separate operation on data reading and writing of the first buffer area and the second buffer area in the data buffer unit, so that switching between transmission of the ping data packet and transmission of the pong data packet is realized, for example, the ping data packet is read when the pong data packet is stored, and the ping data packet is read when the pong data packet is stored, so that the system transmission efficiency is improved.

The PRF setting module is a data sending mark generated by the PC upper computer periodically, sets a data output period, simulates a real radar transmitting period, and can adjust the size of the sending period according to different requirements.

And the parameter query module is used for querying the state of the ping-pong flag register in the FPGA unit.

The FPGA unit comprises: a power supply module; the FPGA chip is used for judging the qualification of the ping data packet and the pong data packet, monitoring the storage state of the data packet, changing the storage position according to the storage state and simultaneously reading the data packet in the cache region after the storage is finished; and the clock management module is used for providing 100MHz and 125MHz differential clocks.

One end of the FPGA unit is connected with the PC upper computer through a PCIe interface module, the other end of the FPGA unit is connected with the data cache module, the storage state of the data packet can be monitored, the storage position is changed according to the storage state, and meanwhile, the data packet in the cache region which is stored completely is read, for example, after the fact that the storage of the ping data packet is completed is monitored, the ping data packet which is stored completely is stored, and meanwhile, the ping data packet which is stored completely is read; the specific model of the FPGA chip in the FPGA unit selected in this embodiment is XC7K325TFFG 900-2.

The clock management module is composed of a differential crystal oscillator which provides 100MHz and 125MHz differential clocks and a PCIe interface module which provides 100MHz differential clocks. A100 MHz differential Clock generated by a Clock management module differential crystal oscillator is input to an MMCM (Mixed-Mode Clock Manager) module in the FPGA as a main Clock source, a 125MHz differential Clock generated by the differential crystal oscillator is input to a data cache unit and an optical fiber communication module in the FPGA as reference clocks, and a 100MHz differential Clock generated by a PCIe interface module is input to a PCIe communication module in the FPGA as reference clocks.

The optical fiber unit comprises a 4-channel optical fiber interface, can complete conversion from an electrical signal of data to an optical signal, and then transmits the converted signal through an optical fiber, and the optical fiber interface module can provide a data transmission rate of 20 Gbps.

So far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. It is to be noted that, in the attached drawings or in the description, the implementation modes not shown or described are all the modes known by the ordinary skilled person in the field of technology, and are not described in detail. Further, the above definitions of the various elements and methods are not limited to the various specific structures, shapes or arrangements of parts mentioned in the examples, which may be easily modified or substituted by those of ordinary skill in the art.

From the above description, those skilled in the art should have clear understanding of the present disclosure of a method and system for transmitting a multi-channel radar echo signal based on an FPGA.

In summary, the present disclosure provides a method and a system for transmitting a multi-channel radar echo signal based on an FPGA, which are based on an FPGA + PCIe structure, implement high-speed and multi-channel parallel data transmission, are suitable for a computer device with a PCIe slot, have good versatility and a wide application range, can implement a high-speed data transmission function between a computer and a data processing board, have a data transmission efficiency of 12Gbps, can meet high-speed data transmission under various bandwidth requirements, greatly improve the data transmission efficiency, and the FPGA reconfigurable hardware is easy to upgrade and develop secondarily, and can meet the requirements of different users.

It should also be noted that directional terms, such as "upper", "lower", "front", "rear", "left", "right", and the like, used in the embodiments are only directions referring to the drawings, and are not intended to limit the scope of the present disclosure. Throughout the drawings, like elements are represented by like or similar reference numerals. Conventional structures or constructions will be omitted when they may obscure the understanding of the present disclosure. And the shapes and sizes of the respective components in the drawings do not reflect actual sizes and proportions, but merely illustrate the contents of the embodiments of the present disclosure.

The use of ordinal numbers such as "first," "second," "third," etc., in the specification and claims to modify a corresponding element does not by itself connote any ordinal number of the element or any ordering of one element from another or the order of manufacture, and the use of the ordinal numbers is only used to distinguish one element having a certain name from another element having a same name.

In addition, unless steps are specifically described or must occur in sequence, the order of the steps is not limited to that listed above and may be changed or rearranged as desired by the desired design. The embodiments described above may be mixed and matched with each other or with other embodiments based on design and reliability considerations, i.e., technical features in different embodiments may be freely combined to form further embodiments.

The above-mentioned embodiments are intended to illustrate the objects, aspects and advantages of the present disclosure in further detail, and it should be understood that the above-mentioned embodiments are only illustrative of the present disclosure and are not intended to limit the present disclosure, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.