阅读说明：本技术 一种局部钝化接触的ibc电池结构及其制备方法 (Local passivation contact IBC battery structure and preparation method thereof ) 是由 邵玉林 王军 张三洋 于 2021-08-06 设计创作，主要内容包括：本发明公开了一种局部背面钝化接触的IBC太阳能电池,包括P型晶体硅基体,其背表面从内到外依次包括隧穿氧化层、交替排列的背表面n+掺杂多晶硅区域和背表面开槽处p+掺杂区域、背表面钝化膜和背表面金属电极；其前表面为金字塔绒面结构,依次为前表面钝化膜和减反射膜；P型晶体硅基体背表面的发射极区域采用隧穿氧化层以及n+掺杂多晶硅钝化层,表面采用氧化铝和氮化硅复合膜或氮氧化硅膜钝化,接受极区域采用局部硼掺杂,表面采用氧化铝和氮化硅复合膜或氮氧化硅膜钝化；本发明能避免正面电极对光线的阻挡,同时能大大降低电池背表面的复合速率,提升了开路电压和短路电流,进一步降低太阳能电池的制造成本。(The invention discloses an IBC solar cell with local back passivation contact, which comprises a P-type crystal silicon substrate, wherein the back surface of the P-type crystal silicon substrate sequentially comprises a tunneling oxide layer, alternately arranged back surface n + doped polycrystalline silicon regions, back surface slotted P + doped regions, a back surface passivation film and a back surface metal electrode from inside to outside; the front surface of the metal substrate is a pyramid suede structure and is sequentially provided with a front surface passivation film and an antireflection film; the emitter region of the back surface of the P-type crystal silicon substrate adopts a tunneling oxide layer and an n + doped polycrystalline silicon passivation layer, the surface of the P-type crystal silicon substrate is passivated by adopting an aluminum oxide and silicon nitride composite film or a silicon oxynitride film, the receiver region adopts local boron doping, and the surface of the P-type crystal silicon substrate is passivated by adopting an aluminum oxide and silicon nitride composite film or a silicon oxynitride film; the invention can avoid the obstruction of the front electrode to the light, greatly reduce the recombination rate of the back surface of the cell, improve the open-circuit voltage and the short-circuit current and further reduce the manufacturing cost of the solar cell.)

1. An IBC solar cell with a locally passivated back contact, comprising: the P-type crystal silicon substrate comprises a P-type crystal silicon substrate (100), wherein the back surface of the P-type crystal silicon substrate (100) sequentially comprises a tunneling oxide layer (200), alternately arranged back surface n + doped layers (300), back surface slotted P + doped regions (101), a back surface passivation film (503) and back surface metal electrodes from inside to outside; the front surface of the P-type crystalline silicon substrate (100) is of a pyramid textured structure, and a front passivation film (501) and a front antireflection film (502) are sequentially arranged from inside to outside;

the front side antireflection film (502) comprises SiO₂And/or Al₂O₃Dielectric film and SiNx dielectric film or SiOxNy, the SiO₂The thickness of the dielectric film is 1-5 nm, and the Al is₂O₃The thickness of the dielectric film is 2-20 nm, the thickness of the SiNx dielectric film is 40-100 nm, and the thickness of the SiOxNy dielectric film is 40-100 nm;

the tunneling oxide layer (200) and the n + doped layer (300) form an emitter region of the back surface of the P-type crystal silicon substrate, and the back surface passivation film (503) is an aluminum oxide and silicon nitride composite film or a silicon oxynitride film passivation film; the thickness of the tunneling oxide layer (200) is 1-3nm, the thickness of the n + doped layer (300) is 40-200nm, and the Al is₂O₃The thickness of the dielectric film is 2-20 nm, the thickness of the SiNx dielectric film is 40-100 nm, and the thickness of the SiOxNy dielectric film is 40-100 nm;

the receiving electrode area of the back surface of the P-type crystalline silicon substrate (100) is doped with local boron, the surface of the P-type crystalline silicon substrate is passivated by adopting an aluminum oxide and silicon nitride composite film or a silicon oxynitride film, and the Al is₂O₃The thickness of the dielectric film is 2-20 nm, the thickness of the SiNx dielectric film is 40-100 nm, and the thickness of the SiOxNy dielectric film is 40-100 nm.

2. The local backside passivated contacted IBC solar cell of claim 1, wherein: the front surface of the P-type crystal silicon substrate is a pyramid textured structure formed by alkali texturing.

3. The local backside passivated contacted IBC solar cell of claim 1, wherein: the back surface metal electrode comprises a first back surface electrode (601) in ohmic contact with the back surface n + doped layer (300) and a second back surface electrode (602) in ohmic contact with the p + doped region (101) at the groove of the back surface.

4. A method for preparing an IBC solar cell with a local back passivation contact is characterized by comprising the following steps:

s1, selecting a P-type crystal silicon substrate, carrying out double-sided polishing treatment, and removing a cutting damage layer;

s2, sequentially growing a tunneling oxide layer and an n + doped layer on the back of the P-type crystal silicon substrate, wherein the n + doped layer is doped polycrystalline silicon or doped amorphous silicon; growing an n + doped layer on the tunneling oxide layer by LPCVD (low pressure chemical vapor deposition) or PECVD (plasma enhanced chemical vapor deposition) equipment, wherein the thickness of the n + doped layer is 40-200 nm;

s3, printing a mask layer on the back surface of the P-type crystalline silicon substrate after the processing of S2, wherein the line width of the pattern is 200-2000um, and the line spacing is 100-500 um;

s4, injecting boron atoms into the back of the P-type crystalline silicon substrate after the treatment of S3 by adopting an ion injection method to form a P + doped region;

s5, performing wet etching on the p-type crystalline silicon substrate after the processing of S4, removing the n + doped layer and the tunneling oxide layer in the unmasked region, and forming insulation isolation of the p + doped region and the n + doped layer by wet chemical drilling and etching on the edge of the mask layer;

s6, carrying out wet cleaning on the P-type crystalline silicon substrate after the S5 treatment, removing the mask layer, then putting the substrate into an annealing furnace for high-temperature oxidation annealing, wherein the peak temperature of the oxidation annealing treatment is 800-₂And O₂Crystallizing the n + doped layer, annealing the ion-implanted p + region and forming a protective silicon oxide layer on the surface;

s7, performing single-sided texturing on the front surface of the P-type crystalline silicon substrate after the S6 treatment to form a textured surface, and removing the protective silicon oxide layer;

s8, growing a front surface passivation film and a front surface antireflection film on the front surface of the p-type crystal silicon substrate after the S7 treatment is completed; growing a back surface passivation film and a back surface antireflection film on the back surface of the p-type crystalline silicon substrate 100;

s9, printing a first back electrode on the n + doped region on the back of the P-type crystal silicon substrate after the processing of S8 by using silver paste, drying, and printing an electrode second back electrode on the laser grooving region of the P + region by using aluminum paste, and drying; or laser grooving is carried out on the n + doped region and the p + region, and copper metal electrodes are electroplated;

and S10, conveying the P-type crystalline silicon substrate after the S9 treatment to a sintering furnace for sintering, wherein the sintering peak temperature is 800-950 ℃ when silver paste printing and aluminum paste printing electrodes are adopted, and the sintering temperature is 500-700 ℃ when copper electroplating is adopted.

5. The method of claim 4, wherein the P-type crystalline silicon substrate 100 in S1 has a resistivity of 0.5-10 Ω cm and a thickness of 100-250 μm.

6. The method as claimed in claim 4, wherein the step of preparing the tunneling oxide layer in S2 comprises placing the P-type crystalline silicon substrate after S1 is completed in a high temperature furnace, introducing oxygen at a reaction temperature of 550-700 ℃, for a reaction time of 2-20min, at an oxygen flow rate of 500-5000sccm, and for a grown tunneling oxide layer 200 with a thickness of 1-3 nm.

7. The method of claim 4, wherein the front passivation film and the back passivation film are SiO in S8₂、Al₂O₃And one or more of SiOxNy dielectric films, wherein the front antireflection film is a silicon nitride antireflection film with the thickness of 50-90 nm; the back antireflection film is a silicon nitride antireflection film, and the thickness of the back antireflection film is 50-120 nm.

Technical Field

The invention relates to the technical field of solar cells, in particular to an IBC solar cell with local back passivation contact and a preparation method thereof.

Background

Solar cells are semiconductor devices that convert solar energy into electrical energy, and lower electricity consumption costs have been the goal of the solar cell industry. At present, the mainstream product in the industry is a P-type PERC crystalline silicon solar cell, and the efficiency of the P-type PERC crystalline silicon solar cell is close to the theoretical level of the structure, so that the efficiency improvement space is not large. The cell has simple process, and the p + doping area contact electrode and the n + doping area contact electrode are respectively positioned on the front side and the back side of the cell piece. The front surface of the cell is a light receiving surface, and the coverage of the front metal contact electrode can lead to the fact that a part of incident sunlight is shielded and reflected by the metal electrode, and a part of optical loss is caused. The coverage area of the front metal electrode of the common crystalline silicon solar cell is about 5%, and the energy conversion efficiency of the cell can be directly improved by reducing the front coverage of the metal electrode.

The back contact cell is a cell with a p + doped region and an n + doped region both arranged on the back (non-light-receiving surface) of the cell, and the light-receiving surface of the cell is not shielded by any metal electrode, so that the short-circuit current of the cell is effectively increased, and the energy conversion efficiency of the cell is improved.

The back surface of a common back contact cell is an N-type silicon substrate, a p + and an N + type doped layer, on which SiNx or SiO2/SiNx is generally used as a passivation layer, and then a fire-through silver paste is used to penetrate the passivation layer to form an ohmic contact with silicon. Wherein the back metal electrode occupies about 5% to 8% of the back surface area, which means that more than 5% of the area of the silicon surface is not covered by the passivation layer and severe metal recombination occurs in these areas.

Disclosure of Invention

In order to obtain high open-circuit voltage, short-circuit current and fill factor, we hope to develop a novel battery which can make good contact between the metal electrode and the silicon substrate, maintain the integrity of the passivation film and reduce the manufacturing cost of the back contact battery by combining the selective passivation contact technology of TOPCon and the heavily doped metal contact area mode.

In order to solve the technical problems, the invention provides the following technical scheme:

the IBC solar cell with local back passivation contact comprises a P-type crystal silicon substrate, wherein the back surface of the P-type crystal silicon substrate sequentially comprises a tunneling oxide layer, alternately arranged back surface n + doped polycrystalline silicon regions, back surface slotted P + doped regions, a back surface passivation film and back surface metal electrodes from inside to outside; the front surface of the P-type crystal silicon substrate is of a pyramid textured structure, and a front surface passivation film and an antireflection film are sequentially arranged from inside to outside;

the front surface of the P-type crystal silicon substrate is a pyramid textured structure formed by alkali texturing and front surface field passivation formed by a front surface passivation antireflection film; the front surface passivation antireflection film comprises a SiO2 and/or Al2O3 dielectric film and a SiNx dielectric film or SiOxNy, the thickness of the SiO2 dielectric film is 1-5 nm, the thickness of the Al2O3 dielectric film is 2-20 nm, the thickness of the SiNx dielectric film is 40-100 nm, and the thickness of the SiOxNy dielectric film is 40-100 nm.

The emitter region on the back surface of the P-type crystal silicon substrate adopts a tunneling oxide layer and an n + doped polycrystalline silicon passivation layer, and the surface of the emitter region is passivated by adopting an aluminum oxide and silicon nitride composite film or a silicon oxynitride film, so that the passivation contact of the emitter region is realized; the thickness of the tunneling oxide layer (SiO2) is 1-3nm, the thickness of the n + doped polycrystalline silicon layer is 40-200nm, the thickness of the Al2O3 dielectric film is 2-20 nm, the thickness of the SiNx dielectric film is 40-100 nm, and the thickness of the SiOxNy dielectric film is 40-100 nm.

The receiving electrode area of the back surface of the P-type crystal silicon substrate is doped with local boron, and the surface of the P-type crystal silicon substrate is passivated by adopting an aluminum oxide and silicon nitride composite film or a silicon oxynitride film, so that the low-ohmic contact and field passivation effects of the receiving electrode area are realized. The thickness of the Al2O3 dielectric film is 2-20 nm, the thickness of the SiNx dielectric film is 40-100 nm, and the thickness of the SiOxNy dielectric film is 40-100 nm.

Compared with the traditional TOPCON battery and IBC battery, the structure has the advantages of avoiding the blockage of the front electrode to light, greatly reducing the recombination rate of the back surface of the battery and improving the open-circuit voltage and short-circuit current; the back surface N area and the back surface P area can be metalized by applying a screen printing process to prepare electrodes or an electroplating process, the manufacturing cost of the solar cell is further reduced, the cost is reduced by more than 5%, and the efficiency of preventing light rays from being blocked by arranging the electrodes on the back surface of the cell can be improved by more than 0.5.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:

fig. 1 is a schematic cross-sectional view of the battery structure after S1;

fig. 2 is a schematic cross-sectional view of the battery structure after S2;

fig. 3 is a schematic cross-sectional view of the battery structure after S3;

fig. 4 is a schematic cross-sectional view of the battery structure after S4;

fig. 5 is a schematic cross-sectional view of the battery structure after S5;

fig. 6 is a schematic cross-sectional view of the battery structure after S6;

fig. 7 is a schematic cross-sectional view of the battery structure after S7;

fig. 8 is a schematic cross-sectional view of the battery structure after S8;

fig. 9 is a schematic cross-sectional view of the battery structure after S9.

Detailed Description

The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.

Examples

The IBC solar cell with local back passivation contact comprises a P-type crystalline silicon substrate 100, wherein the back surface of the P-type crystalline silicon substrate 100 sequentially comprises a tunneling oxide layer 200, alternately arranged back surface n + doped layers 300, back surface slotted P + doped regions 101, a back surface passivation film 503 and back surface metal electrodes from inside to outside; the front surface of the P-type crystal silicon substrate 100 is of a pyramid textured structure, and a front surface passivation film 501 and an antireflection film 502 are sequentially arranged from inside to outside;

the antireflection film 502 includes SiO₂And/or Al₂O₃Dielectric film and SiNx dielectric film or SiOxNy, the SiO₂The thickness of the dielectric film is 1-5 nm, and the Al is₂O₃The thickness of the dielectric film is 2-20 nm, the thickness of the SiNx dielectric film is 40-100 nm, and the thickness of the SiOxNy dielectric film is 40-100 nm;

the tunneling oxide layer 200 and the n + doped layer 300 form an emitter region of the back surface of the P-type crystalline silicon substrate, and the back surface passivation film 503 is an aluminum oxide and silicon nitride composite film or a silicon oxynitride film passivation film; the tunneling oxide layer 200 is 1-3nm thick, the n + doping layer 300 is 40-200nm thick, and the Al is₂O₃The thickness of the dielectric film is 2-20 nm, the thickness of the SiNx dielectric film is 40-100 nm, and the thickness of the SiOxNy dielectric film is 40-100 nm;

the receiving electrode area of the back surface of the P-type crystalline silicon substrate 100 adopts local boron doping, the surface is passivated by adopting an aluminum oxide and silicon nitride composite film or a silicon oxynitride film, and the Al₂O₃The thickness of the dielectric film is 2-20 nm, the thickness of the SiNx dielectric film is 40-100 nm, and the thickness of the SiOxNy dielectric film is 40-100 nm.

A method for preparing a back contact solar cell comprises the following steps:

s1, selecting a P-type crystalline silicon substrate 100, and performing double-sided polishing treatment on the P-type crystalline silicon substrate 100 to remove a cutting damage layer; the resistivity of the P-type crystalline silicon substrate 100 is 0.5-10 omega cm, and the thickness is 100-250 um; the cell structure after this step is completed is shown in fig. 1.

S2, growing a tunneling oxide layer 200 and an n + doped layer 300 on the back surface of the P-type crystalline silicon substrate 100, wherein the n + doped layer is doped polycrystalline silicon or doped amorphous silicon; the growth method of the tunnel oxide layer 200 may be a high temperature thermal oxidation method, an ozone oxidation method, a nitric acid oxidation method, or an ALD atomic layer deposition method, and the like, in this example, the high temperature thermal oxidation method is adopted, the P-type crystalline silicon substrate 100 after the S1 is completed is placed into a high temperature furnace tube, oxygen is introduced, the reaction temperature is 550-. Then growing an n + doped layer 300 with a thickness of 40-200nm on the tunneling oxide layer by LPCVD or PECVD equipment. The cell structure after this step is completed is shown in fig. 2.

S3, printing a mask layer 400 on the back surface of the P-type crystalline silicon substrate 100 after the processing of S2, wherein the line width of the pattern is 200-2000um, and the line spacing is 100-500 um. The cell structure after this step is completed is shown in fig. 3.

S4, implanting boron atoms into the back of the P-type crystalline silicon substrate 100 after the treatment of the S3 by adopting an ion implantation method to form a P + doped region 101; the cell structure after this step is completed is shown in fig. 4.

And S5, performing wet etching on the p-type crystalline silicon substrate 100 after the processing of the S4, removing the n + doped layer 300 and the tunneling oxide layer 200 in the unmasked region, and forming insulation isolation of the p + doped region 101 and the n + doped layer 300 by wet chemical etching on the edge of the mask layer 400. The cell structure after this step is completed is shown in fig. 5.

And S6, carrying out wet cleaning on the P-type crystalline silicon substrate 100 after the processing of the S5 is finished, removing the mask layer 400, and then putting the substrate into an annealing furnace for high-temperature oxidation annealing. The peak temperature of the oxidation annealing treatment is 800-1050 ℃, the annealing time is 20-120min, and the environment is N₂And O₂The crystallization of the n + doped layer 300, the annealing of the ion-implanted p + region 101, and the surface formation of the protective silicon oxide layer 201 are realized. The cell structure after this step is completed is shown in fig. 6.

S7, performing single-sided texturing on the front surface of the P-type crystalline silicon substrate 100 after the S6 treatment to form a textured surface, and removing the protective silicon oxide layer 201, wherein the cell structure after the step is completed is shown in FIG. 7.

S8, growing a front-side passivation film 501 and a front-side antireflection film 502 on the front surface of the p-type crystalline silicon substrate 100 after the S7 treatment is completed, wherein the front-side passivation film 501 can be SiO₂、Al₂O₃And SiOxNy dielectric film, the front anti-reflective film 502 may be a silicon nitride anti-reflective film with a thickness of 50-90 nm; growing a back surface passivation film 503 and a back surface antireflection film 504 on the back surface of the p-type crystalline silicon substrate 100, wherein the back surface passivation film 503 can be SiO2 or Al2O3, SiOxNy dielectric film, and the back side anti-reflective film 504 may be a silicon nitride anti-reflective film with a thickness of 50-120 nm. The cell structure after this step is completed is shown in fig. 8.

S9, printing and drying the first back electrode 601 on the back n + doped region 300 of the P-type crystalline silicon substrate 100 after the processing of S8 by using silver paste, and printing and drying the second back electrode 602 on the laser grooving region of the P + region 101 by using aluminum paste; or laser grooving and copper metal electrode electroplating are carried out on the n + doping area 300 and the p + doping area 101, and the structure of the battery after the step is completed is shown in fig. 9.

S10, conveying the P-type crystalline silicon substrate 100 after the S9 treatment to a sintering furnace for sintering, wherein the sintering peak temperature is 800-950 ℃ when silver and Al electrodes are printed, and the sintering temperature is 500-700 ℃ when copper electroplating is adopted. At this point, the fabrication of an IBC solar cell with a locally passivated back contact is completed.

The comparison of the test parameters of the prepared local passivation contact IBC battery and the conventional PERC and TOPCON batteries is shown in the following table, and the battery has the advantages of avoiding the blockage of the front electrode to light, greatly reducing the recombination rate of the back surface of the battery and improving the open-circuit voltage and short-circuit current; the back surface N area and the back surface P area can be metalized by adopting a screen printing process to prepare electrodes or an electroplating process, so that the manufacturing cost of the solar cell is further reduced.

The average electrical performance parameters of a plurality of battery pieces prepared by adopting the optimal process parameters of the palm tester are shown in the following table:

type of battery	NUM/number	VOC (open circuit Voltage)/V	ISC (short-circuit Current)/mA	FF (fill factor)/%)	Eta (cell efficiency)/%)
						Conventional PERC	797	0.689	9.963	81.87	23.08
Conventional topCON	784	0.708	10.089	82.43	23.82
						TBC	788	0.721	10.124	83.14	24.46

Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.