阅读说明：本技术 算术装置和乘法累加系统 (Arithmetic device and multiply-accumulate system ) 是由 吉田浩 于 2020-03-12 设计创作，主要内容包括：该算术装置设置有多个输入线对和一个或多个乘法累加计算设备。信号对在输入周期内输入到多个输入线对中。乘法累加设备包括多个乘法单元、累加单元、充电单元和输出单元。多个乘法单元基于信号对的各信号生成与正权重值的正权重乘积值相对应的正权重电荷和与负权重值的负权重乘积值相对应的负权重电荷。累加单元累积正权重电荷和负权重电荷。充电单元在输入周期之后对累加单元充电。在充电开始之后,输出单元使用预定阈值对累加单元的电压执行阈值确定,从而输出表示正权重乘积值之和的正乘法累加信号和表示负权重乘积值之和的负乘法累加信号。此外,在每个乘法累加设备中,在公共的充电模式下执行充电,并且使用预定阈值设置公共阈值。(The arithmetic device is provided with a plurality of input line pairs and one or more multiply-accumulate calculation devices. The signal pairs are input into a plurality of input line pairs during an input period. The multiply-accumulate apparatus includes a plurality of multiply units, an accumulate unit, a charge unit, and an output unit. The plurality of multiplication units generate, based on each signal of the signal pair, a positive weight charge corresponding to a positive weight product value of the positive weight values and a negative weight charge corresponding to a negative weight product value of the negative weight values. The accumulation unit accumulates the positive weight charges and the negative weight charges. The charging unit charges the accumulation unit after the input period. After the start of charging, the output unit performs threshold determination on the voltage of the accumulation unit using a predetermined threshold, thereby outputting a positive multiply-accumulate signal representing the sum of the positive weight product values and a negative multiply-accumulate signal representing the sum of the negative weight product values. Further, in each multiply-accumulate device, charging is performed in a common charging mode, and a common threshold value is set using a predetermined threshold value.)

1. An arithmetic device comprising:

a plurality of input line pairs to each of which a signal pair corresponding to an input value is input in a predetermined input period; and

one or more multiply-accumulate devices, each device comprising

A plurality of multiplication units that are respectively connected to at least some of the input line pairs and are capable of generating each of a positive weight charge and a negative weight charge, the positive weight charge corresponding to a positive weight product value obtained by multiplying a signal value of one signal of the signal pair input to the input line pair to which the multiplication units are connected by a positive weight value, the negative weight charge corresponding to a negative weight product value obtained by multiplying a signal value of the other signal by a negative weight value,

an accumulation unit capable of accumulating the positive weight charges and the negative weight charges generated by each of the plurality of multiplication units,

a charging unit that charges the accumulation unit, wherein a charge corresponding to a product value is accumulated after the input period, an

An output unit that performs threshold determination on the voltage held by the accumulation unit using a predetermined threshold after the start of charging by the charging unit, thereby outputting a positive multiply-accumulate signal representing the sum of the positive weight product values and a negative multiply-accumulate signal representing the sum of the negative weight product values, wherein

In one or more of the multiply-accumulate devices, the charging by the charging unit is performed in a common charging mode, and a common threshold value is set to the predetermined threshold value.

2. The arithmetic device of claim 1, wherein

The common charging mode includes charging according to a common time constant.

3. The arithmetic device of claim 1, wherein

The common charge mode includes charging based on a maximum sum value of a sum value of the sum values of the positive weight values and the absolute values of the negative weight values, the maximum sum value being the largest in the multiply-accumulate device or devices, the positive weight values and the negative weight values being set in a plurality of the multiplication units.

4. Arithmetic device according to claim 3, wherein

The common charging mode charges the accumulation unit according to the maximum sum value by a time constant.

5. The arithmetic device of claim 4, wherein

A plurality of the input line pairs supply a charging signal that enters an on-state after the input period, and

the charging unit charges the accumulation unit by accumulating the charges generated by the plurality of multiplication units based on the charging signal.

6. The arithmetic device of claim 4, wherein

The charging unit includes a resistor for charging and a charging line connected to the accumulation unit via the resistor for charging and supplying a charging signal that enters an on state after the input period.

7. The arithmetic device of claim 6, wherein

The resistor for charging is set to have a resistance value according to the maximum sum value.

8. The arithmetic device of claim 6, wherein

A plurality of the input line pairs enter an off state after the input period, and

the charging unit charges the accumulation unit by accumulating the charge generated by the resistor for charging based on the charging signal.

9. Arithmetic device according to claim 3, wherein

The common threshold is set based on the maximum sum value.

10. Arithmetic device according to claim 3, wherein

The common threshold is set based on a voltage curve representing a change over time of a voltage of the accumulation unit in a case where the accumulation unit is charged via a resistor having a resistance value according to the maximum sum value.

11. The arithmetic device of claim 1, wherein

For each of the plurality of multiplication units, the absolute values of the positive weight value and the negative weight value are set to the same value.

12. The arithmetic device of claim 1, wherein

The absolute values of the positive weight value and the negative weight value are fixed to the same value.

13. The arithmetic device of claim 1, wherein

The absolute values of the positive weight value and the negative weight value are set to any one of a plurality of values different from each other.

14. The arithmetic device of claim 1, wherein

One or more of the multiply-accumulate devices are a plurality of multiply-accumulate devices connected in parallel to a plurality of the input line pairs.

15. The arithmetic device of claim 14, wherein

Setting a sum value of the positive weight values and a sum value of the absolute values of the negative weight values to a common sum value equal to each other in the multiply-accumulate apparatus, and

a plurality of the multiply-accumulate devices include the common sum value set to the same value.

16. The arithmetic device of claim 14, wherein

Setting a sum value of the positive weight values and a sum value of the absolute values of the negative weight values to a common sum value equal to each other in the multiply-accumulate apparatus, and

the plurality of multiply-accumulate devices include a multiply-accumulate device including the common sum value different from each other.

17. The arithmetic device of claim 1, wherein

The input value is represented by the sum of a positive value and a negative value,

the signal pair includes a positive signal having the positive value as a signal value and a negative signal having an absolute value of the negative value as a signal value, and

the plurality of multiplication units include at least one of a first multiplication unit that generates the positive weight charge by multiplying the signal value of the positive signal by the positive weight value and generates the negative weight charge by multiplying the signal value of the negative signal by the negative weight value, or a second multiplication unit that generates the positive weight charge by multiplying the signal value of the negative signal by the positive weight value and generates the negative weight charge by multiplying the signal value of the positive signal by the negative weight value.

18. The arithmetic device of claim 17, wherein

A plurality of the input line pairs each include a positive input line to which the positive signal is input and a negative input line to which the negative signal is input,

one or more of the multiply-accumulate devices includes a positive charge output line and a negative charge output line,

the first multiplication unit includes a resistor connected between the positive input line and the positive charge output line, defining the positive weight value, and outputting the positive weight charge to the positive charge output line, and a resistor connected between the negative input line and the negative charge output line, defining the negative weight value, and outputting the negative weight charge to the negative charge output line, and

the second multiplication unit includes a resistor connected between the negative input line and the positive charge output line, defining the positive weight value, and outputting the positive weight charge to the positive charge output line, and a resistor connected between the positive input line and the negative charge output line, defining the negative weight value, and outputting the negative weight charge to the negative charge output line.

19. The arithmetic device of claim 18, wherein

The accumulation unit includes a positive charge accumulation unit connected to the positive charge output line and accumulating the positive weight charges and a negative charge accumulation unit connected to the negative charge output line and accumulating the negative weight charges,

the charging unit charges each of the positive charge accumulation unit and the negative charge accumulation unit, and

the output unit performs threshold determination on the positive charge accumulation unit using the common threshold value to output the positive multiply-accumulate signal, and performs threshold determination on the negative charge accumulation unit using the common threshold value to output the negative multiply-accumulate signal.

20. A multiply-accumulate system, comprising:

a plurality of input line pairs into each of which a signal pair corresponding to an input value is input in a predetermined input period;

a plurality of analog circuits, each analog circuit comprising

A plurality of multiplication units that are respectively connected to at least some of the input line pairs and are capable of generating each of a positive weight charge and a negative weight charge, the positive weight charge corresponding to a positive weight product value obtained by multiplying a signal value of one signal of the signal pair input to the input line pair to which the multiplication units are connected by a positive weight value, the negative weight charge corresponding to a negative weight product value obtained by multiplying a signal value of the other signal by a negative weight value,

an accumulation unit capable of accumulating the positive weight charges and the negative weight charges generated by each of the plurality of multiplication units,

a charging unit charging the accumulation unit, wherein a charge corresponding to a product value is accumulated after the input period, and

an output unit that performs threshold determination on the voltage held by the accumulation unit using a predetermined threshold after the charging is started by the charging unit, thereby outputting a positive multiply-accumulate signal representing the sum of the positive weight product values and a negative multiply-accumulate signal representing the sum of the negative weight product values; and

a network circuit configured by connecting a plurality of the analog circuits, wherein

In the plurality of analog circuits, the charging by the charging unit is performed in a common charging mode, and a common threshold is set to the predetermined threshold.

Technical Field

The present technology relates to an arithmetic device and a multiply-accumulate system that can be applied to multiply-accumulate operations using an analog method.

Background

Conventionally, techniques for performing multiply-accumulate operations have been developed. The multiply-accumulate operation is an operation of multiplying each of a plurality of input values by a weight and adding the multiplication results to each other, and is used for processing of recognizing an image, a voice, or the like, for example, by a neural network or the like.

For example, patent document 1 describes an analog circuit in which multiply-accumulate processing is performed in an analog manner. In the analog circuit, a weight corresponding to each of the plurality of electric signals is set. Further, the electric charges are individually output according to the corresponding electric signals and weights, and the output electric charges are appropriately accumulated in the capacitors. The value to be calculated representing the multiply-accumulate result is calculated based on the voltage of the capacitor in which the charge is accumulated. Therefore, power consumption required for multiply-accumulate operation can be reduced as compared with, for example, digital processing (paragraphs [0003], [0049] to [0053], [0062], fig. 3, and the like in the specification of patent document 1).

Reference list

Patent document

Patent document 1: WO 2018/034163

Disclosure of Invention

Technical problem to be solved by the invention

Use of such an analog type circuit is expected to realize low power consumption of a neural network or the like, and it is expected to provide a technique of simplifying a circuit configuration and realizing high-speed arithmetic operation processing.

In view of the above circumstances, an object of the present technology is to provide an arithmetic apparatus and a multiply-accumulate system by which a circuit configuration can be simplified and high-speed arithmetic operation processing can be realized.

Solution to the problem

To achieve the above object, an arithmetic apparatus according to an embodiment of the present technology includes a plurality of input line pairs and one or more multiply-accumulate devices.

A signal pair corresponding to the input value is input into each of the plurality of input line pairs within a predetermined input period.

Each of the one or more multiply-accumulate devices includes a plurality of multiply units, an accumulate unit, a charge unit, and an output unit.

The plurality of multiplication units are respectively connected to at least some of the input line pairs, and are capable of generating each of positive weight charges corresponding to a positive weight product value obtained by multiplying a signal value of one signal of the signal pair input to the input line pair to which the multiplication unit is connected by a positive weight value and negative weight charges corresponding to a negative weight product value obtained by multiplying a signal value of the other signal by a negative weight value.

The accumulation unit is capable of accumulating the positive weight charges and the negative weight charges generated by each of the plurality of multiplication units.

The charging unit charges the accumulation unit in which the charge corresponding to the product value is accumulated after the input period.

After the charging unit starts charging, the output unit performs threshold determination on the voltage held by the accumulation unit using a predetermined threshold, thereby outputting a positive multiply-accumulate signal representing the sum of the positive weight product values and a negative multiply-accumulate signal representing the sum of the negative weight product values.

Further, in the one or more multiply-accumulate devices, the charging by the charging unit is performed in a common charging mode, and the common threshold is set to a predetermined threshold.

In the arithmetic device, in one or more multiply-accumulate apparatuses, a positive weight charge and a negative weight charge are generated by multiplying respective signal values of a signal pair corresponding to an input value by positive and negative weight values, and are accumulated in an accumulation unit. The accumulation unit is charged by the charging unit and performs threshold determination on its voltage by using a predetermined threshold value, thereby outputting positive and negative multiply-accumulate signals. Therefore, a circuit or the like for integrating the arithmetic operation result into one signal can be omitted. Further, in the one or more multiply-accumulate devices, the charging by the charging unit is performed in a common charging mode, and a common threshold is used in the threshold determination. Therefore, the arithmetic operations of the respective multiply-accumulate apparatuses can be appropriately performed at the same timing. As a result, the circuit configuration can be simplified, and high-speed arithmetic operation processing can be realized.

The common charging mode may include charging according to a common time constant.

The common charging mode may include charging based on a maximum sum value of a sum value of positive weight values and a sum value of an absolute value of a negative weight value, the maximum sum value being the largest in the one or more multiply-accumulate devices, the positive weight values and the negative weight values being set in the plurality of multiplication units.

The common charging mode may charge the accumulation unit according to the maximum sum value by a time constant.

The plurality of input line pairs may supply a charging signal that enters a conductive state after an input period. In this case, the charging unit may charge the accumulation unit by accumulating the charges generated by the plurality of multiplication units based on the charging signal.

The charging unit may include a resistor for charging and a charging line connected to the accumulation unit via the resistor for charging and supplying a charging signal that enters a conductive state after an input period.

The resistor for charging may be set to have a resistance value according to a maximum sum value.

The plurality of input line pairs may enter an off state after an input period. In this case, the charging unit may charge the accumulation unit by accumulating the charge generated by the resistor for charging based on the charging signal.

The common threshold may be set based on the maximum sum value.

The common threshold value may be set based on a voltage curve representing a change over time of the voltage of the accumulation unit in a case where the accumulation unit is charged via a resistor having a resistance value according to a maximum sum value.

The absolute values of the positive weight value and the negative weight value may be set to the same value for each of the plurality of multiplication units.

The absolute values of the positive weight value and the negative weight value may be fixed to the same value.

The absolute values of the positive weight value and the negative weight value may be set to any one of a plurality of values different from each other.

The one or more multiply-accumulate devices may be a plurality of multiply-accumulate devices connected in parallel to the plurality of input line pairs.

In the multiply-accumulate device, the sum value of the positive weight values and the sum value of the absolute values of the negative weight values may be set to a common sum value equal to each other. In this case, the plurality of multiply-accumulate devices may include a common sum value set to the same value.

In the multiply-accumulate apparatus, the sum value of the positive weight values and the sum value of the absolute values of the negative weight values may be set to a common sum value equal to each other. In this case, the plurality of multiply-accumulate devices may include a multiply-accumulate device including common sum values different from each other.

The input value may be represented by the sum of a positive value and a negative value. In this case, the signal pair may include a positive signal having a positive value as the signal value and a negative signal having an absolute value as a negative value of the signal value. Further, the plurality of multiplication units may include at least one of a first multiplication unit that generates a positive weight charge by multiplying a signal value of a positive signal by a positive weight value and generates a negative weight charge by multiplying a signal value of a negative signal by a negative weight value; the second multiplication unit generates a positive weight charge by multiplying the signal value of the negative signal by the positive weight value, and generates a negative weight charge by multiplying the signal value of the positive signal by the negative weight value.

The plurality of input line pairs may each include a positive input line to which a positive signal is input and a negative input line to which a negative signal is input. In this case, the one or more multiply-accumulate devices may include a positive charge output line and a negative charge output line. Further, the first multiplication unit may include: a resistor connected between the positive input line and the positive charge output line and a resistor connected between the negative input line and the negative charge output line, the resistor defining a positive weight value and outputting a positive weight charge to the positive charge output line; a resistor connected between the negative input line and the negative charge output line, the resistor defining a negative weight value, and outputting the negative weight charge to the negative charge output line. Further, the second multiplication unit may include: a resistor connected between the negative input line and the positive charge output line, the resistor defining a positive weight value and outputting the positive weight charge to the positive charge output line; a resistor connected between the positive and negative charge output lines, the resistor defining a negative weight value, and outputting the negative weight charge to the negative charge output line.

The accumulation unit may include a positive charge accumulation unit connected to the positive charge output line and accumulating the positive weight charges and a negative charge accumulation unit connected to the negative charge output line and accumulating the negative weight charges. In this case, the charging unit may charge each of the positive charge accumulation unit and the negative charge accumulation unit. Further, the output unit may perform threshold determination on the positive charge accumulation unit using the common threshold value to output a positive multiply-accumulate signal, and perform threshold determination on the negative charge accumulation unit using the common threshold value to output a negative multiply-accumulate signal.

A multiply-accumulate system in accordance with embodiments of the present technology includes a plurality of input lines, a plurality of analog circuits, and a network circuit.

The plurality of analog circuits each include a plurality of multiplication units, accumulation units, charging units, and output units.

The network circuit is configured by connecting a plurality of analog circuits.

Further, in the plurality of analog circuits, the charging by the charging unit is performed in a common charging mode, and the common threshold is set to a predetermined threshold.

Drawings

Fig. 1 is a schematic diagram showing a configuration example of an arithmetic device according to an embodiment of the present technology.

Fig. 2 is a schematic diagram showing an example of a pair of signals to be input into an analog circuit.

Fig. 3 is a schematic diagram showing a specific configuration example of the arithmetic device.

Fig. 4 is a schematic diagram showing a configuration example of a neuron circuit.

Fig. 5 is a schematic circuit diagram showing an example of an analog circuit according to the present embodiment.

Fig. 6 is a schematic diagram showing an example of a signal pair.

Fig. 7 is a schematic circuit diagram showing an example of the configuration of a synapse circuit.

Fig. 8 is a diagram for describing a calculation example of the multiply-accumulate signal of the analog circuit shown in fig. 5.

Fig. 9 is a schematic diagram showing an example of positive and negative multiply-accumulate signals.

Fig. 10 is a schematic diagram showing an example of connection between analog circuits of layers.

Fig. 11 is a schematic diagram showing an example of a change in voltage held by a capacitor with time.

Fig. 12 is a circuit diagram showing a configuration example of an arithmetic device.

Fig. 13 is a circuit diagram showing a configuration example of an arithmetic device.

Fig. 14 is a circuit diagram showing a configuration example of an arithmetic device.

Fig. 15 is a circuit diagram showing a configuration example of an arithmetic device.

Detailed Description

Hereinafter, embodiments according to the present technology will be described with reference to the drawings.

[ configuration of arithmetic device ]

Fig. 1 is a schematic diagram showing a configuration example of an arithmetic device according to an embodiment of the present technology. The arithmetic device 100 is an analog type arithmetic device, and performs predetermined arithmetic processing including multiply-accumulate operations. By using the arithmetic device 100, for example, arithmetic processing can be performed according to a mathematical model such as a neural network.

The arithmetic device 100 includes a plurality of signal lines 1, a plurality of input units 2, and a plurality of analog circuits 3. Each of the signal lines 1 is a line that transmits a predetermined type of electric signal. For example, an analog signal representing a signal value by using analog quantities such as pulse timing and pulse width is used as an electric signal. The direction in which the electrical signals are transmitted is schematically shown by the arrows in fig. 1.

As shown in fig. 1, the signal line 1 includes a positive signal line 1a and a negative signal line 1 b. Each of the positive signal lines 1a and each of the negative signal lines 1b are wired in pairs and used as a pair of signal lines 1. In the following description, a pair of signal lines 1 composed of a positive signal line 1a and a negative signal line 1b is described as a signal line pair P1. It should be noted in fig. 1 that the positive signal line 1a is a signal line 1 connected to a connection point that is a white circle, and the negative signal line 1b is a signal line 1 connected to a connection point that is a black circle.

The signal line pair P1 transmits a signal pair corresponding to an input value (or an output value). The signal pair is a pair of electric signals input into the positive signal line 1a and the negative signal line 1b, respectively. Each signal value of the pair of electrical signals represents an input value. That is, it can be said that the signal line pair P1 functions as a transmission path for transmitting an input value.

The input value x being a positive value x⁺And negative value x^-And the sum of them. Here, a positive value x⁺Is a real number (x) of 0 or more⁺Not less than 0). In addition, negative values x^-Is a real number (x) of 0 or less^-Less than or equal to 0). Thus, the input value x is represented by x ═ x⁺+x^-Expressed as positive values x⁺And negative value x^-And (4) summing. Here, a negative value x is used^-In the case of the absolute value of (a), the input value x is represented by x ═ x⁺-|x^-| is expressed as a positive value x⁺And negative valuex^-The difference between the absolute values of (a) and (b). Thus, the input value x may be represented using a difference between two positive real numbers.

In this embodiment, the signal pair includes a positive signal and a negative signal. The positive signal having a positive value x⁺An electric signal as a signal value, and is input into the positive signal line 1 a. The negative signal having a negative value x^-Absolute value of (2 | x)^-I is an electric signal as a signal value, and is input into the negative signal line 1 b. Therefore, both the positive signal and the negative signal included in the signal pair become electric signals representing positive real numbers.

As described above, in this embodiment, the input value x represented by the signal pair is the signal value (positive value x) of the positive signal input to the positive signal line 1a⁺) And the signal value (negative value x) of the negative signal inputted to the negative signal line 1b^-) The difference between them. In other words, a positive signal and a negative signal (signal pair) are generated such that a value obtained by subtracting a signal value of the negative signal from a signal value of the positive signal is an input value x. Specific waveforms and the like of the signal pairs will be described in detail later with reference to fig. 2.

As shown in fig. 1, a plurality of signal line pairs P1 are connected to one analog circuit 3. The signal line pair P1 for transmitting a signal pair to the analog circuit 3 is an input signal line pair (input signal line pair), and the signal pair is input to the input signal line pair, and is used for connecting the analog circuit 3 of the signal line pair P1. The signal line pair P1 carrying the signal pair output from the analog circuit 3 is an output signal line pair (output signal line pair) from which a signal pair is output, and is used for connecting the analog circuit 3 of the signal line pair P1. In this embodiment, the input signal line pair corresponds to the input line pair.

The plurality of input units 2 each generate a signal pair corresponding to a value (input value x) of the input data 4. The input data 4 is, for example, data to be processed using a neural network or the like implemented by the arithmetic device 100. Therefore, it can also be said that each signal value of the plurality of electric signals corresponding to the input data 4 is an input value to the arithmetic device 100. Further, it can also be said that the signal pair is an input pair.

For example, arbitrary data such as image data, audio data, and statistical data to be processed by the arithmetic device 100 is used as the input data 4. For example, in the case where image data is used as the input data 4, a signal pair corresponding to a pixel value (RGB value, luminance value, or the like) of each pixel of the image data as a signal value is generated. Further, the signal pair corresponding to the input data 4 may be appropriately generated according to the type of the input data 4 and the content of the processing performed by the arithmetic device 100.

The analog circuit 3 is an analog circuit that performs a multiply-accumulate operation based on a plurality of input signal pairs. The multiply-accumulate operation is, for example, an operation of adding a plurality of product values obtained by multiplying a plurality of input values by weight values corresponding to the input values. Therefore, it can also be said that the multiply-accumulate operation is a process of calculating the sum of product values (hereinafter, referred to as a multiply-accumulate result). In this embodiment, the analog circuit 3 corresponds to a multiply-accumulate device.

As shown in fig. 1, a plurality of input signal line pairs are connected to one analog circuit 3, and a plurality of signal pairs are supplied thereto. The plurality of input signal line pairs and the analog circuit 3 constitute a multiply-accumulate operation circuit according to this embodiment. Further, a plurality of signal pairs are input from each input signal line pair, and thus the multiply-accumulate method according to this embodiment is performed by the multiply-accumulate operation circuit (analog circuit 3).

Hereinafter, assuming that the total number of signal pairs (input signal line pairs) input into one analog circuit 3 is N, in this case, the total number of input signal lines connected to the analog circuit 3 is 2 × N, it should be noted that the number N of signal pairs input into each analog circuit 3 is appropriately set for each circuit in accordance with, for example, a model of arithmetic processing, accuracy, and the like.

In the analog circuit 3, for example, w is calculated_i*x_i，w_i*x_iIs an input value x represented by a signal pair input from the ith input signal line pair_iAnd corresponds to the input value x_iWeight value w of_iThe product value of (c). Here, i represents a natural number equal to or less than N (i ═ 1, 2.., N).

In the multiply-accumulate operation using the signal pair, the positive signal input to the positive signal line 1a isSignal value (positive value x)_i ⁺) And the signal value of the negative signal (negative value x) input to the negative signal line 1a_i ^-) Each of which is multiplied by a respective weight value and two product values are determined. Two product values may be used to represent the input value x_iAnd a weight value w_iThe product value w of_i*x_i. Hereinafter, this will be described in detail.

Performing a product value w for each signal pair (input signal line pair)_i*x_iAnd calculating N product values. By multiplying N product values w_i*x_iThe value obtained by the addition is calculated as a multiply-accumulate result (sum of N product values). Therefore, the multiply-accumulate result calculated by one analog circuit 3 is represented by the following expression.

[ equation 1]

Weight value w_iFor example, is set at-alpha ≦ w_iThe range of not more than + alpha. Here, α represents an arbitrary real value. Thus, the weight value w_iMay include a positive weight value w_iA negative weight value w_iZero weight value w_iAnd the like. By weighting the values w as described above_iThe setting is within a predetermined range, so that the situation where the multiply-accumulate result diverges can be avoided.

Further, for example, a weight value w may be set therein_iThe range of (a) is normalized. In this case, the weight value w_iIs set to be equal to or less than-1 and less than w_iLess than or equal to 1. Therefore, for example, the maximum value, the minimum value, or the like of the multiply-accumulate result can be adjusted, and the multiply-accumulate operation can be performed with desired accuracy.

In a neural network or the like, a method called binary concatenation which weights values w_iSet to + α or- α. Binary concatenation is used in various fields, such as image recognition using a deep neural network (multilayer neural network). The use of binary concatenation may simplify the weight value w_iWithout deteriorating the recognition accuracy and the like. In binary concatenation, the absolute values of the positive and negative weight values are fixed to the same value.

As described above, in binary concatenation, the weight value w_iIs binarized into binary values (± α). Thus, for example, by weighting the values w_iChanging to positive or negative, a desired weight value w can be easily set_i. Alternatively, the binarized weight values w may be compared_iNormalized and the weight value w can be_iSet to ± 1.

In addition, the weight value w_iMay be multivalued. In this case, the weight value w is set by selecting from a plurality of discrete weight value candidates_i. Examples of weight value candidates include (-3, -2, -1, 0, 1,2, 3) and (1, 2, 5, 10). Further, normalized weight value candidates (-1, -0.5, 0, 0.5, 1), or the like may be used. One value is selected from these weight value candidates and set as the weight value w_i. The number of weight value candidates, the method of setting the candidate value, and the like are not limited. By applying a weight value w_iThe multivalued structure can construct, for example, a neural network having high versatility.

In addition, the weight value w_iThe setting range, the setting value, and the like of (a) are not limited and may be appropriately set so that a desired processing accuracy is achieved, for example.

Input value x shown in expression (formula 1)_iIs, for example, the value of the input data 4 output from the input unit 2 and the value of the multiply-accumulate result output from the analog circuit 3. Thus, it can also be said that the input unit 2 and the analog circuit 3 serve for outputting the input value x_iThe signal source of (1).

As shown in fig. 1, in this embodiment, the input value x is output and output from one signal source (input unit 2, analog circuit 3) via a signal line pair P1_iA corresponding pair of electrical signals (signal pair). That is, the same signal pair is input into each signal line pair P1 connected to the output side of one signal source. In addition, a signal source and an analog circuit 3 to which an electric signal outputted from the signal source is inputted are connected through a single lineThe signal line pair P1 (input signal line pair) are connected to each other.

Thus, for example, M pairs of input signal lines are connected to the analog circuit 3, and the analog circuit 3 is connected to M signal sources in the arithmetic device 100 shown in fig. 1. In this case, the total number N of signal pairs input to the analog circuit 3 is N ═ M. It should be noted that the total number of electric signals input to the analog circuit 3, that is, the total number of signal lines 1 connected to the input side is 2 × M.

As shown in fig. 1, the arithmetic device 100 has a layer structure in which a plurality of analog circuits 3 are provided in each of a plurality of layers. By configuring the layer structure of the analog circuit 3, for example, a multilayer perceptron (MLP) type neural network or the like is constructed. The number of analog circuits provided in each layer, the number of layers, and the like are appropriately designed so that, for example, desired processing can be performed. Hereinafter, the number of analog circuits 3 provided in the j-th layer may be referred to as N_j。

For example, N signal pairs generated by N input units 2 are input into each analog circuit 3 provided in a layer (the lowest layer) of the first stage. The analog circuit 3 of the first stage calculates and inputs the input value x of the data_iThe multiplication-accumulation result of the correlation, and outputs the calculated multiplication-accumulation result to the analog circuit 3 provided in the next layer (second stage) after the nonlinear conversion process.

N representing respective multiply-accumulate results calculated in the first stage₁The signal pairs are input into the respective analog circuits 3 provided in the second layer (upper layer). Therefore, from the viewpoint of the analog circuit 3 of the second stage, the result of the nonlinear conversion processing of the respective multiply-accumulate results calculated in the first stage is the input value x of the signal pair_i. The analog circuit 3 of the second stage calculates the input value x output from the first stage_iAnd outputs the calculated multiply-accumulate result to the analog circuit 3 of the upper layer.

In this way, in the arithmetic device 100, the multiply-accumulate result of the analog circuit 3 in the upper layer is calculated based on the multiply-accumulate result calculated by the analog circuit 3 in the lower layer. Such processing is performed a plurality of times, and the processing result is output from the analog circuit 3 included in the top layer (the layer of the third stage in fig. 1). Thus, for example, processing such as image recognition to determine that the object is a cat based on image data (input data 4) obtained by imaging a cat may be performed.

As described above, by appropriately connecting a plurality of analog circuits 3, a desired network circuit can be configured. The network circuit functions as a data stream processing system that performs arithmetic processing by, for example, passing a signal therethrough. In the network circuit, various processing functions can be realized by appropriately setting, for example, a weight value (synaptic connection). With this network circuit, the multiply-accumulate system according to this embodiment is constructed.

It should be noted that a method or the like of connecting the analog circuits 3 to each other is not limited, and, for example, a plurality of analog circuits 3 may be appropriately connected to each other so that desired processing can be performed. For example, even in the case where the analog circuits 3 are connected to each other to configure another structure different from the layer structure, the present technology can be applied.

In the above description, the configuration in which the multiply-accumulate result calculated in the lower layer is input to the upper layer as it is has been described. The present technology is not limited to this, and for example, conversion processing or the like may be performed on the multiply-accumulate result. For example, in the neural network model, a process of performing nonlinear conversion on the multiply-accumulate result of each analog circuit 3 by using an activation function, for example, and inputting the conversion result to an upper layer is performed.

In the arithmetic device 100, for example, a functional circuit 5 or the like that performs nonlinear conversion on a signal pair using an activation function is used. The functional circuit 5 is, for example, a circuit provided between a lower layer and an upper layer, and it inputs a value x of an input signal pair_i(signal values of the respective electric signals) are appropriately converted, and a signal pair is output according to the conversion result. For example, the functional circuit 5 is provided for each signal line 1. The number of the functional circuits 5, the arrangement of the functional circuits 5, and the like are appropriately set according to, for example, a mathematical model implemented in the arithmetic device 100.

For example, a ReLU function (ramp function) or the like is used as the activation function. ReLThe U function being, for example, at an input value x represented by a signal pair_iThe signal pair is output as it is in the case of 0 or more. Otherwise, the ReLU function outputs a signal pair corresponding to 0 (an electrical signal pair whose signal value is 0). For example, a functional circuit 5 that implements the ReLU function is appropriately connected to each of the signal line pairs P1. Thus, the processing of the arithmetic device 100 can be realized.

Fig. 2 is a schematic diagram showing an example of a pair of signals input into an analog circuit. As shown in fig. 2A and B, diagrams representing waveforms of a pair of electric signals (signal pair) are schematically shown. IN fig. 2A (fig. 2B), the upper diagram shows an electric signal (positive signal IN) input to the positive signal line 1a⁺) The waveform of (2). The lower diagram shows an electric signal (negative signal IN) input to the negative signal line 1b^-) The waveform of (2). The horizontal axis of the graph indicates a time axis, and the vertical axis indicates the voltage of the electric signal.

In fig. 2, an exemplary waveform of an electric signal of a spike timing method (hereinafter referred to as a TACT method) is shown. The TACT method is a method of representing a signal value by using the rising timing of a pulse, for example. For example, by using a predetermined timing as a reference, a pulse is input at a timing corresponding to a signal value.

Each of the electric signals is inputted to the analog circuit 3 for a predetermined input period T, and the signal value is represented by the input timing of the pulse in the input period T. The pulse input at the same time as the start of the input period T represents the maximum signal value. The pulse input simultaneously with the end of the input period T represents the minimum signal value.

It can also be said that the signal value is represented by the duration from the input timing of the pulse to the end timing of the input period T. For example, a pulse having a duration from the input timing of the pulse to the end timing of the input period T equal to the input period T represents the maximum signal value. A pulse having a duration of 0 from the input timing of the pulse to the end timing of the input period T represents the minimum signal value.

As shown IN FIG. 2A, the ith signal pair includes a positive signal IN_i ⁺And a negative signal IN_i ^-. IN the TACT method, the positive signal IN_i ⁺Is in and as its creditPositive value x of number_i ⁺The pulsed electrical signal is input at a corresponding timing. IN addition, a negative signal IN_i ^-Is at a negative value x as its signal value_i ^-Absolute value of (2 | x)_i ^-The electrical signal of the pulse is input at a timing corresponding to | l.

Input value x of a signal pair_iFrom positive values x_i ⁺And a negative value x_i ^-Absolute value of (2 | x)_i ^-The difference between | is expressed. Thus, the value x is input_iIs derived from a positive signal IN_i ⁺Minus the negative signal IN_i ^-The input timing of the pulse of (1). As described above, in the signal pair according to the TACT method, the value x is input_iRepresented by the difference between the input timings of the pulses input to the positive signal line 1a and the negative signal line 1 b.

It should be noted that, in fig. 2A, according to the TACT method, continuous pulse signals that rise to a timing corresponding to an input value and hold an on level until a multiplication accumulation result is obtained are used as electric signals (positive and negative signals). The present technology is not limited thereto, and according to the TACT method, a rectangular pulse or the like having a predetermined pulse width may be used as the electric signal.

In the case of using the electric signal according to the TACT method, a time axis analog multiply-accumulate operation using the analog circuit 3 according to the TACT method can be performed.

An exemplary waveform of the electric signal according to a Pulse Width Modulation (PWM) method is shown in fig. 2B. The PWM method is a method of expressing a signal value by using a pulse width of a pulse waveform, for example. That is, in the PWM method, the pulse width of the electric signal is a length corresponding to the signal value. In general, longer pulse widths indicate larger signal values.

Further, the electric signal is inputted to the analog circuit 3 for a predetermined input period T. More specifically, the respective electric signals are input into the analog circuit 3 so that the pulse waveforms of the electric signals fall within the input period T. Therefore, the maximum value of the pulse width of the electric signal is similar to the input period T. It should be noted that the timing or the like of inputting each pulse waveform (electric signal) is not limited as long as the pulse waveform falls within the input period T.

In the PWM method, for example, the signal value may be normalized by using a duty ratio R (═ τ/T) between the pulse width τ and the input period T. That is, the signal value expressed as normalized is the duty ratio R. It should be noted that a method or the like for making the signal value correspond to the pulse width τ is not limited, and for example, the pulse width τ representing the signal value may be appropriately set so that arithmetic processing or the like can be performed with desired accuracy.

As shown IN FIG. 2B, IN the PWM method, a positive signal IN_i ⁺Is a signal having a positive value x as its signal value_i ⁺Corresponding pulse width electrical signal. IN addition, a negative signal IN_i ^-Is of a negative value x with as its signal value_i ^-Absolute value of (2 | x)_i ^-I corresponding to the pulse width. It should be noted that the positive signal IN is input_i ⁺And a negative signal IN_i ^-May deviate from each other.

Furthermore, the input value x of the signal pair_iIs derived from the negative signal IN_i ^-Is subtracted by the positive signal IN_i ⁺The pulse width of (a). Therefore, in the signal pair according to the PWM method, the value x is input_iBy the electric signal (positive signal IN) inputted to the positive signal line 1a and the negative signal line 1b_i ⁺And a negative signal IN_i ^-) Is expressed as the difference between the pulse widths of (a).

In the case of using the electric signal according to the PWM method, a time axis analog multiply-accumulate operation using the analog circuit 3 according to the PWM method can be performed.

As shown in fig. 2A and B, a pulse signal corresponding to an input value with respect to the on duration of the input period T may be used as the electric signal corresponding to the input value. It should be noted that in the following, it will be assumed that the signal value x is represented by each electrical signal_iThe description is for variables of 0 or greater and 1 or less.

Fig. 3 is a schematic diagram showing a specific configuration example of the arithmetic device 100. Fig. 3 is an example of arrangement of a circuit for realizing the arithmetic device 100 shown in fig. 1, for example, and schematically shows a plurality of analog circuits 3 provided in one layer of the arithmetic device 100. A plurality of input signal line pairs P6 are each connected to each analog circuit 3.

And the input value x_iThe corresponding signal pairs are input to the plurality of input signal line pairs P6 for a predetermined input period T. For example, during the input period T, a signal pair according to the TACT method or the PWM method described with reference to fig. 2 is input into each of the input signal line pairs P6.

Each input signal line pair P6 has a positive input signal line 6a and a negative input signal line 6 b. The positive input signal line 6a is a signal line 1 to which a positive signal is input, and the negative input signal line 6b is a signal line to which a negative signal is input. In this embodiment, the positive input signal line 6a corresponds to a positive input line, and the negative input signal line 6b corresponds to a negative input line.

Each analog circuit 3 includes a pair of output lines 7, a plurality of synaptic circuits 8, and a neuron circuit 9. As shown in fig. 3, one analog circuit 3 is configured to extend in a predetermined direction (vertical direction in the drawing). A plurality of such analog circuits 3 extending in the vertical direction are arranged side by side in the horizontal direction, thereby forming one layer. Hereinafter, it is assumed that the analog circuit 3 disposed on the leftmost side in the figure is the first analog circuit 3. Further, the direction in which the analog circuit 3 extends is sometimes referred to as an extending direction.

The pair of output wires 7 are spaced apart from each other along the extending direction. The pair of output lines 7 includes a positive charge output line 7a and a negative charge output line 7 b. Each of the positive charge output line 7a and the negative charge output line 7b is connected to a neuron circuit 9 via a plurality of synapse circuits 8.

The plurality of synapse circuits 8 are arranged corresponding to the plurality of input signal line pairs P6, respectively. An input signal line pair P6 is connected to a synaptic electrical circuit 8. The number of synapse circuits 8 arranged in one analog circuit 3 is set equal to or smaller than the number of pairs of input signal lines P6, for example. That is, the synaptic electrical circuit 8 need not be connected to all of the pairs of input signal lines P6.

In this way, the plurality of synapse circuits 8 are respectively connected to at least some of the plurality of pairs of input signal lines P6. For example, by using a mathematical model, simulation, or the like mounted on the arithmetic device 100, the pair of input signal lines P6 (i.e., the arrangement of the synapse circuit 8) connected with the synapse circuit 8 is appropriately selected.

The synaptic electrical circuit 8 calculates an input value x represented by a signal pair_iAnd weight value w_iValue of (w)_i*x_i). More specifically, the product value (w)_i*x_i) By comparing each signal value (positive value x) of the positive signal and the negative signal included in the signal pair_i ⁺And negative value x_i ^-Absolute value of (2 | x)_i ^-|) by the corresponding weight value.

Positive weight value v_i ⁺And a negative weight value v_i ^-Each being arranged to a plurality of synaptic electrical circuits 8. Here, the positive weight value v_i ⁺Is a positive real number (v)_i ⁺>0). In addition, a negative weight value v_i ^-Is a negative real number (v)_i ^-<0). Therefore, it can be said that the synaptic electrical circuit 8 is one in which a positive weight value v is set_i ⁺And a negative weight value v_i ^-The weight pair of (2).

The synaptic electrical circuit 8 calculates the signal value and the positive weight value v of one of the electrical signals included in the signal pair_i ⁺The product value of (c). In addition, the synaptic electrical circuit 8 calculates a signal value and a negative weight value v of another electrical signal_i ^-The product value of (c). Specifically, the synaptic electrical circuit 8 generates a charge (current) corresponding to each product value.

As to be associated with a positive weight value v_i ⁺The electrical signal of the multiplied object is appropriately set for each synaptic electrical circuit 8. Further, it is not set to the positive weight value v_i ⁺The electric signal of the target is to be matched with a negative weight value v_i ^-The target of the multiplication. In the following description, the positive weight value v_i ⁺The product value of (d) will be referred to as a positive weight product value, and the charge corresponding to the positive weight product value will be referred to as a positive weight charge. In addition, a negative weight value v_i ⁺The product value of (d) will be referred to as a negative weight product value, and the charge corresponding to the negative weight product value will be referred to as a negative weight charge.

As described above, the synaptic electrical circuit 8 is capable of generating a positive weight charge and a negative weight charge, the positive weight charge corresponding to a signal value of one signal of a signal pair inputted into the connected input signal line pair P6 by multiplying the signal value by a positive weight value v_i ⁺A positive weight product value obtained by multiplying the signal value of the other signal by a negative weight value v_i ^-And the resulting negative weight product value.

It should be noted that in the synaptic electrical circuit 8, the weight value w is not critical_iWhether positive or negative, a charge (e.g., positive charge) having the same sign is output as a charge corresponding to the product value. That is, the positive weight charges and the negative weight charges become charges having the same sign. Thus, in practical circuits, for example, a negative weight value v may be considered_i ^-Absolute value of | vi^-I is multiplied as a negative weight value v_i ^-. Since the positive and negative weight values can be handled as values having the same sign in this way, the circuit configuration can be simplified.

In this embodiment, for each of the plurality of synaptic electrical circuits 8, a positive weight value v_i ⁺And a negative weight value v_i ^-Absolute value of | vi^-| is set to the same value. In particular, a positive weight value v_i ⁺And a negative weight value v_i ^-Absolute value of | vi^-All are set to the weight value w_iAbsolute value of | w_iThe same value. I.e. each weight satisfies | w_i|＝v_i ⁺＝|v_i ^-The relationship of | is given. Hereinafter, the weight value w_iWill sometimes be referred to as pair weight values w_i。

In the synaptic electrical circuit 8, the pair weight value w will be a positive value_i ⁺Or as a negative value_i ^-Is set as a pair weight value w_i. By appropriately pairing signals (positive and negative signals) with weights (positive)Weight value) to set a positive weight value w_i ⁺And a negative pair weight value w_i ^-. In the following, a positive weight value w is set therein_i ⁺Will be referred to as positive synaptic circuit 8a, and a negative pair weight value w is set therein_i ^-Will be referred to as negative synaptic circuit 8 b.

The positive synapse circuit 8a passes the signal value (x) of the positive signal_i ⁺) Multiplying by a positive weight value v_i ⁺Generating positive weight charges and generating negative weight charges by multiplying the signal value (| x) of the negative signal_i ^-|) multiplied by a negative weight value | v_i ^-Generating negative weight charges. Therefore, the positive weight charge and the negative weight charge are respectively the product values (v) of the positive weight and the negative weight_i ⁺*x_i ⁺) And negative weight product value (| v)_i ^-|*|x_i ^-|) corresponding charge.

In this example, the difference Δ between the positive and negative weight product values⁺As shown below.

Δ⁺＝v_i ⁺*x_i ⁺-|v_i ^-|*|x_i ^-|＝|w_i|(x_i ⁺+x_i ^-)＝w_i ⁺*x_i

Thus, the difference Δ⁺Is just opposite to the weight value w_i ⁺And the input value x_iThe product value w of_i ⁺*x_i. That is, in the positive synapse circuit 8a, the product value w_i ⁺*x_iIs calculated as the difference between the positive and negative weight charges. In this embodiment, the positive synapse circuit 8a corresponds to a first multiplication unit.

The negative synapse circuit 8b is controlled by comparing the signal value (| x) of the negative signal_i ^-|) multiplied by a positive weight value v_i ⁺Generating positive weight charges and generating positive weight charges by multiplying the signal value (x) of the positive signal_i ⁺) Multiplying by a negative weight charge | v_i ^-Generating a negative weight value. Thus, positively and negatively weighted chargesAre respectively the product values (| v) with positive weights_i ^-|*x_i ⁺) And a negative weight product value (v)_i ⁺*|x_i ^-|) corresponding charge.

In this example, the difference Δ between the positive and negative weight product values^-As shown below.

Δ^-＝|v_i ^-|*x_i ⁺-v_i ⁺*|x_i ^-|＝-|w_i|(x_i ⁺+x_i ^-)＝w_i ^-*x_i

Thus, the difference Δ^-Is a negative pair weight value w_i ^-And the input value x_iThe product value w of_i ^-*x_i. That is, in the negative synaptic electrical circuit 8b, the product value w_i ^-*x_iIs calculated as the difference between the positive and negative weight charges. In this embodiment, the negative synapse circuit 8b corresponds to a second multiplication unit.

It should be noted that the positive weight charges corresponding to the positive weight product value are output to the positive charge output line 7a, and the negative weight charges corresponding to the negative weight product value are output to the negative charge output line 7 b. Hereinafter, a specific configuration of the synapse circuit 8 will be described in detail.

In this embodiment, a pair of input signal lines 6 (input signal line pair 6P) and a pair of output lines 7 are connected to a single synaptic electrical circuit 8. That is, a signal pair is input into a single synaptic electrical circuit 8 and according to a pair weight value w_iOutputs electric charges corresponding to the product value calculated based on each electric signal to either one of the output lines 7a or 7 b. Therefore, the synaptic electrical circuit 8 is a dual-input dual-output circuit.

In one analog circuit 3, a plurality of synaptic circuits 8 are arranged along a pair of output lines 7. Each synaptic circuit 8 is connected in parallel with a positive charge output line 7a (negative charge output line 7 b). Hereinafter, it is assumed that the synaptic circuit 8 arranged on the most downstream side (the side connected to the neuron circuit 9) is the first synaptic circuit 8.

As shown in fig. 3, a plurality of input signal line pairs 6 are wired to intersect a pair of output lines 7 of each of the plurality of analog circuits 3. Typically, each input signal line 6 is arranged orthogonal to each output line 7. That is, the arithmetic device 100 has a crossbar configuration in which the input signal line 6 and the output line 7 cross each other. With the crossbar configuration, the analog circuit 3 and the like can be integrated with high density, for example.

Further, in the arithmetic device 100, the jth synaptic circuit 8 included in each analog circuit 3 is connected in parallel with the jth pair of input signal lines P6. Thus, similar signal pairs are input into the synaptic electrical circuit 8 connected to the same input signal line pair P6. Accordingly, a configuration can be realized in which one signal source included in the lower layer is connected to a plurality of analog circuits 3 included in the upper layer.

It should be noted that, in the example shown in fig. 3, the analog circuit 3 (anterior neuron) included in the lower layer is schematically shown as a signal source which inputs a signal pair into each input signal line pair P6. The present technology is not limited to this, and for example, in the case where the input unit 2 is used as a signal source, a cross bar configuration may also be used.

As described above, in the arithmetic device 100, the plurality of analog circuits 3 are connected in parallel with each of the plurality of pairs of input signal lines P6. Thus, for example, it is possible to input a signal pair in parallel into each analog circuit 3 (each synapse circuit 8) and to realize arithmetic processing at high speed. As a result, excellent operation performance can be exhibited.

The neuron circuit 9 calculates a multiply-accumulate result shown by expression (formula 1) based on the product value calculated by the synapse circuit 8. Specifically, the neuron element circuit 9 outputs an electric signal (multiply-accumulate signal) representing a multiply-accumulate result based on the electric charges input via the pair of output lines 7.

Fig. 4 is a schematic diagram showing a configuration example of the neuron element circuit 9. The neuron element circuit 9 includes an accumulation unit 11 and a signal output unit 12. Fig. 4 shows a two-input two-output neuron circuit 9 connected to a pair of output lines 7 and a pair of output signal lines 10 (a positive output signal line 10a and a negative output signal line 10 b). It should be noted that, in some cases, a two-input single-output circuit or the like may be used as the neuron circuit 9.

The accumulation unit 11 accumulates the electric charges output to the pair of output lines 7 by the plurality of synapse circuits 8. The accumulation unit 11 includes two capacitors 13a and 13 b. The capacitor 13a is connected between the positive charge output line 7a and GND. Further, a capacitor 13b is connected between the negative charge output line 7b and GND. It should be noted that the capacitors 13a and 13b are set to have the same capacitance.

Therefore, the positive weight charges flowing from the positive charge output line 7a are accumulated in the capacitor 13 a. Further, the negative weight charges flowing from the negative charge output line 7b are accumulated in the capacitor 13 b. In this way, the accumulation unit 11 can accumulate the positive weight charge and the negative weight charge generated by each of the plurality of synapse circuits 8. In this embodiment, the capacitor 13a corresponds to a positive charge accumulation unit that is connected to a positive charge output line and accumulates positive weight charges, and the capacitor 13b corresponds to a negative charge accumulation unit that is connected to a negative charge output line and accumulates negative weight charges.

For example, at the timing at which the input period T of the electric signal ends, the electric charge accumulated in the capacitor 13a is the sum of positive weight charges each corresponding to a positive weight value v set in each synaptic electrical circuit 8_i ⁺Positive weight product value of. Further, the electric charge accumulated in the capacitor 13b is the sum of negative weight electric charges corresponding to a negative weight value v set in each synaptic circuit 8_i ^-Negative weight product value of (1).

For example, when positive weight charges are accumulated in the capacitor 13a, the potential of the positive charge output line 7a with reference to GND increases. Therefore, the potential of the positive charge output line 7a depends on the positive weight values v each corresponding to_i ⁺The value of the sum of the positive weight charges of the product value of (b). It should be noted that the potential of the positive charge output line 7a corresponds to the voltage held by the capacitor 13 a.

Similarly, in the case where negative weight charges are accumulated in the capacitor 13b, the potential of the negative charge output line 7b with reference to GND increases. Therefore, the potential of the negative charge output line 7b depends on the potentials each corresponding to the negative weight value v_i ^-The value of the sum of the negative weight charges of the product value of (b). It should be noted that the potential of the negative charge output line 7b corresponds to the voltage held by the capacitor 13 b.

The signal output unit 12 outputs a product value (w) representing the product based on the electric charges accumulated in the accumulation unit 11_i ⁺*x_i) The sum of which multiply accumulates the signal. In this embodiment, a positive multiply-accumulate signal representing the sum of positive-weight product values and a negative multiply-accumulate signal representing the sum of negative-weight product values are each taken as the product value (w)_i ⁺*x_i) The sum of which is multiplied by the accumulated signal to output.

Here, the total number of synapse circuits 8 set in the analog circuit 3 is N, and further, a positive weight value w is set therein_i ⁺The total number of synaptic electrical circuits 8 (positive weight pairs) of the N synaptic electrical circuits 8 is N⁺And wherein a negative pair weight value w is set_i ^-The total number of synaptic electrical circuits 8 (negative weight pairs) of (N) is defined as^-To indicate. Thus, N ═ N⁺+N^-. In this case, the multiply-accumulate result expressed by the expression (formula 1) can be written as follows.

[ formula 2]

As described above, in the case of using a signal pair, the value x is input_iIs expressed as a positive value x_i ⁺And a negative value x_i ^-Absolute value of (2 | x)_i ^-Sum between | (x)_i＝x_i ⁺-|x_i ^-| to a difference value. Therefore, the expression (formula 2) can be rewritten as follows.

[ formula 3]

As shown in expression (equation 3), the multiply-accumulate result is a value obtained by subtracting the second term from the first term. Here, each of the first item and the second item is an item enclosed by braces { }.

The first term is by setting a positive weight value w therein_i ⁺Positive weighted product value (w) calculated by synaptic electrical circuit 8 of_i ⁺*x_i(+) and a negative pair weight value w set therein_i ^-Positive weighted product value (| w) calculated by the synaptic electrical circuit 8 of_i ^-|*|x_i ^-|) the value of the sum. That is, the first term is the sum σ of the positive weight product values computed by all synaptic electrical circuits 8⁺. The sum of the positive-weight product values is represented by the sum of the positive-weight charges accumulated in the capacitor 13 a.

The second term is obtained by setting a positive weight value w_i ⁺The synaptic electrical circuit 8 of (a) calculates a negative weighted product value (w)_i ⁺*|x_i ^-|) and a negative pair weight value w set therein_i ^-The synaptic electrical circuit 8 of (a) calculates a negative weighted product value (| w)_i ^-|*x_i ⁺) The value of the sum. That is, the second term is the sum σ of the negative weight product values computed by all synaptic electrical circuits 8^-. The sum of the negative-weight product values is represented by the sum of the negative-weight charges accumulated in the capacitor 13 b.

In this manner, the total multiply-accumulate result may be calculated as the sum of the positive weight product values, σ⁺Sum of product values sigma of negative weights^-The difference between them.

It should be noted that the first term (sum of positive weight product values σ) of the expression (formula 3)⁺) Does not correspond to N⁺Individual positive weighted value w_i ⁺The second term (sum of negative weight product values σ) of the expression (formula 3)^-) Does not correspond to N^-Individual negative pair weight value w_i ^-The result is accumulated by multiplication.

In the example shown in fig. 4, the signal output unit 12 calculates a positive multiply-accumulate signal representing the sum of the positive weight product values by referring to the electric charge accumulated in the capacitor 13a, and calculates a negative multiply-accumulate signal representing the sum of the negative weight product values by referring to the electric charge accumulated in the capacitor 13 b.

At the timing at which the input period T ends, electric charges corresponding to the sum of the positive weight product values (the sum of the negative weight product values) are accumulated in the capacitor 13a (13 b). The same applies to the case where the TACT method or the PWM method is used.

As will be described later, in this embodiment, when the input period T has elapsed, the capacitor 13a and the capacitor 13b are charged. For example, the electric charge (current) output from each synaptic circuit is used to charge each of the capacitors 13a and 13 b. In this case, each synapse circuit 8 connected to the plurality of input signal line pairs P6 functions as a charging unit 15, which charging unit 15 charges the accumulation unit 11 in which a charge corresponding to the product value is accumulated after the input period T. It should be noted that a dedicated wiring (charging unit) or the like for charging each of the capacitors 13a and 13b may be provided.

For example, after the input period T, the charging unit 15 charges each of the capacitor 13a and the capacitor 13 b. At this time, the timing at which the potential of the output line connecting the capacitor 13a or the capacitor 13b reaches a predetermined threshold potential is detected by using a comparator or the like.

For example, as more electric charges are accumulated at the start of charging, the timing at which the potential reaches the threshold potential becomes earlier. Therefore, the electric charge accumulated during the input period T (multiply-accumulate result) can be expressed based on the timing. The signal output unit 12 performs threshold determination with respect to each of the capacitors 13a and 13b, generates each of a positive multiply-accumulate signal and a negative multiply-accumulate signal, and outputs it to a pair of output signal lines 10.

In this way, after the charging unit 15 starts charging, the signal output unit performs threshold determination using a predetermined threshold on the voltage held in the accumulation unit 11, thereby outputting a positive multiply-accumulate signal representing the sum of positive weight product values and a negative multiply-accumulate signal representing the sum of negative weight product values. In this embodiment, the signal output unit 12 corresponds to an output unit.

Fig. 5 is a schematic circuit diagram showing an example of the analog circuit 3 according to the embodiment. The analog circuit 3 is provided to extend in a direction orthogonal to the plurality of input signal line pairs P6. That is, in the example shown in fig. 5, a crossbar configuration is employed.

The analog circuit 3 includes a pair of output lines (a positive charge output line 7a and a negative charge output line 7b), a plurality of synapse circuits 8, and neuron circuits 9. The neuron element circuit 9 includes an accumulation unit 11 and a signal output unit 12.

In the example shown in fig. 5, four pairs of input signal lines P6 are connected to the analog circuit 3. The number of input signal line pairs P6, etc. is not limited. Each signal pair is input into each input signal line pair P6. These signal pairs comprise their input values x_iFor negative signal pairs or input values x thereof_iA positive signal pair. I.e. positive and negative input values x_iIs transmitted by each signal pair. Hereinafter, a pair of signals according to the TACT method will be mainly described.

Fig. 6 is a schematic diagram showing an example of a signal pair. Fig. 6A and 6B schematically show graphs each representing an exemplary waveform of a signal pair according to the TACT method.

In the analog circuit 3, the output period T is set after the input period T. Normally, the output period T starts from the end timing of the input period T. Further, the duration of the output period T is set equal to the duration of the input period T. Hereinafter, the start timing of the input period T will be T₀To indicate that the end timing of the input period T will be T_nTo indicate. In addition, the end timing of the output period T will be T_mAnd (4) showing. It should be noted that the end timing T of the input period T_nIs the start timing of the output period T.

FIG. 6A is a graph of the input value x_iIs an example of a positive signal pair (positive signal pair). At the input value x_iIN the case of positive, as a positive signal IN_i ⁺Positive value x of the signal value of_i ⁺Greater than as a negative signal IN_i ^-Negative value x of the signal value of_i ^-Absolute value of (2 | x)_i ^-L. Hereinafter, assume that in a positive signal pair, the value x is input_iMay be 0. I.e., in the positive signal pair, x_i ⁺≥|x_i ^-I holds.

IN the positive signal pairs according to the TACT method, the positive signal IN is present IN the input period T_i ⁺Input timing (x) of the pulse of (2)_i ⁺) Before negative signal IN_i ^-Input timing (x) of the pulse of (2)_i ^-) Therefore, the positive signal pair according to the TACT method is defined as a pair IN which the positive signal IN is present_i ⁺Input timing of not less than negative signal IN_i ^-The pair of signals whose input timings are established.

FIG. 6B is a graph showing the input value x_iAn example of a negative signal pair (negative signal pair). At the input value x_iIN the negative case, as the positive signal IN_i ⁺Positive value x of the signal value of_i ⁺Less than as a negative signal IN_i ^-Negative value x of the signal value of_i ^-Absolute value of (2 | x)_i ^-L. I.e. in the negative signal pair, x_i ⁺<|x_i ^-I holds.

IN the negative signal pair according to the TACT method, the positive signal IN is supplied during the input period T_i ⁺Input timing (x) of the pulse of (2)_i ⁺) Slower than the negative signal IN_i ^-Timing of input of pulses (| x)_i ^-|) according to the TACT method, a negative signal pair is therefore defined IN which the positive signal IN is present_i ⁺Input timing of<Negative signal IN_i ^-The pair of signals whose input timings are established.

In the example shown in fig. 5, a positive signal pair is input into the first and third input signal line pairs P6 from the top of the figure. In addition, the negative signal pair is also input into the second and fourth input signal line pairs P6. It should be noted that the input signal line pair P6 to which the positive signal pair and the negative signal pair are input changes in accordance with input data, for example, in each operation.

Further, as shown in fig. 6A and 6B, after the input period T is ended, the positive-negative signal pair is also maintained in the on state. That is, each of the electric signals included in the signal pair is also input at the input cycleEnd timing T of period T_nAnd thereafter maintains a predetermined signal voltage. The on state continues, for example, until the end timing T of the output period T_m. The output period T has the same duration as the input period T.

Each electrical signal enters an on state in the output period T, so that electric charges (current) are supplied to the pair of output lines 7 via the synapse circuit 8 (resistor 17). Therefore, the accumulation unit 11 (the capacitor 13a and the capacitor 13b) is charged during the output period T.

It should be noted that the present technique is not limited to the signal according to the TACT method, and a signal according to the PWM method (refer to 2B in fig. 3) may be used. In this case, even in the case where the electric signals are input so that the electric signals having the respective pulse widths are input in the input period T, and all the input signal lines 6 are held in the on state in the output period T, the electric charges corresponding to the multiplication-accumulation result can be accumulated in the input period T, and thereafter the capacitor 13 can be charged.

Returning to FIG. 5, a positive charge output line 7a is connected to each synaptic electrical circuit 8 and outputs a positive signal or a negative signal by multiplying the signal value of the signal by a positive weight value v_i ⁺And the obtained positive weight product value corresponds to the positive weight charge. Similarly, a negative charge output line 7b is connected to each synaptic circuit 8 and outputs a signal value obtained by multiplying a positive signal or a negative signal by a negative weight value v_i ^-Absolute value of | vi^-And | obtaining a negative weight product value corresponding to the negative weight charge.

The plurality of synaptic electrical circuits 8 are arranged in association with a plurality of pairs of input signal lines P6, respectively. In the example shown in FIG. 5, four synaptic electrical circuits 8 are provided for four pairs of input signal lines P6.

Each synaptic electrical circuit 8 is provided with two resistors 17. The two resistors 17 each serve as a weight for multiplying the weight value. The synaptic electrical circuit 8 is thus a weight pair that multiplies the signal pair by a weight value.

It should be noted that fig. 5 schematically shows a parasitic capacitance derived from each input signal line 6 and a parasitic capacitance derived from each output line 7, and each parasitic capacitance is, for example, a capacitance generated between each wiring and GND or the like.

The plurality of synaptic electrical circuits 8 includes at least one of a positive synaptic electrical circuit 8a and a negative synaptic electrical circuit 8 b. Therefore, the synaptic circuits 8 arranged in one analog circuit 3 may all be positive synaptic circuits 8a, or may all be negative synaptic circuits 8 b. Of course, the analog circuit 3 may be configured to include both positive and negative synaptic circuits 8a and 8 b. In the example shown in FIG. 5, the first and second positive synaptic electrical circuits 8a are disposed from the top, and the third and fourth negative synaptic electrical circuits 8b are disposed from the top.

Fig. 7 is a schematic circuit diagram showing a configuration example of the synapse circuit 8. Fig. 7A and 7B schematically show circuit diagrams of the positive synaptic electrical circuit 8a and the negative synaptic electrical circuit 8B. It should be noted that illustration of the parasitic capacitance is omitted in fig. 7.

The positive synapse circuit 8a is one in which a positive weight value w is set_i ⁺And is a positive weight pair. As shown in FIG. 7A, the positive synaptic electrical circuit 8a includes a first resistor 17A and a second resistor 17 b.

A first resistor 17a is connected between the positive input signal line 6a and the positive charge output line 7a, defining a positive weight v_i ⁺And outputs the positive weight charge to the positive charge output line 7 a. For example, a positive signal input to the positive input signal line 6a is output as positive weight charge to the positive charge output line 7a through the first resistor 17 a. The first resistor 17a serves as a positive weight for generating a positive weight charge.

A second resistor 17b is connected between the negative input signal line 6b and the negative charge output line 7b, defining a negative weight v_i ^-And outputs the negative weight charges to the negative charge output line 7 b. For example, a negative signal input to the negative input signal line 6b is output as negative weight charge to the negative charge output line 7b through the first resistor 17 b. The second resistor 17b serves as a negative weight for generating a positive weight charge.

Therefore, to convert the signal value x of a signal pair_iMultiplying by a positive weight value w_i ⁺A positive input signal line 6a and a positive charge output line 7a are connected to each other via a resistor, and a negative inputThe in signal line 6b and the negative charge output line 7b are connected to each other via a resistor. Thus, it can be said that in the positive synaptic electrical circuit 8a (positive weight pair), the positive signal (positive input) corresponds to a positive weight, and the negative signal (negative input) corresponds to a negative weight.

The negative synapse circuit 8b is one in which a negative pair weight value w is set_i ^-And is a negative weight pair. As shown in FIG. 7B, the negative synaptic electrical circuit 8B includes a third resistor 17c and a fourth resistor 17 d.

A third resistor 17c is connected between the negative input signal line 6b and the positive charge output line 7a, defining a positive weight v_i ⁺And outputs the positive weight charge to the positive charge output line 7 a. For example, a negative signal input to the negative input signal line 6b is output as positive weight charge to the positive charge output line 7a through the third resistor 17 c. The third resistor 17c serves as a positive weight for generating a positive weight charge.

A fourth resistor 17d is connected between the positive input signal line 6a and the negative charge output line 7b, defining a negative weight v_i ^-And outputs the negative weight charges to the negative charge output line 7 b. For example, a positive signal input to the positive input signal line 6a is output as negative weight charge to the negative charge output line 7b through the fourth resistor 17 d. The fourth resistor 17d serves as a negative weight for generating positive weight charges.

Therefore, to convert the signal value x of a signal pair_iMultiplying by a negative pair weight value w_i ^-The negative input signal line 6b and the positive charge output line 7a are connected to each other via a resistor, and the positive input signal line 6a and the negative charge output line 7b are connected to each other via a resistor. Thus, it can be said that in the negative synaptic electrical circuit 8b (negative weight pair), the positive signal (positive input) corresponds to the negative weight, and the negative signal (negative input) corresponds to the positive weight.

In this embodiment, in one synaptic electrical circuit 8, the resistors 17 used as the positive and negative weights are set to have the same conductance (or resistance value). For example, according to a pair weight value w set in the synaptic electrical circuit 8_iIs suitably set. For example, in the case where a constant voltage is applied to the resistor 17, the current (charge) generated by the resistor 17 and the electricityThe conductance is proportional (inversely proportional to the resistance value). Thus, for example, the conductance of the resistor 17 is set to be proportional to the weight value set in the resistor 17.

Therefore, it is possible to equalize the magnitudes of the positive weight value and the negative weight value, and to appropriately perform the multiply-accumulate operation. It should be noted that the resistance value may be different or the same for each synaptic electrical circuit 8.

For example, a fixed resistor element, a variable resistor element, a MOS transistor operating in a sub-threshold region, or the like is used as the resistor 17(17a to 17d, or the like). For example, by using a MOS transistor operating in a subthreshold region as the resistor 17, power consumption can be reduced. Of course, another arbitrary resistor may be used. Further, the resistor 17 may have a nonlinear characteristic, or may have a reverse current blocking function.

The accumulation unit 11 accumulates each of the positive weight charge and the negative weight charge generated in the input period T by each synapse circuit 8. Therefore, it can also be said that the accumulation unit 11 performs an operation of positive weight product value addition and an operation of negative weight product value addition. The accumulation unit 11 includes a capacitor 13a and a capacitor 13 b.

The capacitor 13a is connected between the positive charge output line 7a and GND. The positive weight charge generated by the positive weight (the first resistor 17a or the third resistor 17c) of each synaptic electrical circuit 8 is accumulated in the capacitor 13 a. The capacitor 13b is connected between the negative charge output line 7b and GND. The negative weight charge generated by the negative weight (the second resistor 17b or the fourth resistor 17d) of each synaptic electrical circuit 8 is accumulated in the capacitor 13 b.

Further, when the input period T ends and the output period T starts, the capacitors 13a and 13b are charged by the charging unit 15 (the plurality of synapse circuits 8). Therefore, the voltage held by each of the capacitors 13a and 13b continuously increases during the output period T.

The signal output unit 12 performs threshold determination on the voltage of the charged accumulation unit 11 (capacitors 13a and 13b), thereby outputting each of the positive and negative multiply-accumulate signals. In this embodiment, two comparators 20a and 20b are used as the signal output unit 12.

The comparator 20a detects the timing at which the voltage held by the capacitor 13a exceeds the predetermined threshold θ 1. It should be noted that the magnitude of the voltage held by the capacitor 13a is determined by the total amount of positive weight electric charges accumulated in the capacitor 13a and the amount of electric charges.

The comparator 20b detects the timing at which the voltage held by the capacitor 13b exceeds the predetermined threshold θ 2. It should be noted that the magnitude of the voltage held by the capacitor 13b is determined by the total amount of the negative weight electric charges accumulated in the capacitor 13b and the amount of the electric charges.

It should be noted that, in this embodiment, the multiply-accumulate signal is output by performing threshold determination with the common threshold θ for each of the capacitors 13a and 13 b. That is, θ 1 is set to θ 2.

Further, the comparators 20a and 20b output a positive multiply-accumulate signal and a negative multiply-accumulate signal, respectively, based on the detected timing. For example, an electric signal that enters a conductive state at a timing when the voltage of the capacitor exceeds a threshold value and then maintains the conductive state is generated. Such an electric signal is output as a positive multiply-accumulate signal or a negative multiply-accumulate signal.

Therefore, the comparator 20a outputs a positive multiply-accumulate signal by performing threshold determination using the common threshold θ on the capacitor 13 a. Further, the comparator 20b outputs a negative multiply-accumulate signal by performing threshold determination using the common threshold θ on the capacitor 13 b. The predetermined threshold value θ will be described later in detail.

As shown in FIG. 5, the positive weight of the positive synaptic electrical circuit 8a (the first resistor 17a) and the positive weight of the negative synaptic electrical circuit 8b (the third resistor 17c) are connected in parallel to the capacitor 13 a. The positive weight of each synaptic electrical circuit 8 constitutes a row of positive weights 18 a. Further, the negative weight of the positive synaptic circuit 8a (the second resistor 17b) and the negative weight of the negative synaptic circuit 8b (the fourth resistor 17d) are connected in parallel to the capacitor 13 b. The negative weight of each synaptic electrical circuit 8 constitutes a row of negative weights 18 b. Further, a circuit including one weight row 18 and the capacitor 13 and a comparator 20 connected to the weight row 18 function as a multiply-accumulate deriving means for deriving a multiply-accumulate result.

For example, assume that N synapse circuits 8 are provided in the analog circuit 3. In this case, N positive weights (negative weights) are connected to the capacitor 13a (capacitor 13b) as the positive weight row 18a (negative weight row 18 b). Thus, in this configuration, the same number of weights as the synaptic electrical circuit 8 (resistor 17) are connected in parallel to each capacitor.

Further, in each synaptic electrical circuit 8, a positive weight value and a negative weight value (v)_i ⁺And | v_i ^-|) are set to be equal to each other. Therefore, the sum total value of the positive weight values included in the positive weight line 18a and the sum total value of the negative weight values included in the negative weight line 18b are equal to each other. Therefore, a circuit that outputs a positive multiply-accumulate signal and a circuit that outputs a negative multiply-accumulate signal can be regarded as circuits having similar configurations.

Fig. 8 is a diagram for describing a calculation example of the multiply-accumulate signal of the analog circuit 3 shown in fig. 5. In this embodiment, a positive multiply-accumulate signal is output based on the positive weight charge accumulated in the capacitor 13a, and a negative multiply-accumulate signal is output based on the negative weight charge accumulated in the capacitor 13 b.

As described above, the circuit for outputting the positive and negative multiply-accumulate signals is basically a similar circuit. Therefore, the calculation of the positive multiply-accumulate signal (multiply-accumulate result of the positive weight charge) and the calculation of the negative multiply-accumulate signal (multiply-accumulate result of the negative weight charge) are the same process. Fig. 8 shows a diagram representing a calculation example of the multiply-accumulate signal in one weight row 18 (positive weight row 18a or negative weight row 18 b).

Hereinafter, a calculation method (multiply-accumulate method) of a multiply-accumulate result based on the electric charge accumulated in the capacitor 13 will be described with reference to fig. 8 without distinguishing between positive and negative values. It should be noted that in some cases, both the positive and negative signals will be referred to as input signals as the signal values (x) of the positive and negative signals_i ⁺And | x_i ^-|) will be referred to as signal value y_iAnd as weight values of positive and negative weights (v)_i ⁺And | v_i ^-|) will be referred to as weight values v_i。

“S_i(t) "represents an inputTo the input signal (TACT signal) in the i-th input signal line pair P6. ' tau_i"denotes the slave input signal S_i(T) input timing to end timing T of input period T_nThe duration of (c). Thereafter, ` τ_i"may be referred to as input signal S_i(T) pulse width in the input period T. When is "τ_i"when the input signal t (t) becomes larger, it shows a larger signal value y_iOf the signal of (1).

“P_i(t) "represents the amount of change in the internal state (potential) in each synaptic electrical circuit 8 shown in FIG. 5. "v" is a unit of_i"denotes a weight value of a weight connected to one weight line (positive weight line or negative weight line), and is defined by a resistance value of the resistor 17 shown in fig. 5. Here, it is assumed that the potential corresponding to each synaptic electrical circuit 8 increases linearly with time. At this time, the resistance value of the resistor 17 is set, for example, so that the gradient of the potential is "v_i”。

For example, with respect to S₁(t), gradient of potential (weight value v)₁) Smallest compared to the others. Thus, by S₁(t) the charge generated per unit time is minimized. On the other hand, with respect to S₂(t), gradient of potential (weight value v)₂) The maximum compared to the others, and the charge generated per unit time is the maximum. Furthermore, S₄(t) is the pulse width τ thereof₄Is 0 and its signal value y_iA signal of 0. In this case, the potential of the signal line is at the timing T from the end of the input period T_nEntering a conducting state. Thus, with respect to S₄(T) charging is started with the start of the output period T, and the potential representing the internal state is according to the weight value v₄And (4) increasing.

"α" represents a gradient in which the potential of the capacitor 13 rises in the output period T after the input period T, and is a charging speed of the capacitor 13. In the example shown in fig. 8, each synaptic electrical circuit 8 is maintained at the conduction level after the input period T has elapsed, and thus the potential of capacitor 13 increases with a gradient "α". It should be noted that, for example, when the capacitor 13 is charged through another wiring in the output period T, α is a value corresponding to the charging speed. θ denotes a threshold value used for threshold value determination performed by the signal output unit 12 (comparator 20).

“V_n(t) "represents" P_i(t) "and corresponds to the total amount of electric charges accumulated in the capacitor 13. "S_n(t) "represents a multiply-accumulate signal (PWM signal) representing a multiply-accumulate result. ' tau_n"denotes a pulse width of the multiply-accumulate signal to be output. Specifically, "τ_n"indicates a timing corresponding to a period from the timing at which the voltage held by the capacitor 13 exceeds the threshold value θ in the output period T to the end timing T of the output period T_mThe value of the duration of time.

Here, as shown in the following expression, the signal value y of the input signal_iBy the input signal S in the input period T_i(t) pulse width τ_iDuty ratio R to input period T_i(. tau/T).

[ formula 4]

The synaptic electrical circuit 8 shown in FIG. 5 generates and combines the signal value y_iMultiplying by a weight value v_iAnd the obtained product value corresponds to the charge. In particular, the resistance of the resistor 17 is at a constant gradient v_iIncreasing the internal state (potential).

The internal potential of each synaptic circuit 8 is at the end timing T of the input period T_nAmount of change Pi (t) of_n) Given by the following expression. It should be noted that the input signal S_iThe high level value of (t) is set to 1.

[ formula 5]

P_i(t_n)＝v_iR_iT＝v_iy_iT

The total amount V of charge accumulated in the capacitor 13_n(t_n) Is Pi (t)_n) The sum of (a) and (b) is thus given by the following expression.

[ formula 6]

In the example shown in fig. 5, at the end timing T of the input period T_nThereafter, all input signals enter the conducting state and the internal states (potentials) in all synaptic circuits 8 are graded by a gradient v_iAnd (4) increasing. That is, the electric charge is output to the capacitor 13 from all the weights connected to the weight row. At this time, the gradient (charging speed α) of the voltage of the capacitor 13 is equal to each "v_i"is the sum of. That is, the charging speed α is the sum of all weight values provided in the weight line.

The comparator performs threshold determination on the voltage of the capacitor 13 that increases at the charging speed α. Is generated to have a timing from the timing at which the voltage held by the capacitor 13 exceeds the threshold value θ in the output period T to the end timing T of the output period T_mCorresponding to the duration of the pulse width τ_nMultiply accumulate the signal.

Suppose pulse width τ of multiply-accumulate signal_nDuty ratio to output period T is R_n(＝τ_n/T), then R)_nGiven by the following expression. It should be noted that the threshold value θ is equal to or greater than the total amount V of electric charge_n(t_n)。

[ formula 7]

Thus, by dividing the signal value y_iMultiplying by a weight value v_iEach product value (v) thus obtained_i*y_i) The multiply-accumulate result obtained by the addition is given by the following expression.

[ formula 8]

That is, the multiply-accumulate result is from α R_n＝α·(τ_nSubtracting from the charging rate in/T)Degree α, threshold θ, and output period T. In this way, the multiply-accumulate signal representing the multiply-accumulate result for each weight pair can be based on the timing (pulse width τ) at which the voltage held by the accumulation unit 11 exceeds the threshold θ in the output period T having a predetermined duration_n) And (6) outputting.

In the example shown in fig. 5, a multiply-accumulate signal representing the multiply-accumulate result shown in the expression (formula 8) is calculated for each of the positive weight rows 18a and the negative weight rows 18 b. For example, the comparator 20a generates a positive multiply-accumulate signal S indicating a multiply-accumulate result of the positive weight charge output from the positive weight row 18a_n ⁺(t) of (d). Further, the comparator 20a generates a negative multiply-accumulate signal S indicating a multiply-accumulate result of the negative weight charge output from the negative weight row 18b_n ^-(t)。

Fig. 9 is a diagram showing an example of positive and negative multiply-accumulate signals. Hereinafter, the negative multiply-accumulate signal S_n ⁺(t) the pulse width will be defined by_n ⁺"denotes, negative multiply-accumulate signal S_n ⁺(t) the pulse width will be defined by_n ^-"means. Further, the "S" shown in FIG. 9_n(t) "is an exemplary multiply-accumulate signal representing the total multiply-accumulate signal of the positive and negative multiply-accumulate signals included in the analog circuit 3. S_n(t) pulse width of "τ_n"means.

By multiplying the value (v) in the positive weight row 18a_i*y_i) The multiply-accumulate result obtained by the addition is the sum of the product values of the positive weights provided in the positive weight pair and the negative weight pair. That is, the multiply-accumulate result of the positive weight row 18a is the sum σ of the positive weight product values described using the expression (formula 3)⁺. Therefore, according to the expression (formula 6), at the end timing T of the input period T, T_nThe total amount V of the positive weight charges accumulated in the capacitor 13a_n ⁺(t_n) Given by the following expression.

[ formula 9]

By composing N as shown in the expression (equation 9)⁺Positive signal (positive input x) of a signal pair_i ⁺) Associated with positive weights forming pairs of positive weights in the input period T, and will form N-N⁺＝N^-Negative signal of a signal pair (negative input x)_i ^-) Calculating the sum of product values of positive weights σ in association with positive weights constituting a pair of negative weights in an input period T⁺。

By multiplying the value (v) in the negative weight row 18b_i*y_i) The multiply-accumulate result obtained by the addition is the sum of the product values of the negative weights provided in the positive weight pair and the negative weight pair. That is, the multiply-accumulate result of the negative weight row 18b is the sum σ of the negative weight product values described by using the expression (formula 3)^-. Therefore, according to the expression (formula 6), at the end timing T of the input period T, T_nAt this point, the total amount V of negative weight charges accumulated in the capacitor 13b_n ^-(t_n) Given by the following expression.

[ equation 10]

By composing N as shown in the expression (equation 10)⁺Negative signal of a signal pair (negative input x)_i ^-) Associated with positive weights forming pairs of positive weights in the input period T, and will form N^-Positive signal (positive input x) of a signal pair_i ⁺) Calculating the sum σ of the product values of the negative weights in association with the positive weights constituting the pair of negative weights in the input period T^-。

Assuming a positive multiply-accumulate signal S_n ⁺(t) duty cycle is represented by R_n ⁺(＝τ_n ⁺T) and set in the positive weight line 18a, and a weight value (v)_i ⁺) Is composed of⁺And (4) showing. In this kind ofIn this case, the result of multiply-accumulate (sum of positive weight product values σ) calculated by the positive weight row 18a⁺) Given by the following expression. It should be noted that the threshold θ is assumed to be equal to or greater than the total amount V of positive-weight charges_n ⁺(t_n)。

[ formula 11]

Assuming a negative multiply-accumulate signal S_n ^-(t) duty cycle is represented by R_n ^-(＝τ_n ^-T) and set in the negative weight line 18b, and a weight value (v)_i ^-) Is composed of^-And (4) showing. In this case, the result of multiply-accumulate (sum of negative weight product values σ) calculated by the negative weight row 18b^-) Given by the following expression. It should be noted that the threshold value θ is equal to or larger than the total amount V of negative weight charges_n ^-(t_n) And θ is the same value as shown in the expression (formula 11).

[ formula 12]

As described above, in the analog circuit 3 configured by using the weight pair, the weight values (W) to the positive weight row 18a and the negative weight row 18b are set⁺And W^-) The sums of (a) and (b) are equal to each other. Hereinafter, the sum value of the weight values set in each weight line is denoted by W. Therefore, in this embodiment, the positive weight value v is weighted in the analog circuit 3_i ⁺Sum of (W)⁺And a negative weight value v_i ^-Absolute value of | vi^-Total sum of | W^-Set to the same common sum value W. The sum W (common sum) of the weight values is equal to the sum of the positive and negative weights W_i ⁺Sum and negative pair weight w_i ^-The sum is added to obtain a value as follows.

[ formula 13]

In addition, the total multiply-accumulate result is formed by the sum σ of the positive-weight product values⁺Sum of product values sigma of negative weights^-The difference therebetween, as shown in the expression (equation 3). Therefore, using the expression (formula 11), the expression (formula 12), and the expression (formula 13), the total multiply-accumulate result is given by the following expressions.

[ formula 14]

That is, the sum W of the weighted values and the positive multiplication and accumulation signal S_n ⁺(t) pulse width τ_n ⁺Negative multiply-accumulate signal S_n ^-(t) pulse width τ_n ^-And outputting the period T to obtain the total multiply-accumulate result. In this way, the multiply-accumulate result can be easily calculated based on the timing detected by the comparator 20a and the timing detected by the comparator 20 b.

Thus, the analog circuit 3 calculates the "sum" of the N product values determined based on the positive and negative electric signal pairs and the positive and negative weight pairs based on the analog signal. Thus, for example, irrespective of the input value x_iAnd a weight value w_iWhether positive or negative, the multiply-accumulate operation may be performed as appropriate.

In the analog circuit 3, positive multiply-accumulate signals S are generated respectively_n ⁺(t) and a negative multiply-accumulate signal S_n ^-(t) of (d). That is, the pulse width τ is generated to have as a signal value_n ⁺And pulse width τ_n ^-A pair of electrical signals (signal pair). Thus, the input value x represented by the signal pair_iEqual to the pulse width tau corresponding to the total multiply-accumulate result_n. Therefore, the analog circuit 3 is a circuit that outputs the total multiply-accumulate result as a signal pair。

It should be noted that a single electrical signal representing the total multiply-accumulate result may also be output, instead of a signal pair. For example, generating the total multiply-accumulate signal S_n(t) the total multiply-accumulate signal S_n(t) has a pulse width of τ_n ⁺And pulse width τ_n ^-The difference between them as the pulse width τ_n. Such a multiply-accumulate signal S_n(t) can be easily configured by using a logic circuit such as an AND circuit AND a NOT circuit. For example, in the arithmetic device 100, the total multiply-accumulate signal S_n(t) is used as the output of the uppermost (final) stage.

Fig. 10 is a schematic diagram showing an example of connection between the analog circuits 3 of the layers. In fig. 10, an analog circuit 3a provided in the first layer and an analog circuit 3b provided in the second layer are schematically shown. It should be noted that the second layer is a layer subsequent to the first layer.

For example, in the input period T, a plurality of signal pairs are input to the analog circuit 3a of the first layer. The analog circuit 3a generates a positive multiply-accumulate signal S during the output period T_n ⁺And negative multiply-accumulate signal S_n ^-Each of which. Positive multiply-accumulate signal S_n ⁺And negative multiply-accumulate signal S_n ^-Is a signal pair representing the total multiply-accumulate result of the analog circuit 3 a.

In this embodiment, the signal pair (S) generated in the first layer_n ⁺And S_n ^-) Is used as an input signal for the second layer. That is, the signal pair is used as an input to any one of the synaptic circuits 8 of the analog circuit 3 b. For example, the outputs (the positive output signal line 10a and the negative output signal line 10b) of the comparators 20a and 20b of the analog circuit 3a are connected to the positive input signal line 6a and the negative input signal line 6b of any one of the input signal line pairs P6 of the analog circuit 3b, respectively.

As shown in fig. 10, a signal pair (S) generated in the first layer_n ⁺And S_n ^-) Is a pair of signals input into the second layer in the input period T. That is, the output period T in the first layer is at the firstInput period T in two layers. It should be noted that where S may be employed_n ⁺And S_n ^-A configuration in which the operation time is delayed in the second layer and stored in an analog memory or the like.

As described above, in which the signal pair (S) is combined_n ⁺And S_n ^-) In the configuration as the multiply-accumulate signal output, the signal pair may be used as an input of the next stage as it is. Thus, for example, there is no need to multiply the accumulation signal S positively_n ⁺(t) and a negative multiply-accumulate signal S_n ^-(t) (total multiply-accumulate signal), and the circuit configuration can be substantially simplified. Further, since a circuit for calculating the difference is not required, the power consumption of the arithmetic device 100 can be reduced. Therefore, a low arithmetic device 100 of extremely high power consumption can be realized.

Hereinafter, a charging mode of the charging unit 15 when the capacitor 13 is charged will be described.

In this embodiment, in one or more analog circuits 3, the charging of the charging unit 15 is performed in a common charging mode, and the common threshold θ is set to a predetermined threshold θ. Here, the one or more analog circuits 3 are analog circuits 3 connected to the common input signal line pair P6, and are analog circuits 3 constituting one layer, for example.

The charging of the capacitors 13 in the one or more analog circuits 3 is performed based on a common time constant. That is, the common charging mode includes charging based on a common time constant in the one or more analog circuits 3. Thus, each capacitor 13 may be charged according to a similar charging curve, for example. Further, a common charge signal or the like is used for this charging. In other words, it can be said that charging using a similar charging method is performed in one or more analog circuits 3.

Further, the threshold determination is performed on the voltage of each capacitor 13 charged in the common charging mode using the common threshold θ. Therefore, in the arithmetic device 100, the voltage of the capacitor 13 charged in the common charging mode is determined based on the common threshold θ. Therefore, an appropriate multiply-accumulate result (positive and negative multiply-accumulate signals, etc.) can be output from each analog circuit 3.

In this embodiment, the common charging pattern includes a positive weight value v set in the plurality of synaptic electrical circuits 8 based on_i ⁺Sum of (W)⁺And a negative weight value v_i ^-Absolute value of | vi^-Total sum of | W^-Is charged, the maximum sum value of which is the largest in the one or more analog circuits 3. For example, based on the weight value v in each analog circuit 3_iSets a common charging parameter or the like, and charges each capacitor 13 in a common charging mode.

Further, the common threshold θ is set based on the maximum sum value. Therefore, in the arithmetic device 100, parameters (charge parameters, threshold θ, and the like) necessary for calculating the multiply-accumulate result are set based on the maximum sum value in one or more analog circuits 3.

For example, as shown in fig. 3, in the arithmetic device 100, a plurality of analog circuits 3 are connected to a common input signal line pair P6. In this case, the largest weight value v in these analog circuits 3_iTotal value of W (W)⁺Or W^-) Is the maximum sum value.

Further, for example, the arithmetic device 100 may be configured as an arithmetic module equipped with a single analog circuit 3. In this case, in the analog circuit 3, the sum value W of the positive weight rows 18a⁺Sum W with negative weight row 18b^-The larger of which is the maximum sum value. It should be noted that, as shown in the expression (formula 13), the sum value (W) in one analog circuit 3 has been described above⁺And W^-) The case of being equal to each other. In this case, W⁺And W^-Is the maximum sum value.

In any case, all capacitors 13 are based on the weight value v at the respective weight row 18_iIs charged, and the threshold determination is performed according to a threshold θ set based on the maximum sum value. Hereinafter, the charging mode of the charging unit 15 and the common threshold θ will be described in detail. Furthermore, the maximum sum will be represented by W_maxAnd (4) showing.

First, the voltage variation of the capacitor 13 is considered. For example, in fig. 8, the voltage change of the capacitor 13 assuming that the voltage of the capacitor 13 (potential to GND) linearly increases due to the charge supplied to the capacitor 13 has been described.

In an actual circuit, when electric charge is supplied to the capacitor 13, the voltage of the capacitor 13 varies according to a voltage curve. The voltage curve is a curve according to, for example, the capacitance C of the capacitor 13 and the resistance value (or conductance) of a resistor connected to the capacitor 13. Here, the capacitance C corresponds to, for example, a combined capacitance including a parasitic capacitance or the like in the weight row 18 (each synapse circuit 8) to which the capacitor 13 is connected.

For example, it is assumed that the capacitor 13 is charged in the analog circuit 3 shown in fig. 5. The plurality of input signal lines 6 are connected in parallel with the capacitor 13 via the resistor 17. Therefore, the capacitor 13 accumulates charges in a state in which the plurality of resistors 17 are connected in parallel. When an electric signal that enters the on state from time t-0 to each input signal line 6 is input, the voltage curve v (t) of the capacitor 13 is represented by the following expression.

[ formula 15]

Here, V_inRepresents a constant which is the convergence value of the voltage and is usually the voltage value (pulse height) representing the on-state of the input signal. T is₀Is the time constant of the voltage curve and is the voltage V (t) reaching the convergence value V_inAbout 63% of the time. The expression (formula 15) is gradually approaching V with the lapse of time t as shown below_inAs a function of (c).

Using the combined capacitance C of the capacitor 13 and the combined conductance w of the resistor 17 connected in parallel to the capacitor 13₀Will make the time constant T₀Is denoted by T₀＝C/w₀. Combined conductance w₀Is, for example, dependent on the weight value v_iThe sum value of (a) and (b). Therefore, the voltage of the capacitor 13 is dependent on the weight value v_iIs changed according to the total sum value W ofAnd (4) transforming. It should be noted that the voltage curve is the charging curve of the capacitor 13, and T₀Is the time constant when the capacitor 13 is charged.

Fig. 11 is a schematic diagram showing an example of a change over time in the voltage held by the capacitor 13. The horizontal axis of the graph indicates time, and the vertical axis indicates the voltage v (t) of the capacitor 13.

In FIG. 11, the weight value v is shown_iIs the maximum sum W_maxThe maximum voltage curve V of the voltage change of the capacitor 13 in the case of_max(t) is shown as a solid grey line. V_max(t) is a value in which the time constant of the expression (formula 15) is in accordance with the maximum sum value W_maxTime constant T of_WCurve (c) of (d). For example, when connecting to a sum of W_maxWhen the capacitor 13 of the weight of (1) is charged at the maximum charging speed, the voltage of the capacitor 13 is according to the maximum voltage curve V_max(t) is varied.

So to speak, according to V_max(t) is a voltage variation in which the voltage has a value according to the maximum sum W_maxIs connected to the voltage variation in the circuit of the capacitor 13 with the capacitance C. Therefore, the maximum voltage curve V_max(t) is a value obtained when the capacitor 13 has a value according to the maximum sum W_maxThe resistance value of (1) and the voltage of the capacitor 13 when charged by the resistor 17. The threshold value theta is based on the maximum voltage curve V_max(t) is set.

In this embodiment, the threshold θ is based on a curve V according to the maximum voltage during the input period T_max(t) the voltage of the varying capacitor 13 is varied. The voltage change is, for example, a voltage V when the capacitor 13 is charged within the input period T at the maximum charging speed from a state in which the voltage of the capacitor 13 is 0_max(T). Generally, the voltage V_max(T) is set as the threshold value θ. Therefore, the threshold θ is expressed as follows.

[ formula 16]

For example, it is assumed that the maximum pulse whose pulse width is the maximum in the input period T is input to all the input signal lines 6, that is, the capacitor 13 is charged at the maximum charging speed from T-0. This is a state in which the multiply-accumulate result is maximum. In this case, as shown in fig. 11, the voltage of the capacitor 13 is at the end timing T of the input period T_n(start timing T of output period T)_n) Exceeds the threshold theta.

On the other hand, it is assumed that a pulse whose pulse width becomes 0 in the input period T is input to all the input signal lines 6, that is, the capacitor 13 is changed from T to T_nThe charging is performed at the maximum charging speed. This is a state in which the multiply-accumulate result is minimum. In this case, the voltage of the capacitor 13 is at the end timing T of the output period T_mExceeds the threshold theta.

In this way, the maximum multiply-accumulate result and the minimum multiply-accumulate result are detected at the beginning and the end of the output period T. As a result, the multiply-accumulate signal can be accurately calculated with high resolution in the output period T. That is, the maximum sum value W can be obtained by calculating the sum value based on the input period T and the maximum sum value W_maxThe threshold value θ is set to show a favorable effect.

It should be noted that the threshold θ may be set based on the value on the right side of the expression (formula 16). For example, in the case where the frequency (ratio) of calculating the minimum value of the multiply-accumulate result is low, the threshold θ may be set to a value slightly larger than the expression (formula 16). In contrast, in the case where the frequency (ratio) of calculating the maximum value is low, the threshold θ may be set slightly larger. Therefore, even in the presence of voltage noise or the like, the multiply-accumulate result can be appropriately detected.

In actual operation, it is conceivable that, in the input period T (refer to fig. 5), input signals having various pulse widths τ as shown below are input to the respective resistors 17 (weights). In fig. 11, a histogram showing the distribution of those pulse widths is schematically shown.

In the case where the pulse width τ of each input signal is not constant, the voltage of the capacitor 13 is not necessarily constantAlong a curve V with the maximum voltage_max(t) the corresponding curve rises. In this case, the voltage of the capacitor 13 in the input period T is increased in accordance with, for example, the pulse width τ (the graph of the black solid line in fig. 11) of each input signal (input timing).

Further, at the end timing T of the input period T_nThereafter, all input signals are brought into a conducting state, and electric charges are supplied from all weights, for example. That is, the capacitor 13 is charged at the maximum charging speed. Therefore, the voltage of the capacitor 13 in the output period T follows a voltage corresponding to V regardless of the pulse width of the input signal or the like_maxThe curve of (t) increases. For example, the voltage of the capacitor 13 in the output period T is represented by the following expression.

[ formula 17]

V_tnIs the end timing T of the capacitor 13 at the input period T_nAnd is a voltage according to the sum (multiply-accumulate result) of the charges accumulated in the input period T. Therefore, the expression (equation 17) represents when the voltage V corresponding to the multiply-accumulate result is maintained_tnCapacitor 13 according to V_max(t) voltage change at the time of charging.

In addition, V_tnBy substituting the average value of the pulse width τ of the input signal inputted to each weight into the maximum voltage curve V_max(t) is obtained. That is, the capacitor 13 is used at the end timing T of the input period T_nThe voltage held at (a) is a voltage similar to that in the case where a pulse having a width similar to the average value of the pulse width τ is input to all weights.

Therefore, the voltage of the capacitor 13 can be set according to the maximum sum value W of the respective input signals_maxThe average of the sum pulse width τ is based on the time constant T_WTo be determined. That is, as shown in fig. 11, the voltage of the capacitor 13 can be considered as an average value obtained by subtracting the pulse width τ of each input signal from the input period TThe timing obtained (median value of the histogram) follows the curve V with the maximum voltage_max(t) voltage increase of the corresponding curve.

In this embodiment, the charging unit 15 is configured such that each capacitor 13 is charged according to the expression (formula 17). That is, in the output period T, the time constant of the voltage (charge) variation of each capacitor 13 is in accordance with the maximum sum value W_maxTime constant T of_W. As described above, the common charging mode performed by each analog circuit 3 is based on the maximum sum value W_maxAccording to the time constant T_WThe capacitor 13 is charged.

The voltage increased according to the expression (formula 17) exceeds the threshold value θ in the output period T. The timing exceeding the threshold value θ is used to generate a multiply-accumulate signal representing the multiply-accumulate result of the capacitor 13. As described above, it can be said that the process of charging the capacitor 13 according to the expression (formula 17) and performing threshold determination using the threshold value θ is to normalize the voltage V with the threshold value θ_tnThe conversion is to a process of voltage (pulse width) normalized by the period T.

Here, consider the weight value v connected thereto_iIs less than the maximum sum value W_maxThe voltage of the capacitor 13 of the weight row 18 varies. For example, assume that there is a connection to W<W_maxThe capacitor 13 of the capacitance C of the weight row 18 of (a) is charged at the maximum charging speed from the beginning of the input period T. In this example, the voltage curve V' (t) of the capacitor 13 (gray dashed line in fig. 11) is a curve in which the voltage variation is smaller than the maximum voltage V_maxCurve of (t).

Therefore, at the end timing T of the input period T_nW is<W_maxIn the case where the maximum value V' (T) of the voltage of the capacitor 13 connected to the weight row 18 is smaller than the maximum sum value W_maxSet threshold value theta (V)_max(T)). Therefore, in the input period T, the connection to the voltage W<W_maxThe voltage of the capacitor 13 of the weight row 18 does not exceed the threshold value theta.

Further, V' (T) can be simply regarded as the voltage of the capacitor 13 having the capacitance C. Therefore, for example, by charging the capacitor 13 holding V '(T) according to the curve shown in the expression (formula 17) and performing threshold determination using the threshold value θ, V' (T) normalized by the threshold value θ can be converted into timing normalized by the period T.

I.e. in connection with which W is provided_maxIn the charging mode common to the capacitors 13 of the weight row 18, to the capacitor connected to W<W_maxThe capacitors 13 of the weight row 18 are processed so that a multiply-accumulate signal normalized with the same normalization parameter can be generated. Therefore, the multiply-accumulate values represented by the multiply-accumulate signals can be accurately aligned.

It should be noted that even at W<W_maxIn the case of (2), it is also possible to charge the capacitor 13 according to the expression (formula 17), and perform threshold determination on the voltage of the capacitor 13 using the threshold θ. In this case, a current source different from the input signal line 6 and the resistor 17 is used to charge the capacitor 13. This will be described in detail later with reference to fig. 13 and 15 and the like.

By using the time constant T in this way_WAnd based on the maximum sum value W_maxThe set threshold value θ can appropriately calculate the multiply-accumulate result in the ownership re-row 18 included in the analog circuit 3 connected to the common input signal line pair P6. For example, the multiply-accumulate result calculated by each analog circuit 3 is a value normalized with the same normalization parameter (threshold value θ and output period T).

Therefore, for example, a plurality of multiply-accumulate results generated in one layer can be output to the next layer as values that can be compared with each other, and a highly accurate analog multiply-accumulate operation can be realized. Further, for example, the threshold value θ can be supplied to all the analog circuits 3 with a single wiring, and the circuit configuration can be sufficiently simplified.

Fig. 12 to 15 are circuit diagrams showing configuration examples of the arithmetic device. The arithmetic devices 200 to 500 shown in fig. 12 to 15 each include a plurality of analog circuits 3 connected in parallel to each of a plurality of pairs of input signal lines P6. Hereinafter, the configuration of the weight pairs in the plurality of analog circuits 3 connected in parallel to each other will be specifically described.

In the arithmetic apparatus 200 shown in fig. 12, binary weights are set, and each analog circuit 3 is provided with the same number of synapse circuits 8.

The binary weights are configured to implement, for example, binary connections, and the pair weight value w of each synaptic electrical circuit 8_iIs set to ± w. In this case, both positive and negative weights included in the positive and negative weight pairs (the positive synaptic circuit 8a and the negative synaptic circuit 8b) are set to the weight value w. I.e. a positive weight value v_i ⁺And a negative weight value v_i ^-Absolute value of | vi^-| is fixed to the same value. Thus, v is the sum of all the weight pairs in the arithmetic device 200_i ⁺＝|v_i ^-W holds.

Further, in the arithmetic apparatus 200, the number of synapse circuits 8 (weight pairs) included in each analog circuit 3 is set to the same number. That is, the arithmetic device 200 has a configuration in which the analog circuits 3 including the same number of weight pairs are connected in parallel with the plurality of input signal line pairs P6.

Therefore, in the arithmetic apparatus 200, the weight values of the positive weight and the negative weight are equal, and the number of synapse circuits 8 included in each analog circuit 3 is equal. Therefore, in the plurality of analog circuits 3 in the arithmetic device 200, as the weight value v_iIs set to the same value W.

For example, the number of synapse circuits 8 provided in one analog circuit 3 is N, in which case, in each analog circuit 3, the sum value W⁺Total sum of values W^-W stands for N × W. Therefore, in the arithmetic device 200, the weight values v included in the positive weight line 18a and the negative weight line 18b_iAll of the sum W of (a) and (b) are equal. Weight value v common to ownership redo 18a_iIs the maximum sum W_max。

In the example shown in fig. 12, four input signal line pairs P6 and three analog circuits 3 are provided. Furthermore, each analog circuit 3 comprises four synaptic circuits 8 connected to four pairs of input signal lines P6, respectively.

Further, in fig. 12, the left analog circuit 3 is constituted by all the positive synapse circuits 8 a. In the central analog circuit 3, a positive synaptic electrical circuit 8a is set as first and second synaptic electrical circuits from the top, and a negative synaptic electrical circuit 8b is set as third and fourth synaptic electrical circuits. The right analog circuit 3 is made up of all negative synaptic circuits 8 a. Of course, the number of analog circuits 3, the number of synapse circuits 8, the sign of the weight set in the synapse circuits 8, and the like are not limited to the examples shown in fig. 12.

It should be noted that, in fig. 12, an example of a signal pair (positive signal and negative signal) input into each input signal line pair P6 and an example of a signal pair (positive multiply-accumulate signal and negative multiply-accumulate signal) output from each analog circuit 3 are schematically shown.

When the input period T begins, the AND indicates the input value x_iPositive and negative values of (x)_i ⁺And x_i ^-) Corresponding positive and negative signals (signal pairs) are input into each input signal line pair P6. For example, a signal pair input into the first input signal line pair P6 from the top is simultaneously input into the first synapse circuits 8 of the left, right and central analog circuits 3. Similarly, the signal pairs input into the corresponding input signal line pair P6 are simultaneously input into the synapse circuits 8 of the respective analog circuits 3.

In the positive synaptic circuit 8a (positive weight pair), a positive weight product value of the positive signal and the positive weight is calculated, and a negative weight product value of the negative signal and the negative weight is calculated. Further, in the negative synapse circuit 8a (negative weight pair), a positive weight product value of the negative signal and the positive weight is calculated, and a negative weight product value of the positive signal and the negative weight is calculated. The positive weight charges corresponding to the positive product value are output to the positive charge output line 7a, and the negative weight charges corresponding to the negative product value are output to the negative charge output line 7 b.

As a result, in the input period T, the positive weight charges and the negative weight charges are simultaneously accumulated in the capacitors 13a and 13b provided in each analog circuit 3. At the end timing T of the input period T_nHere, the accumulation of the electric charge corresponding to the sum of the product values is completed, and the voltage of the capacitor 13 becomes a voltage representing the multiplication-accumulation result. At this time, multiplication by the plurality of analog circuits 3 is completedCalculation of the accumulation result (multiply-accumulate operation processing).

As shown in fig. 12, a signal that continuously maintains an on state during the output period T as each signal pair (input signal) in the arithmetic device 200. Thus, each capacitor 13 can be charged during the output period. Therefore, the signal (voltage) input in the output period T functions as a common charge signal for charging the capacitor 13. That is, it can also be said that the plurality of input signal line pairs P6 supply the charge signal that enters the on state after the input period T.

For example, the voltage of each input signal line pair P6 is brought into a conducting state, so that electric charges are generated by positive and negative weights (resistors 17) provided in the synapse circuit 8 and accumulated in the capacitors 13a and 13b through the positive and negative output lines 7, respectively. In this way, in the arithmetic device 200, the capacitor 13 is charged by accumulating the electric charges generated by the plurality of synapse circuits 8 based on the electric charge signal.

As described above, in the arithmetic device 200, the weight value v included in each weight line 18_iAre all equal (maximum sum value W)_max). Therefore, in the output period T, the charging time constant of each capacitor 13 is dependent on the weight value v_iTime constant T of the sum value W of_W. Therefore, during the output period T, all the capacitors 13 included in the arithmetic device 200 are charged according to the curve represented by the expression (formula 17).

In addition, in the output period T, the maximum sum value W is used_maxThe set common threshold value θ performs threshold determination on the voltage of each capacitor 13 in the output period T. The common threshold θ is a value set using an expression (formula 16). Therefore, in the ownership resumption line 18, the voltage of the capacitor 13 normalized by the threshold value θ is converted to the timing normalized by the output period T. As a result, a plurality of comparable multiply-accumulate signals can be generated simultaneously. That is, a plurality of multiply-accumulate operations can be executed in parallel, and high-speed operation processing can be realized.

Therefore, in the arithmetic device 200, the respective weight values v in the respective weight rows 18_iOfAnd the sum W are all equal. In this example, the respective capacitors 13 can be driven by the charge signals supplied from the plurality of pairs of input signal lines P6 according to the same time constant T_WAnd (6) charging. In other words, due to the weight value v_iAre equal to each other, the capacitor 13 is charged according to a similar voltage curve even if the input signal line pair P6 is used as a source of the charge signal.

Therefore, in the arithmetic device 200, the capacitor 13 can be charged while using the wiring for inputting a signal pair. Furthermore, since each capacitor 13 can be based on a similar time constant T_WCharging, and thus the threshold θ can be shared. Therefore, for example, it is not necessary to provide a dedicated wiring for charging the capacitor 13, a wiring for separately supplying the threshold value θ, or the like, and the circuit configuration can be sufficiently simplified.

In the arithmetic apparatus 300 shown in fig. 13, binary weights are set and the number of synapse circuits 8 provided in each analog circuit 3 is different.

The arithmetic device 300 includes a plurality of pairs of input signal lines P6, a plurality of analog circuits 3, and a charging circuit 40. As shown in fig. 13, in the arithmetic device 300, the number of synapse circuits 8 included in the analog circuit 3 is set for each analog circuit 3. It should be noted that each synaptic electrical circuit 8 is set to have a binary weight, and v is set to have a binary weight in all synaptic electrical circuits 8_i ⁺＝|v_i ^-W holds.

Therefore, in the arithmetic apparatus 300, the weight values of the positive weight and the negative weight are equal, and the number of synapse circuits 8 included in each analog circuit 3 is different. Therefore, in the arithmetic device 300, the plurality of analog circuits 3 are included therein as the weight values v_iThe common sum value of the sum values W of (a) and (b) are different from each other.

For example, it is assumed that the number of input signal line pairs P6 is denoted by N, and the maximum number of synaptic circuits 3 set in each analog circuit 3 is denoted by N, that is, in the case where the synaptic circuits 3 are set in association with all of the input signal line pairs P6, the number of synaptic circuits 3 is the maximum. Therefore, in the analog circuit 3 including N synaptic circuits 3, the sum value W⁺Total sum of values W^-N × w. The Nxw is the maximum sum W_max。

Furthermore, N 'synaptic circuits 3(N'<N) is a circuit connected to N 'input signal line pairs P6 and not connected to the remaining (N-N') input signal line pairs P6. In the analog circuit 3, the sum value W⁺Total sum of values W^-N' × w holds. It should be noted that the sum value N' x W is smaller than the maximum sum value W_max(N'×w<W_max). Therefore, the arithmetic device 300 includes a circuit in which the maximum sum value W or less is set_maxAnd various weights 18 for the sum W of.

In the example shown in fig. 13, four input signal line pairs P6 and three analog circuits 3 are provided. The left analog circuit 3 is composed of four positive synaptic circuits 8 a. Thus, the left analog circuit 3 includes a circuit in which the maximum sum value W is set_maxPositive weight row 18a and negative weight row 18b of (═ 4 × w).

The central analog circuit 3 includes a positive synaptic circuit 8a connected to the second input signal line pair P6 from the top and a negative synaptic circuit 8b connected to the third and fourth input signal line pairs P6 from the top, and the sum of the weight values is 3 × w. The right analog circuit 3 includes a negative synaptic circuit 8b connected to the third and fourth pairs of input signal lines P6, and the sum of the weight values is 2 × w. It should be noted that the central analog circuit 3 is not connected to the first input signal line pair P6, and the right analog circuit 3 is not connected to the first and second input signal line pairs P6.

It should be noted that the configuration of the arithmetic device 300 is not limited to the above-described configuration. For example, the ratio of the positive synapse circuit 8a and the negative synapse circuit 8b included in the analog circuit 3 may be set appropriately to enable the target calculation to be performed. That is, the ratio may be set as needed to provide a configuration in which the positive synaptic electrical circuit 8a is 100% and a configuration in which the negative synaptic electrical circuit 8b is 100%. Alternatively, the number of synapse circuits 8 included in the analog circuit 3 may be set appropriately within a range of N or less. Of course, the correlation between each input signal line pair P6 and the synaptic electrical circuit 8 may also be arbitrarily set.

The charging circuit 40 includes a charging resistor 41 and a charging line 42. In the arithmetic device 300, the charging circuit 40 functions as a charging unit that charges the accumulation unit after the input period T.

The charging resistor 41 is connected between the charging line 42 and the output line 7 of each analog circuit 3. For example, two charging resistors 41 that connect the positive charge output line 7a and the negative charge output line 7b to a charging line 42 are provided in each analog circuit 3. In the example shown in fig. 13, six charging resistors 41 provided in association with the respective output lines 7 of the three analog circuits 3 are used. These charging resistors 41 are set to have the same resistance value (conductance).

The charging resistor 41 is set to have a value according to the maximum sum value W_maxThe resistance value of (2). Typically, the resistance value of the charging resistor 41 is set to serve as the maximum sum value W_maxA single resistor as a weight value.

For example, as described with reference to the expression (formula 15), the sum value W is a value corresponding to the combined conductance (the reciprocal of the combined resistance) of the resistors 17 included in one weight row 18. Therefore, the resistance value of the charging resistor 41 is set to the combined resistance of the resistors 17 included in the weight row 18, which is, for example, the maximum sum value W_max. Therefore, the charging resistor 41 may be regarded as having a weight value W_maxThe weight of (c).

The charging line 42 is, for example, a single signal line arranged orthogonal to the output line 7 of each analog circuit 3. A charging line 42 is connected to each output line 7 via a charging resistor 41. Therefore, it can also be said that the charging line 42 is connected to each capacitor 13 via the charging resistor 41.

As shown in fig. 13, at the end timing T of the input period T_nAt the same time, a charge signal is input into the charge line 42. The charge signal is an electrical signal that is maintained in an on state during the output period T. The voltage of the charge signal is, for example, equal to the voltage (V) of the input signal_in) The same is true. Accordingly, the charging line 42 supplies a charge signal that enters a conductive state after the input period T.

Thus, included in each weight row thereinIn a configuration in which the sum values W of the weights are different from each other, the charging line 42 for charging is provided separately from the N input signal line pairs P6. That is, charge signals (additional signals) separate from the N electric signals input to the respective weight rows are supplied. Further, the charge signal is obtained by having a maximum sum value W in the arithmetic device 300_maxA charging resistor 41 as a weight value is applied to the capacitor 13 of each analog circuit 3.

When the input cycle T starts, signal pairs are input into the respective synaptic circuits 8 via a plurality of pairs of input signal lines P6. For example, the signal pairs are input to the left analog circuit 3 from the first to fourth input signal line pairs P6. The signal pair is input to the central analog circuit 3 from the second to fourth input signal line pairs P6, and the signal pair is input to the right analog circuit 3 from the third and fourth input signal line pairs P6.

In the synapse circuit 8 to which each signal pair is input, a positive weight charge and a negative weight charge are generated and output to the positive charge output line 7a and the negative charge output line 7b, respectively. As a result, at the end timing T of the input period T_nThe multiply-accumulate operation is completed and each capacitor 13 holds a voltage corresponding to the multiply-accumulate result. It should be noted that, during the input period T, no charge signal is input, and the voltage of the charging line 42 is 0.

As shown in fig. 13, in the arithmetic device 300, the plurality of input signal line pairs P6 enter the off state after the input period T. That is, when the input period T ends, the signal pair (input signal) to be input into each input signal line pair P6 is switched to the low level. Therefore, an input signal that becomes high level at a time corresponding to the signal value during the input period T and becomes low level during the output period T is used. Therefore, in the arithmetic device 300, the input signal line pair P6 does not supply electric charge in the output period T.

On the other hand, when the input period T ends and the output period T starts, a charge signal is input into the charging line 42, and the voltage of the charging line 42 becomes a high level. Therefore, in the output period T, based on the charge signal input into the charging line 42, the charge (current) is generated by all the charging resistors 41.

The electric charges generated by the respective charging resistors 41 are each accumulated in the corresponding capacitor 13 via the output line 7. Therefore, at the same time as the start of the output period T, the charging of all the capacitors 13 is started. Accordingly, the charging circuit 40 charges the capacitor 13 by accumulating the charge generated by the charging resistor 41 based on the charge signal.

As described above, the charging resistor 41 may be regarded as having the weight value W_maxThe weight of (c). Therefore, the charge generated by the charging resistor 41 based on the charge signal having the same voltage as the input signal is equal to, for example, when the input signal is input in the on state to set the maximum sum value W_maxAll weights of the weight pairs of (1) are the generated charge.

Therefore, the voltage of the capacitor 13 charged by the charging circuit 40 varies according to the expression (formula 17). For example, all the capacitors 13 included in the left analog circuit 3, the center analog circuit 3, and the right analog circuit 3 in fig. 13 hold voltages corresponding to the respective multiply-accumulate results therefrom in accordance with the maximum sum value W_maxAccording to the time constant T_wAnd (6) charging. Therefore, by providing the charging circuit 40, it is possible to obtain the same time constant T_WAll capacitors 13 are charged regardless of the weight value v set as a weight pair_iThe sum of the values W.

Further, in the output period T, the use of the voltage of the capacitor 13 in the output period T is performed based on the maximum sum value W_maxA threshold value of the set common threshold value theta is determined. The common threshold θ is a value set using an expression (formula 16). Therefore, the multiply-accumulate signals normalized by the same normalization parameter (threshold θ and output period T) can be simultaneously generated in the ownership resumption line 18 regardless of the sum value W.

For example, assume that in the arithmetic device 300, based on being less than the maximum sum value W_maxThe sum value W' to set the threshold value θ. In this case, for example, the maximum multiply-accumulate result (gray dashed line in fig. 11) calculated in the weight row 18 having the sum value W' can be detected in the output period T. On the other hand, in the case of having the maximum sum value W_maxThe maximum multiply-accumulate result calculated in the weight row 18 of (a) may exceed the threshold value theta before the start of the output period T, i.e., in the input period T. Therefore, it is difficult to obtain the maximum sum value W_maxThe maximum multiply-accumulate result is suitably detected in weight row 18.

Further, it is assumed that in the arithmetic device 300, the respective capacitors 13 are charged using the input signal line pair P6 in the output period T. In this example, for example, in the left analog circuit 3, the capacitor 13 is according to W_maxThe time constant of (c) is charged. On the other hand, since the central analog circuit 3 is not connected to the first input signal line pair P6, the charging speed is reduced. In addition, since the right analog circuit 3 is not connected to the first and second input signal line pairs P6, the charging speed is further reduced. Therefore, in the charging using the input signal line pair P6, the charging speed may vary among the respective analog circuits 3.

On the other hand, since in the arithmetic device 300, the maximum sum value W is used_maxThe common threshold value θ is set so that the voltage of the capacitor 13 does not exceed the threshold value θ in the input period T. Therefore, the multiply-accumulate results (positive and negative multiply-accumulate signals) in all the analog circuits 3 connected to the plurality of input signal line pairs P6 can be appropriately calculated.

Further, in the arithmetic device 300, the capacitor 13 is charged in the output period T via the charging circuit 40 added separately from the input signal line pair P6. According to the maximum sum value W_maxCharging is performed with a time constant. Therefore, the variation in the charging speed is eliminated, and thus a comparable multiply-accumulate result can be easily calculated.

As described above, when the total values W of the weights of the analog circuits 3 (weight rows 18) are not all equal to each other, the maximum total value W, which is the maximum value of the total values W of the weights, is defined_maxAnd specifies the charging time constant T_WAnd a common threshold value theta. Therefore, even in the case where the weight v is_iIn the configuration in which the sum values W are different from each other, an appropriate multiply-accumulate result may be calculated by connecting a plurality of analog circuits 3 in parallel and simultaneously performing a plurality of multiply-accumulate operations.

In FIG. 14In the arithmetic device 400 shown, a multi-valued weight is set, and in the weight line 18 included in each analog circuit 3, a weight value v is set_iThe sum value W of (a) is set to the same value.

In the case of using multivalued weights, the pair weight value w of each synaptic circuit 8_iIs set to any one of a plurality of weight values (candidate weight values). In the following, the candidate weight value will be represented by { u }_jRepresents it. Candidate weight value { u_jIs a set of candidate values for weight values, e.g., { u }_j-1, -0.5, 0, 0.5, 1. By appropriately selecting the weight values u from these candidates_jTo set a pair weight value w_i. The number, specific value, and the like of the candidate weight values are not limited.

It should be noted that the positive and negative weight values (v) set in one synaptic electrical circuit 8_i ⁺And | v_i ^-| is set to the same value (candidate weight value u)_j). For example, in which the weight value w is adjusted_iIn the synaptic electrical circuit 8 set to 0.5, both the positive and negative weight values are set to 0.5. Thus, a positive weight value v_i ⁺And a negative weight value v_i ^-Absolute value of | vi^-| is set to a plurality of values { u } different from each other_jAny one of them.

Further, in the arithmetic apparatus 400, the number of synapse circuits 8 (weight pairs) included in each analog circuit 3 (weight row 18) is set to the same number, and the weight value v is set to be the same_iThe sum value W of (a) is set to the same value. Therefore, in the plurality of analog circuits 3 of the arithmetic device 400, as the weight value v_iIs set to the same value W. Weight value v common to ownership redo 18a_iIs the maximum sum W_max。

In the example shown in fig. 14, four input signal line pairs P6 and three analog circuits 3 are provided. Further, each analog circuit 3 is provided with four synapse circuits 8 connected to four pairs of input signal lines P6, respectively.

Further, in fig. 14, four types of candidate weight values u are used_j＝(u₁、u₂、u₃、u₄). Is provided with u₁、u₂、u₃And u₄Are schematically shown so that the grey color becomes lighter in the order described. Furthermore, each weight row 18 always comprises one resistor 17, which resistor 17 is arranged with u₁、u₂、u₃Or u₄As a positive weight (negative weight). Thus, the weight value v_iThe sum of W is W ═ W⁺＝W^-＝(u₁+u₂+u₃+u₄)＝W_max。

For example, in fig. 12, the left analog circuit 3 is constituted by four positive synapse circuits 8a in which weight values u are set in order from the top₁、u₂、u₃And u₄. With respect to the central analog circuit 3, the setting has a weight value set to u₃And u₂As the first and second circuits from the top, and set with a weight value set to u₁And u₄As third and fourth circuits, the negative synapse circuit 8 b. The right analog circuit 3 is composed of four negative synapse circuits 8a in which weight values u are set in order from the top₁、u₄、u₃、u₂。

When the input period T starts, the signal pairs are input to the respective synaptic circuits 8 via the plurality of input signal line pairs P6, and the charges are output from the respective resistors. At the end timing T of the input period T_nHere, the accumulation of the electric charge corresponding to the sum of the product values is completed, and the voltage of the capacitor 13 becomes a voltage representing the multiplication-accumulation result.

In the arithmetic device 400, a signal that also continuously maintains an on state during the output period T is used as each signal pair (input signal). That is, the charge signal brought into the on state after the input period T is supplied through the plurality of input signal line pairs P6.

As described above, in each weight line 18 included in the arithmetic device 400, the weight value v_iIs set to the same value (maximum sum value W)_max). Therefore, the time when each capacitor 13 is chargedConstant T_WIs common. As a result, during the output period T, all the capacitors 13 included in the arithmetic device 400 are charged according to the curve represented by the expression (formula 17).

The use of the capacitor 13 for each charge is performed based on the maximum sum value W_maxThe threshold value of the common threshold value θ calculated according to the expression (formula 16). Thus, a plurality of comparable multiply-accumulate signals can be generated simultaneously. Therefore, even in the case of using the multi-value weight, the sum value W of each weight row 18 is made constant, so that charging of the P6 using the input signal line can be performed, and the circuit configuration can be simplified. Further, the common sum value W (W) may be calculated by_max) The threshold value θ is set to properly calculate the multiply-accumulate result.

In the arithmetic apparatus 500 shown in fig. 15, a multi-valued weight is set, and a weight value v therefrom is used_iThe analog circuits 3 (weight rows 18) are different from each other in the total sum value W of (a).

The arithmetic device 500 includes a plurality of pairs of input signal lines P6, a plurality of analog circuits 3, and a charging circuit 40. The number of synapse circuits 8 (weight pairs) included in each analog circuit 3 (weight row 18) is set for each analog circuit 3. Further, in each synaptic electrical circuit 8, a slave candidate weight value u is set_jOf the weight values appropriately selected. Therefore, in the arithmetic device 500, the plurality of analog circuits 3 are included therein as the weight values v_iThe common sum value of the sum values W of (a) and (b) are different from each other.

Since the multivalued weight is used in the arithmetic device 500, the weight value v_iIs calculated as a candidate weight value u set in all synapse circuits 8 (weight pairs) included in one analog circuit 3_jThe sum of (a) and (b). Therefore, the sum value W is not necessarily large even when the number of synapse circuits 8 is large, and conversely, the sum value W may be large even when the number of synapse circuits 8 is small. The sum value W of such sum values W that is the largest among the plurality of analog circuits 3 is the maximum sum value W_max。

In the example shown in fig. 15, four input signal line pairs P6 and three analog circuits 3 are provided.In addition, four candidate weight values u_j＝(u₁、u₂、u₃、u₄) Is used as the weight value.

The left analog circuit 3 includes a positive synaptic circuit 8a having a weight value u in order from the top₁、u₂、u₃And u, and₄. The central analog circuit 3 comprises a pair of input signal lines P6 connected from the top and having a weight value u₂And a positive synaptic circuit 8a and a pair of third and fourth input signal lines P6 connected from the top and having a weight value of u₁And u₄The negative synaptic electrical circuit 8 b. The right analog circuit 3 comprises a negative synaptic circuit 8b, the negative synaptic circuit 8b being connected to the third and fourth pair of input signal lines P6 and having a weight value u₃And u₂. In these analog circuits 3, the sum W (═ u) of the weight values of the left analog circuit 3₁+u₂+u₃+u₄) Is the maximum sum value W_max。

It should be noted that the configuration of the arithmetic device 500 is not limited to the above-described configuration. For example, the number of synapse circuits 8 included in the analog circuit 3, the ratio of positive synapse circuits 8a and negative synapse circuits 8b, a candidate weight value set in each synapse circuit 8, and the like may be appropriately set to enable the target calculation to be performed. Further, the correlation between each input signal line pair P6 and the synapse circuit 8 may also be arbitrarily set.

The charging circuit 40 is configured by using a charging resistor 41 and a charging line 42 (refer to fig. 13). The charging resistor 41 is set to have a value according to the maximum sum value W_maxThe resistance value of (2). The charging resistor 41 is connected between each output line 7 (positive charge output lines 7a and 7b) of each analog circuit 3 and a charging line 42.

When the input period T starts, signal pairs are input into the respective synaptic circuits 8 via the plurality of input signal line pairs P6, and charges are output from the respective resistors. At the end timing T of the input period T_nHere, the accumulation of the electric charge corresponding to the sum of the product values is completed, and the voltage of the capacitor 13 becomes a voltage representing the multiplication-accumulation result. It should be noted that in the arithmetic device 500, a plurality of input signal line pairsP6 enters the off state after input period T.

When the input period T ends and the output period T starts, a charge signal is input into the charging line 42, and the voltage of the charging line 42 becomes a high level. Therefore, in the output period T, based on the charge signal input into the charging line 42, charges (currents) are generated through all the charging resistors 41, so that each capacitor 13 is charged. Since the charging resistor 41 is set to have a value according to the maximum sum value W_maxThe voltage of the capacitor 13 charged by the charging circuit 40 varies according to the expression (formula 17).

A threshold determination is performed for each charged capacitor 13 using a maximum sum value W_maxThe common threshold value θ calculated according to the expression (formula 16). Thus, a plurality of comparable multiply-accumulate signals can be generated simultaneously. As described above, even when a multi-valued weight is used and as the weight value v_iMay be different from each other by using the charging circuit 40 according to the same time constant T_WEach capacitor 13 is charged. Furthermore, the maximum sum value W can be obtained by_maxThe threshold value θ is set to properly calculate the multiply-accumulate result.

It should be noted that in the case of using a multi-valued weight, even if the number of synapse circuits 3 set in each analog circuit 3 is the same, it is not necessarily provided that the weight value v is provided therein_iThe sum value W of (a) is equal (the configuration in fig. 12). Even in this case, the charging circuit 40 is set and based on the maximum sum value W_maxSetting the charging time constant and the threshold value can also easily realize parallelization of the plurality of analog circuits 3.

On the other hand, even in the case where the number of synapse circuits 3 provided in each analog circuit 3 is different, in the configuration using the multi-valued weight, the weight value v in all analog circuits 3 may be made_iThe sum W of (a) is the same. In such a configuration, for example, the capacitor 13 may be charged directly from the plurality of input signal line pairs P6 without providing the charging circuit 40. In this case, since the sum value W is the same, it can be set atEach capacitor 13 is charged in a common charging mode. For example, such a configuration may be adopted.

As described above, in one or more of the analog circuits 3 in the arithmetic devices 100 to 500 according to the present embodiment, the positive weight charges and the negative weight charges are generated by converting the input value x into the corresponding one_iEach signal value of the signal pair of (1) is multiplied by a positive and negative weight value to generate and accumulated in the accumulation unit 11. The accumulation unit 11 is charged by the charging unit 15, and performs threshold determination on the voltage by using a predetermined threshold value θ, thereby outputting a positive-negative multiply-accumulate signal. Therefore, a circuit or the like for integrating the arithmetic operation result into one signal can be omitted. Further, in the one or more analog circuits 3, the charging by the charging unit 15 is performed in a common charging mode, and the common threshold θ is used for the threshold determination. Therefore, the operation of each analog circuit 3 can be appropriately performed at the same timing. As a result, the circuit configuration can be simplified, and high-speed arithmetic operation processing can be realized.

A method of generating a total multiply-accumulate signal representing a difference between positive and negative multiply-accumulate results can be conceived as a method of calculating the multiply-accumulate results. In this case, a logic circuit or the like for calculating the difference needs to be provided, and the circuit configuration may be complicated and power consumption may be increased. Further, when the difference between the output times of the positive and negative multiply-accumulate results is calculated and the difference is output, the accuracy of the calculation result may be degraded in a manner depending on the performance of the time resolution of the circuit for calculating the difference. Further, due to operational variations and environmental variations of transistors constituting a circuit for calculating the difference value, the accuracy of the final multiply-accumulate result may be deteriorated.

In this embodiment, positive and negative multiply-accumulate signals are output from the multiply-accumulate result of the analog circuit 3. These positive and negative multiply-accumulate signals can be used as input (signal pair) for the next layer as they are. Therefore, a differential circuit for generating a final multiply-accumulate signal from the positive and negative multiply-accumulate signals becomes unnecessary, and thus the circuit configuration can be simplified. Further, since the differential circuit is not provided, power consumption of the arithmetic device can be significantly reduced.

Further, in this embodiment, in the common charging mode, the charging process for reading the positive and negative multiply-accumulate result is performed in each analog circuit 3, and the positive and negative multiply-accumulate signals are generated by using the common threshold value θ. Time constant of charging T_WThe sum threshold θ is based on the maximum sum value W in the analog circuit 3_maxTo set. Thus, for example, appropriately normalized positive and negative multiply-accumulate signals can be output from all the analog circuits 3.

By making the charging mode and the threshold value θ common as described above, the analog circuit 3 in which the "signal pair" and the "weight pair" are used can be connected in parallel with the plurality of input signal line pairs P6. As a result, parallel operations of a plurality of "multiply-accumulate operations", that is, operations simultaneously performed with respect to one input at a time, can be performed, and high-speed operations and efficient operations according to the simulation method can be realized.

For example, a method called multi-layer perceptron (MLP) may be used in the algorithm for deep learning. The MLP may have, for example, a fully connected configuration, and need not perform special processing or the like between the multiply-accumulate operation of the previous stage and the multiply-accumulate operation of the subsequent stage. Therefore, if the process of calculating the final multiply-accumulate signal (the difference between the positive and negative multiply-accumulate results) after the multiply-accumulate operation can be reduced, a circuit for calculating the difference, and the like can be reduced. In this case, an MLP network having only a crossbar wiring structure and a comparator circuit using a resistor (resistor element) as a weight can be realized without providing an unnecessary circuit, and high-speed arithmetic operation processing can be performed with an extremely simplified circuit configuration.

< other examples >

The present technology is not limited to the above-described embodiments, and various other embodiments may be implemented.

The above mainly describes the case where the weight values of the positive weight and the negative weight constituting the weight pair (synapse circuit) are equal to each other. The present technology is not limited thereto, and the analog circuit may include a synapse circuit in which a positive weight and a negative weight are set as weight values different from each other. In this case, the sum total of the weight values of the positive weight lines is not always equal to the sum total of the weight values of the negative weight lines.

With such a configuration as well, for example, the multiply-accumulate result in all the analog circuits 3 in the output period can be calculated by setting the charge time constant and the threshold value based on the maximum value (maximum sum value) of the sum value of the weight values in each weight row connected to each input signal line pair. Thus, multiply-accumulate operations may be performed on multiple layers without delay.

In the above description, the charging time constant, the threshold value, and the like are set based on the voltage curve of the capacitor. The method of setting the charging time constant, the threshold value, and the like is not limited. For example, by linearly approximating the voltage change of the capacitor as described with reference to fig. 8 and the like, a charging time constant (charging rate), a threshold value, and the like can be set in accordance with a gradient or the like. Therefore, each parameter can be easily calculated. Further, the parameter for charging and the threshold θ may be set by using any method.

The parasitic capacitance of each synaptic circuit may be used as an accumulation unit. In this case, the parasitic capacitance of each synaptic circuit acts as a capacitor. For example, the arithmetic device is configured such that the combined capacitance of the parasitic capacitances has the same value in each analog circuit. Also in this case, the time constant and the threshold value can be set based on the maximum sum value and the combined capacitance, and the positive and negative multiply-accumulate signals can be output appropriately.

At least two of the features of the present technology described above may also be combined. In other words, various features described in the respective embodiments may be arbitrarily combined regardless of the embodiments. Further, the various effects described above are not restrictive, but merely illustrative, and other effects may be provided.

In this disclosure, "identical," "equal," "orthogonal," and the like are concepts that include "substantially identical," "substantially equal," "substantially orthogonal," and the like. For example, states included in a predetermined range (for example, a range of ± 10%) referred to as "identical", "identical orthogonal", and the like are also included.

It should be noted that the present technology can also take the following configuration.

(1) An arithmetic device comprising:

a plurality of input line pairs to each of which a signal pair corresponding to an input value is input in a predetermined input period; and

one or more multiply-accumulate devices, each device comprising

A plurality of multiplication units that are respectively connected to at least some of the input line pairs and are capable of generating each of a positive weight charge corresponding to a positive weight product value obtained by multiplying a signal value of one signal of the signal pair input to the input line pair to which the multiplication units are connected by a positive weight value and a negative weight charge corresponding to a negative weight product value obtained by multiplying a signal value of the other signal by a negative weight value,

an accumulation unit capable of accumulating the positive weight charges and the negative weight charges generated by each of the plurality of multiplication units,

a charging unit charging the accumulating unit, wherein a charge corresponding to the product value is accumulated after the input period, an

An output unit performing threshold determination on the voltage held by the accumulation unit using a predetermined threshold after the charging is started by the charging unit, thereby outputting a positive multiply-accumulate signal representing the sum of the positive weight product values and a negative multiply-accumulate signal representing the sum of the negative weight product values, wherein

In the one or more multiply-accumulate devices, the charging by the charging unit is performed in a common charging mode, and the common threshold is set to a predetermined threshold.

(2) The arithmetic device according to (1), wherein

The common charging mode includes charging according to a common time constant.

(3) The arithmetic device according to (1) or (2), wherein

The common charging mode includes charging based on a maximum sum value of a sum value of positive weight values and a sum value of an absolute value of a negative weight value, the maximum sum value being the largest in the one or more multiply-accumulate devices, the positive weight values and the negative weight values being set in the plurality of multiplication units.

(4) The arithmetic device according to (3), wherein

The common charging mode charges the accumulation unit according to the maximum sum value by a time constant.

(5) The arithmetic device according to (4), wherein

The plurality of input line pairs supply a charging signal that enters an on state after an input period, and

the charging unit charges the accumulation unit by accumulating the charges generated by the plurality of multiplication units based on the charging signal.

(6) The arithmetic device according to (4) or (5), wherein

The charging unit includes a resistor for charging and a charging line connected to the accumulation unit via the resistor for charging and supplying a charging signal that enters a conductive state after an input period.

(7) The arithmetic device according to (6), wherein

The resistor for charging is set to have a resistance value according to the maximum sum value.

(8) The arithmetic device according to (6) or (7), wherein

The plurality of input line pairs enter an off state after an input period, an

The charging unit charges the accumulation unit by accumulating charges generated by the resistor for charging based on the charging signal.

(9) The arithmetic device according to any one of (3) to (8), wherein

The common threshold is set based on the maximum sum value.

(10) The arithmetic device according to any one of (3) to (9), wherein

The common threshold is set based on a voltage curve representing a change over time of a voltage of the accumulation unit in a case where the accumulation unit is charged via a resistor having a resistance value according to a maximum sum value.

(11) The arithmetic device according to any one of (1) to (10), wherein

The absolute values of the positive weight value and the negative weight value are set to the same value for each of the plurality of multiplication units.

(12) The arithmetic device according to any one of (1) to (11), wherein

The absolute values of the positive weight value and the negative weight value are fixed to the same value.

(13) The arithmetic device according to any one of (1) to (12), wherein

The absolute values of the positive weight value and the negative weight value are set to any one of a plurality of values different from each other.

(14) The arithmetic device according to any one of (1) to (13), wherein

The one or more multiply-accumulate devices are a plurality of multiply-accumulate devices connected in parallel to the plurality of input line pairs.

(15) The arithmetic device according to (14), wherein

Setting a sum value of the positive weight values and a sum value of the absolute values of the negative weight values to a common sum value equal to each other in the multiply-accumulate apparatus, and

the plurality of multiply-accumulate devices include a common sum value set to the same value.

(16) The arithmetic device according to (14), wherein

Setting a sum value of the positive weight values and a sum value of the absolute values of the negative weight values to a common sum value equal to each other in the multiply-accumulate apparatus, and

the plurality of multiply-accumulate devices include a multiply-accumulate device including a common sum value different from each other.

(17) The arithmetic device according to any one of (1) to (16), wherein

The input value is represented by the sum of a positive value and a negative value,

the signal pair includes a positive signal having a positive value as a signal value and a negative signal having an absolute value of a negative value as a signal value, and

the plurality of multiplication units include at least one of a first multiplication unit that generates a positive weight charge by multiplying a signal value of a positive signal by a positive weight value and generates a negative weight charge by multiplying a signal value of a negative signal by a negative weight value, or a second multiplication unit that generates a positive weight charge by multiplying a signal value of a negative signal by a positive weight value and generates a negative weight charge by multiplying a signal value of a positive signal by a negative weight value.

(18) The arithmetic device according to (17), wherein

The plurality of input line pairs each include a positive input line to which a positive signal is input and a negative input line to which a negative signal is input,

one or more multiply-accumulate devices include a positive charge output line and a negative charge output line,

the first multiplication unit includes a resistor connected between the positive input line and the positive charge output line, the resistor defining a positive weight value and outputting a positive weight charge to the positive charge output line, and the first multiplication unit includes a resistor connected between the negative input line and the negative charge output line, the resistor defining a negative weight value and outputting a negative weight charge to the negative charge output line, and

the second multiplication unit includes a resistor connected between the negative input line and the positive charge output line, the resistor defining a positive weight value and outputting a positive weight charge to the positive charge output line, and the second multiplication unit includes a resistor connected between the positive input line and the negative charge output line, the resistor defining a negative weight value and outputting a negative weight charge to the negative charge output line.

(19) The arithmetic device according to (18), wherein

The accumulation unit includes a positive charge accumulation unit connected to the positive charge output line and accumulating positive weight charges and a negative charge accumulation unit connected to the negative charge output line and accumulating negative weight charges,

the charging unit charges each of the positive charge accumulation unit and the negative charge accumulation unit, and

the output unit performs threshold determination on the positive charge accumulation unit using the common threshold value to output a positive multiply-accumulate signal, and performs threshold determination on the negative charge accumulation unit using the common threshold value to output a negative multiply-accumulate signal.

(20) A multiply-accumulate system, comprising:

a plurality of input line pairs into each of which a signal pair corresponding to an input value is input in a predetermined input period;

a plurality of analog circuits, each analog circuit comprising

A plurality of multiplication units that are respectively connected to at least some of the input line pairs and are capable of generating each of a positive weight charge corresponding to a positive weight product value obtained by multiplying a signal value of one signal of the signal pair input to the input line pair to which the multiplication units are connected by a positive weight value and a negative weight charge corresponding to a negative weight product value obtained by multiplying a signal value of the other signal by a negative weight value,

an accumulation unit capable of accumulating the positive weight charges and the negative weight charges generated by each of the plurality of multiplication units,

a charging unit charging the accumulating unit, wherein a charge corresponding to the product value is accumulated after the input period, an

An output unit that performs threshold determination on the voltage held by the accumulation unit using a predetermined threshold after the start of charging by the charging unit, thereby outputting a positive multiply-accumulate signal representing the sum of the positive weight product values and a negative multiply-accumulate signal representing the sum of the negative weight product values; and

network circuit configured by connecting a plurality of analog circuits, wherein

In the plurality of analog circuits, charging by the charging unit is performed in a common charging mode, and a common threshold is set to a predetermined threshold.

List of reference signs

3. 3a, 3b analog circuit

P6 input signal line pair

6a positive input signal line

6b negative input signal line

7 output line

7a positive charge output line

7b negative charge output line

8 synaptic electrical circuits

8a positive synaptic circuit

8b negative synaptic circuit

11 accumulation unit

12 signal output unit

13a capacitor

13b capacitor

15 charging unit

17 resistor

17a first resistor

17b second resistor

17c third resistor

17d fourth resistor

40 charging circuit

41 resistor for charging

42 charging wire

100. 200, 300, 400, 500 arithmetic devices.