阅读说明：本技术 驱动电路 (Driving circuit ) 是由 C·L·斯塔尔 E·马尔舒瓦 A·S·多伊 J·L·梅兰森 于 2020-03-27 设计创作，主要内容包括：用于在第一采样速率下基于数字参考信号用驱动输出信号驱动机电负载的驱动电路,所述驱动输出信号在所述机电负载处感应出第一电量,所述驱动电路包括：功能块,所述功能块被配置来基于所述第一电量在大于所述第一采样速率的第二采样速率下以数字方式确定调整信号,所述调整信号指示由于所述第一电量而将在所述驱动电路的目标输出阻抗处感应出的第二电量；以及驱动器,所述驱动器被配置来基于所述参考信号和所述调整信号生成所述驱动输出信号,以致使所述驱动输出信号表现得好像所述驱动电路的输出阻抗已被调整为包括所述目标输出阻抗一样,其中所述第一电量是电流并且所述第二电量是电压,或者反之亦然。(A drive circuit for driving an electromechanical load with a drive output signal at a first sampling rate based on a digital reference signal, the drive output signal inducing a first amount of power at the electromechanical load, the drive circuit comprising: a function block configured to digitally determine, based on the first quantity of power, an adjustment signal at a second sampling rate that is greater than the first sampling rate, the adjustment signal indicating a second quantity of power to be induced at a target output impedance of the drive circuit as a result of the first quantity of power; and a driver configured to generate the drive output signal based on the reference signal and the adjustment signal to cause the drive output signal to behave as if an output impedance of the drive circuit has been adjusted to include the target output impedance, wherein the first quantity of electricity is a current and the second quantity of electricity is a voltage, or vice versa.)

1. A drive circuit for driving an electromechanical load with a drive output signal at a first sampling rate based on a digital reference signal, the drive output signal inducing a first amount of power at the electromechanical load, the drive circuit comprising:

a function block configured to digitally determine, based on the first quantity of power, an adjustment signal at a second sampling rate higher than the first sampling rate, the adjustment signal indicating a second quantity of power to be induced at a target output impedance of the drive circuit as a result of the first quantity of power; and

a driver configured to generate the drive output signal based on the reference signal and the adjustment signal to cause the drive output signal to behave as if an output impedance of the drive circuit has been adjusted to include the target output impedance,

wherein the first electrical quantity is a current and the second electrical quantity is a voltage, or vice versa.

2. The drive circuit of claim 1, wherein:

the drive output signal is a voltage signal, the first amount of power is a current drawn by the electromechanical load, and the second amount of power is a voltage across the target output impedance; or

The drive output signal is a current signal, the first amount of power is a voltage across the electromechanical load, and the second amount of power is a current drawn by the target output impedance.

3. The drive circuit according to claim 1 or 2, wherein the functional block is configured to determine the adjustment signal digitally based on the first electrical quantity and a definition of the target output impedance.

4. A driver circuit according to claim 3, wherein the definition comprises one or more configuration values.

5. The drive circuit of claim 4, comprising: a storage device to store the one or more configuration values, wherein an impedance value of the target output impedance is maintained while maintaining the one or more configuration values stored in the storage device.

6. The drive circuit according to claim 4 or 5, wherein:

a target equivalent circuit representing the target output impedance comprises one or more impedance components and a circuit structure for connecting the one or more impedance components together; and is

The one or more configuration values define at least one of the impedance component and/or the circuit structure.

7. The drive circuit of claim 6, wherein:

the target equivalent circuit includes a plurality of impedance components connected together; and is

The function block is configured to, based on the first amount of power and the one or more configuration values:

determining a plurality of adjustment sub-signals, each adjustment sub-signal representing a corresponding portion of the target equivalent circuit and indicating a portion of the second electrical quantity that would be induced at the corresponding portion of the target equivalent circuit if the second electrical quantity were induced at the target equivalent circuit; and is

Determining the adjustment signal by combining the plurality of adjustment sub-signals,

and optionally wherein:

if the second amount of power is the voltage across the target output impedance, then the portion of the second amount of power is the voltage across the corresponding portion of the target equivalent circuit; and is

If the second amount of power is the current drawn by the target output impedance, then the portion of the second amount of power is the current drawn by the corresponding portion of the target equivalent circuit.

8. The drive circuit according to claim 6 or 7, wherein:

the one or more configuration values define the target equivalent circuit as comprising at least one of a series resistor, a series capacitor, a series inductor, and a parallel impedance network comprising at least two of a parallel resistor, a parallel capacitor, and a parallel inductor connected together in parallel, each of those resistors, capacitors, and inductors being the impedance component,

optionally wherein those of the series resistor, the series capacitor, the series inductor and the parallel impedance network present in the target equivalent circuit are connected in series.

9. The drive circuit of claim 8, wherein the one or more configuration values define the target equivalent circuit to optionally include only:

the series resistor, wherein the series resistor has a negative resistance;

the series resistor and the series inductor connected together in series, wherein the series resistor has a negative resistance and the series inductor has a negative inductance;

the series resistor and the series inductor connected together in series and to the parallel impedance network, wherein the series resistor has a negative resistance and the series inductor has a negative inductance, and wherein the parallel impedance network comprises the parallel resistor, the parallel capacitor, and the parallel inductor connected together in parallel;

the series resistor and the series capacitor connected together in series, wherein the series resistor has a negative resistance and the series capacitor has a positive capacitance; or

The series resistor, wherein the series resistor has a positive resistance, and wherein the positive resistance is substantially greater than a resistance of the electromechanical load, or a resistance of a resistor in the electromechanical load equivalent circuit representing a mechanical impedance of the electromechanical load.

10. A drive circuit according to any preceding claim, comprising: a controller configured to:

generating the reference signal based on a drive input signal and based on a current drawn by the electromechanical load and/or a voltage across the electromechanical load; and/or

Controlling the definition of the target output impedance based on the current drawn by the electromechanical load and/or the voltage across the electromechanical load to cause a performance, such as a mechanical performance, of the electromechanical load to meet a performance target; and/or

Controlling the definition of the target output impedance based on the current drawn by the electromechanical load and/or the voltage across the electromechanical load to cause the target output impedance to cancel an impedance of at least one electrical component of the electromechanical load, optionally a coil such as a voice coil; and/or

Controlling the definition of the target output impedance based on an impedance control signal to cause the performance of the drive circuit to vary with the impedance control signal.

11. A drive circuit according to any preceding claim, wherein the driver is configured to generate the drive output signal such that the drive output signal has a predefined relationship to the sum of the adjustment signal and the reference signal.

12. The drive circuit according to any of the preceding claims, wherein:

the functional block is configured to generate a control signal having a predefined relationship to a sum of the adjustment signal and the reference signal; and is

The driver is configured to generate the drive output signal such that the drive output signal has a predefined relationship with the control signal.

13. The drive circuit of claim 12, wherein:

the drive circuit is selectively operable in an impedance drive mode or a current drive mode;

generating the control signal based on the reference signal and the adjustment signal such that the drive output signal behaves as if the output impedance of the drive circuit has been adjusted to include the target output impedance when the drive circuit is in the impedance drive mode; and is

In the current drive mode, the functional block is configured to generate the control signal in dependence on a current control reference signal and a current drawn by the electromechanical load, and to adjust the control signal based on the current drawn by the electromechanical load such that the current drawn by the electromechanical load has a predefined relationship to the current control reference signal.

14. The drive circuit according to claim 12 or 13, wherein:

at least one of the control signal and the adjustment signal is a digital signal;

the control signal and the adjustment signal are digital signals and the functional block is a digital functional block; and/or

The drive output signal is an analog signal.

15. The drive circuit according to any one of claims 12 to 14, wherein:

the control signal is a digital signal; and is

The driver includes a digital-to-analog converter and an analog amplifier connected together to convert the control signal to an analog signal and then amplify the analog signal to form the drive output signal.

16. A drive circuit according to any preceding claim, comprising: a monitoring unit configured to generate a current monitoring signal indicative of a current drawn by the electromechanical load and/or a voltage monitoring signal indicative of a voltage across the electromechanical load, wherein the functional block is configured to digitally determine the adjustment signal based on the current monitoring signal and/or the voltage monitoring signal.

17. The drive circuit according to any of the preceding claims, wherein:

the reference signal is indicative of an expected mechanical property of the electromechanical load; and/or

The behavior of the drive output signal as if the output impedance of the drive circuit had been adjusted to include the target output impedance is an expected behavior relative to an expected drive output signal expected to be generated by the driver based on the reference signal in the absence of the adjustment signal; and/or

The driver circuit comprises one or more analog impedance components connected to contribute to the output impedance of the driver circuit; and/or

The target output impedance is configured to cancel the impedance of at least one electrical component of the electromechanical load, optionally a ground coil such as a voice coil; and/or

The electromechanical load is an electromechanical device, such as an actuator; and/or

The electromechanical load is a resonant electromechanical load such as a linear resonant actuator, a loudspeaker or a micro-loudspeaker.

18. The drive circuit according to any of the preceding claims, wherein:

the driver forms part of a first control loop operable to control the drive output signal based on the reference signal;

the driver and the functional block forming part of a second control loop operable to control the drive output signal based on a current drawn by the electromechanical load and/or a voltage across the electromechanical load; and is

The second control loop is configured to have a lower delay than the first control loop.

19. The drive circuit of claim 18, wherein at least a portion of the first control loop and at least a portion of the second control loop are implemented as digital circuits, and wherein the delays of the first control loop and the second control loop are defined by sampling rates of respective digital signals of the first control loop and the second control loop.

20. A drive circuit according to any preceding claim, comprising: an analog impedance configured to form a portion of the output impedance of the drive circuit,

optionally wherein the analog impedance is a controllable analog impedance and the functional block is configured to control the controllable analog impedance to adjust the output impedance of the drive circuit.

21. The driver circuit of claim 20, configured to control a definition of the target output impedance and/or an impedance of the analog impedance to control the output impedance of the driver circuit.

22. The driver circuit according to any of the preceding claims, implemented as an integrated circuit, such as on an IC chip.

23. An IC chip comprising a driver circuit as claimed in any preceding claim.

24. A control system, comprising:

a drive circuit according to any one of claims 1 to 22; and

the electro-mechanical load is a load of the machine,

wherein the electromechanical load is connected to be driven by the drive output signal.

25. A haptic system comprising the control system of claim 24, wherein the electromechanical load is a linear resonant actuator coupled to a physical structure or surface of the system to produce a haptic effect for a user.

26. A host device, such as a portable electrical or electronic device, comprising a driver circuit according to any one of claims 1 to 22, or an IC chip according to claim 23, or a control system according to claim 24, or a haptic system according to claim 25.

27. A method performed by a drive circuit to drive an electromechanical load with a drive output signal that induces a first amount of power at the electromechanical load based on a digital reference signal, the method comprising:

digitally determining an adjustment signal based on the first quantity of power at a second sampling rate that is higher than the first sampling rate, the adjustment signal indicating a second quantity of power that would be induced at a target output impedance of the drive circuit as a result of the first quantity of power; and

generating the drive output signal based on the reference signal and the adjustment signal to cause the drive output signal to behave as if the output impedance of the drive circuit had been adjusted to include the target output impedance,

wherein the first electrical quantity is a current and the second electrical quantity is a voltage, or vice versa.

28. A drive circuit for driving an electromechanical load with a drive output signal, the drive circuit comprising:

a first control loop operable to control the drive output signal based on a drive input signal; and

a second control loop operable to control the drive output signal based on a current flowing through the electromechanical load and/or a voltage induced across the electromechanical load,

wherein the second control loop is configured to have a lower delay than the first control loop.

29. A drive circuit for driving an electromechanical load with a drive output signal based on a reference signal, the drive circuit being configured to digitally control the drive output signal based on the reference signal so as to cause the drive output signal to behave as if the output impedance of the drive circuit has been adjusted to include a predefined or predetermined target output impedance.

Technical Field

The present disclosure relates generally to drive circuits, and in particular to drive circuits for use in driving electromechanical loads or devices. One example of an electromechanical load (electromechanical device) is an actuator, such as a Linear Resonant Actuator (LRA).

The present disclosure extends to methods performed by such drive circuits, as well as systems, such as haptic systems, including such drive circuits.

Background

The drive circuit may be implemented within a host device (host apparatus) (at least partially on an IC), which may be considered an electrical or electronic device and may be a mobile device. Exemplary host devices include portable and/or battery powered host devices such as mobile phones, smart phones, audio players, video players, PDAs, mobile computing platforms such as laptops or tablets, and/or gaming devices.

Haptic technology is well known to reproduce the sense of touch by applying force, vibration or motion to a user. Haptic devices (haptic technology enabled devices) may incorporate a tactile sensor (input transducer) that measures a force imparted by a user to a user interface, such as a button or touchscreen on a mobile phone or tablet computer, and an output transducer (electromechanical load) that applies a force to the user, either directly or indirectly (e.g., via the touchscreen). Taking the haptic system as an example, in the case where the LRA acts as an electromechanical load, a driver circuit may be employed to drive the LRA to produce haptic effects (such as vibrations or other haptic sensations) for the user. Audio-to-haptic conversion may also be employed, for example, in conjunction with a user playing a video game, to convert an audio signal into a corresponding haptic signal to provide a tactile sensation (output via an electromechanical load such as an LRA) along with the audio signal (output via a speaker).

The main components of the LRA are the voice coil, the movable magnetic mass, the spring and the housing or chassis. The magnetic mass is connected to a spring which is in turn mounted to the housing or chassis of the LRA. The AC voltage signal (drive signal) is used to drive a voice coil arranged to magnetically couple with the movable magnetic mass.

The LRA typically generates an oscillating force or vibration along the axis. When the voice coil is driven with an AC voltage signal (particularly at the resonant frequency of the spring-mass arrangement), the resulting magnetic field causes movement in the magnetic mass and causes it to vibrate with a human-perceptible force. It is the vibration of the mass under an appreciable force that provides the haptic effect. Essentially, the frequency and amplitude of the AC voltage signal is converted to the vibrational frequency and amplitude of the magnetic mass connected to the spring. The LRA is thus in the form of a transducer. The LRA is typically highly resonant and thus typically driven at its resonant frequency to improve efficiency, i.e., to optimize the relationship between haptic effects and power consumption.

Of course, the LRA is one exemplary type of electromechanical load (as an actuator or transducer) that is particularly suited for generating haptic effects for a user in the context of a host device as mentioned above. The drive circuit may be used to drive other types of electromechanical loads (electromechanical devices), which may be modeled as, for example, resonant actuators such as speakers or micro-speakers or solenoid or voice coil motors with non-resonant mechanical loads such as non-resonant.

The example of driving the LRA will proceed as a convenient running example herein forward in the context of a haptic system.

Accuracy in controlling actuators and transducers is important, for example, in the field of haptic technology (e.g., haptic feedback). For example, the quality of the user haptic experience is defined by the accuracy of controlling the LRA in the case of using the LRA.

Accordingly, it is desirable to provide an improved drive circuit to improve control (e.g., mechanical control) of an electromechanical load driven by the circuit.

Disclosure of Invention

According to a first aspect of the present disclosure, a drive circuit is provided for driving an electromechanical load with a drive output signal at a first sampling rate based on a digital reference signal, the drive output signal inducing a first amount of power at the electromechanical load. The drive circuit includes: a function block configured to digitally determine, based on the first quantity of power, an adjustment signal at a second sampling rate that is greater than the first sampling rate, the adjustment signal indicating a second quantity of power to be induced at a target output impedance of the drive circuit as a result of the first quantity of power; and a driver configured to generate the drive output signal based on the reference signal and the adjustment signal to cause the drive output signal to behave as if the output impedance of the drive circuit has been adjusted to include the target output impedance. The first electrical quantity is a current and the second electrical quantity is a voltage, or vice versa.

By digitally determining the adjustment signal, it is possible to cause the drive output signal to behave as if the output impedance of the drive circuit has been adjusted to include a target output impedance in a highly adaptable and controllable manner. Furthermore, by digitally determining the adjustment signal at a second sampling rate higher than the first sampling rate, the target output impedance is achieved over a relatively wide bandwidth.

The drive output signal may be a voltage signal (voltage mode control). In this case, the first quantity of electricity may be a current drawn by the electromechanical load, and the second quantity of electricity may be a voltage across the target output impedance.

The drive output signal may be a current signal (current mode control). In this case, the first quantity of power may be a voltage across the electromechanical load, and the second quantity of power may be a current drawn by the target output impedance.

The function block may be configured to digitally determine the adjustment signal based on the first amount of power and a definition of the target output impedance. For example, a definition may include one or more configuration values. The drive circuit may comprise (or have access to) a storage means for storing the one or more configuration values, wherein the impedance value of the target output impedance is maintained while maintaining the one or more configuration values stored in the storage means. That is, the impedance value of the target output impedance may depend on the configuration value.

The (hypothetical) target equivalent circuit representing the target output impedance may comprise one or more impedance components and a circuit structure for connecting the one or more impedance components together. The one or more configuration values may define at least one impedance component and/or circuit structure.

The target equivalent circuit may include a plurality of impedance components connected together. The function block may be configured to, based on the first amount of power and the one or more configuration values: determining a plurality of adjustment sub-signals, each adjustment sub-signal representing a corresponding portion of the target equivalent circuit and indicating a portion of the second electrical quantity that would be induced at the corresponding portion of the target equivalent circuit if the second electrical quantity were induced at the target equivalent circuit; and determining the adjustment signal by combining the plurality of adjustment sub-signals.

The portion of the second electrical quantity may be a voltage across the corresponding portion of the target equivalent circuit if the second electrical quantity is a voltage across a target output impedance. If the second amount of power is the current drawn by the target output impedance, the portion of the second amount of power may be the current drawn by the corresponding portion of the target equivalent circuit.

The one or more configuration values may define the target equivalent circuit to include at least one of a series resistor, a series capacitor, a series inductor, and a parallel impedance network. The parallel impedance network may include at least two of a parallel resistor, a parallel capacitor, and a parallel inductor connected together in parallel. Each of those resistors, capacitors, and inductors may be considered the impedance component.

Those of the series resistor, the series capacitor, the series inductor and the parallel impedance network that are present in the target equivalent circuit may be connected in series, for example, where the second quantity of power is the voltage across the target output impedance.

The one or more configuration values may define the target equivalent circuit to optionally include only: the series resistor, wherein the series resistor has a negative resistance (e.g., a positive resistance substantially equal in magnitude to a voice coil of the electromechanical load).

The one or more configuration values may define the target equivalent circuit to optionally include only: the series resistor and the series inductor connected together in series, wherein the series resistor has a negative resistance (e.g., a positive resistance substantially equal in magnitude to a voice coil of an electromechanical load) and the series inductor has a negative inductance (e.g., a positive inductance substantially equal in magnitude to the voice coil of the electromechanical load).

The one or more configuration values may define the target equivalent circuit to optionally include only: the series resistor and the series inductor connected together in series and to the parallel impedance network, wherein the series resistor has a negative resistance and the series inductor has a negative inductance, and wherein the parallel impedance network comprises the parallel resistor, the parallel capacitor, and the parallel inductor connected together in parallel.

The one or more configuration values may define the target equivalent circuit to optionally include only: the series resistor and the series capacitor connected together in series, wherein the series resistor has a negative resistance and the series capacitor has a positive capacitance.

The one or more configuration values may define the target equivalent circuit to optionally include only: the series resistor, wherein the series resistor has a positive resistance, and wherein the positive resistance is substantially greater than a resistance of the electromechanical load, or a resistance of a resistor in the electromechanical load equivalent circuit representing a mechanical impedance of the electromechanical load.

The drive circuit may include a controller. The controller may be configured to: the reference signal is generated based on a drive input signal and based on a current drawn by the electromechanical load and/or a voltage across the electromechanical load. The controller may be configured to: controlling the definition of the target output impedance based on the current drawn by the electromechanical load and/or the voltage across the electromechanical load to cause a performance, such as a mechanical performance, of the electromechanical load to meet a performance target. The controller may be configured to: controlling the definition of the target output impedance based on the current drawn by the electromechanical load and/or the voltage across the electromechanical load to cause the target output impedance to cancel an impedance of at least one electrical component of the electromechanical load, optionally a coil, such as a voice coil. The controller may be configured to: controlling the definition of the target output impedance based on an impedance control signal to cause the performance of the drive circuit to vary with the impedance control signal.

The driver may be configured to generate the drive output signal such that the drive output signal has a predefined relationship to a sum of the adjustment signal and the reference signal.

The functional block may be configured to generate a control signal having a predefined relationship to the sum of the adjustment signal and the reference signal. The driver may be configured to generate the drive output signal such that the drive output signal has a predefined relationship to the control signal.

The drive circuit is selectively operable in an impedance drive mode or a current drive mode. When the drive circuit is in the impedance drive mode, the control signal is generated based on the reference signal and the adjustment signal such that the drive output signal behaves as if the output impedance of the drive circuit has been adjusted to include the target output impedance (as mentioned earlier). In the current drive mode, the functional block may be configured to generate the control signal in dependence on a current control reference signal and the current drawn by the electromechanical load, and to adjust the control signal based on the current drawn by the electromechanical load such that the current drawn by the electromechanical load has a predefined relationship to the current control reference signal.

At least one of the control signal and the adjustment signal may be a digital signal. The control signals and adjustment signals may be digital signals, and the functional blocks may be digital functional blocks (e.g., implemented in digital hardware or in software running on a processor). The drive output signal may be referred to as an analog signal.

The control signal may be a digital signal. The driver may comprise a digital-to-analog converter and an analog amplifier connected together to convert the control signal to an analog signal and then amplify the analog signal to form the drive output signal.

The driving circuit may include: a monitoring unit configured to generate a current monitoring signal indicative of a current drawn by the electromechanical load and/or a voltage monitoring signal indicative of a voltage across the electromechanical load. The functional block may be configured to digitally determine the adjustment signal based on the current monitoring signal and/or the voltage monitoring signal.

The reference signal may be indicative of an expected mechanical property of the electromechanical load. The behavior of the drive output signal as if the output impedance of the drive circuit had been adjusted to include the target output impedance may be a desired behavior relative to a desired drive output signal that is desired to be generated by the driver based on the reference signal without the adjustment signal (or based on an adjustment signal having a zero value). The driver circuit may include one or more analog impedance components connected to contribute to the output impedance of the driver circuit. The target output impedance may be configured to cancel the impedance of at least one electrical component of the electromechanical load, optionally a coil such as a voice coil. The electromechanical load may be an electromechanical device, such as an actuator. The electromechanical load may be a resonant electromechanical load, such as a linear resonant actuator, a speaker or a micro-speaker.

The driver may be considered to form part of a first control loop operable to control the drive output signal based on the reference signal. The driver and functional block may be considered to form part of a second control loop operable to control the drive output signal based on the current drawn by the electromechanical load and/or the voltage across the electromechanical load. The second control loop may be configured to have a lower delay than the first control loop.

At least a portion of the first control loop and at least a portion of the second control loop may be implemented as digital circuits. The delays of the first control loop and the second control loop may be defined by the sampling rates of the respective digital signals of the first control loop and the second control loop.

The driving circuit may include: an analog impedance configured to form a portion of the output impedance of the drive circuit. The analog impedance may be a controllable analog impedance, and the functional block may be configured to control the controllable analog impedance to adjust the output impedance of the drive circuit. For example, the driver circuit may be configured to control the definition of the target output impedance and/or the impedance of the analog impedance to control the output impedance of the driver circuit.

The driver circuit may be implemented as an integrated circuit, such as on an IC chip.

According to a second aspect of the present disclosure, there is provided an IC chip comprising the driving circuit according to the aforementioned first aspect of the present disclosure.

According to a third aspect of the present disclosure, there is provided a control system comprising: the drive circuit according to the foregoing first aspect of the present disclosure; and the electromechanical load, wherein the electromechanical load is connected to be driven by the drive output signal.

According to a fourth aspect of the present disclosure, there is provided a haptic system comprising a control system according to the preceding third aspect of the present disclosure, wherein the electromechanical load is a linear resonant actuator (or other type of actuator) coupled to a physical structure or surface of the system to produce a haptic effect for a user.

According to a fifth aspect of the present disclosure, there is provided a host device, such as a portable electrical or electronic device, comprising a drive circuit according to the aforementioned first aspect of the present disclosure, or an IC chip according to the aforementioned second aspect of the present disclosure, or a control system according to the aforementioned third aspect of the present disclosure, or a haptic system according to the aforementioned fourth aspect of the present disclosure.

According to a sixth aspect of the present disclosure, there is provided a method performed by a drive circuit to drive an electromechanical load with a drive output signal based on a digital reference signal, the drive output signal inducing a first electrical quantity at the electromechanical load, the method comprising: digitally determining an adjustment signal based on the first quantity of power at a second sampling rate that is higher than the first sampling rate, the adjustment signal indicating a second quantity of power that would be induced at a target output impedance of the drive circuit as a result of the first quantity of power; and generating the drive output signal based on the reference signal and the adjustment signal to cause the drive output signal to behave as if the output impedance of the drive circuit has been adjusted to include the target output impedance, wherein the first quantity is a current and the second quantity is a voltage, or vice versa.

According to a seventh aspect of the present disclosure, there is provided a drive circuit for driving an electromechanical load with a drive output signal, the drive circuit comprising: a first control loop operable to control the drive output signal based on a drive input signal; and a second control loop operable to control the drive output signal based on a current flowing through and/or a voltage induced across the electromechanical load, wherein the second control loop is configured to have a lower delay than the first control loop.

The second control loop may be configured to control the drive output signal to compensate for an impedance of the electromechanical load. The second control loop may be configured to control the drive output signal such that the drive output signal behaves as if the output impedance of the drive circuit has been adjusted to include the target output impedance.

The drive output signal may be a voltage signal and the second control loop may be configured to perform its control on the drive output signal based on the voltage signal to be induced by the current across said target output impedance. The second control loop may be configured to determine an adjustment signal indicative of the voltage signal based on the current and control the drive output signal based on the adjustment signal.

The drive output signal may be a current signal, and the second control loop may be configured to perform its control on the drive output signal based on the current signal of the current to be induced by the voltage to flow through the target output impedance. The second control loop may be configured to determine an adjustment signal indicative of the current signal based on the voltage and control the drive output signal based on the adjustment signal.

According to an eighth aspect of the present disclosure, there is provided a drive circuit for driving an electromechanical load with a drive output signal based on a reference signal, the drive output signal inducing a first electrical quantity at the electromechanical load, the drive circuit comprising: a function block configured to digitally determine an adjustment signal based on the first quantity of power, the adjustment signal indicating a second quantity of power to be induced at a target output impedance of the drive circuit as a result of the first quantity of power; and a driver configured to generate the drive output signal based on the reference signal and the adjustment signal to cause the drive output signal to behave as if the output impedance of the drive circuit has been adjusted to include the target output impedance.

The drive output signal may be a voltage signal. In this case, the first quantity of electricity may be a current drawn by the electromechanical load, and the second quantity of electricity may be a voltage across the target output impedance.

The drive output signal may be a current signal. In this case, the first quantity of electricity may be a voltage across the electromechanical load, and the second quantity of electricity may be a current drawn by the target output impedance.

According to a ninth aspect of the present disclosure, there is provided a drive circuit for driving an electromechanical load with a drive output signal based on a reference signal, the drive output signal being a voltage signal and causing a current to be drawn by the electromechanical load, the drive circuit comprising: a functional block configured to digitally determine an adjustment signal based on the current, the adjustment signal indicative of a voltage signal to be induced by the current across a target output impedance of the drive circuit; and a driver configured to generate the drive output signal based on the reference signal and the adjustment signal to cause the drive output signal to behave as if the output impedance of the drive circuit has been adjusted to include the target output impedance.

According to a tenth aspect of the present disclosure, there is provided a driving circuit for driving a linear resonant actuator, the driving circuit comprising: a function block configured to generate a digital control signal from a digital reference signal and a monitoring signal intended for controlling the linear resonant actuator; and a driver configured to convert the digital control signal into an analog drive signal to drive the linear resonant actuator, wherein: the monitoring signal is indicative of a current flowing through the linear resonant actuator and/or a voltage across the linear resonant actuator; and the functional block is configured to control a difference between the digital control signal and the digital reference signal based on the monitoring signal such that the analog drive signal has a target manifestation in driving the linear resonant actuator in which the analog drive signal behaves as if the output impedance of the drive circuit had been adjusted to include a target output impedance relative to a desired analog drive signal that is desired to be generated with a digital control signal as a digital reference signal.

According to an eleventh aspect of the present disclosure, there is provided a drive circuit for driving an electromechanical load with a drive output signal based on a reference signal, the drive circuit being configured to generate the drive output signal based on a digital operation from the reference signal and an amount of power induced at the electromechanical load, so as to cause the drive output signal to behave as if an output impedance of the drive circuit has been adjusted to include a target output impedance.

According to a twelfth aspect of the present disclosure, there is provided a drive circuit for driving an electromechanical load with a drive output signal based on a reference signal, the drive output signal inducing a first electrical quantity at the electromechanical load, the drive circuit comprising: a function block configured to digitally determine an adjustment signal based on the first quantity of power, the adjustment signal indicating a second quantity of power to be induced at a target output impedance of the drive circuit as a result of the first quantity of power; and a driver configured to generate the drive output signal based on the reference signal and the adjustment signal to cause the drive output signal to behave as if the output impedance of the drive circuit has been adjusted to include the target output impedance.

According to a thirteenth aspect of the present disclosure, there is provided a drive circuit for driving an electromechanical load with a drive output signal based on a reference signal, the drive circuit being configured to digitally control the drive output signal based on the reference signal so as to cause the drive output signal to behave as if the output impedance of the drive circuit has been adjusted to include a predefined or predetermined target output impedance.

According to a fourteenth aspect of the present disclosure, there is provided a drive circuit for driving an electromechanical load with a drive output signal based on a reference signal, the drive circuit being configured to digitally control the drive output signal based on the reference signal and an amount of power (a feedback signal indicative of the amount of power) at the electromechanical load (in response to the drive output signal) so as to cause the drive output signal to behave as if the output impedance of the drive circuit has been adjusted to include a predefined or predetermined target output impedance.

Method and computer program aspects corresponding to the circuit aspects are contemplated. The IC chip, control system, haptic system and host device system aspects are contemplated for each of the drive circuit aspects, similar to those specified above with respect to the first aspect.

Drawings

Reference will now be made, by way of example only, to the accompanying drawings in which:

FIG. 1 is a schematic diagram showing an equivalent circuit of a drive circuit that drives an LRA under open loop control;

FIG. 2 is a schematic diagram of an equivalent circuit corresponding to that of FIG. 1 but including a target output impedance;

fig. 3A to 3E are schematic diagrams showing equivalent circuits of specific configurations of the target output impedance of fig. 2;

FIG. 4 is a schematic diagram of a drive circuit according to one embodiment;

FIG. 5 is a schematic diagram of a drive circuit according to one embodiment;

FIG. 6 is a schematic diagram of a portion of the drive circuit of FIG. 5 according to a detailed implementation;

FIG. 7 is a schematic diagram of an exemplary implementation of a portion of the drive circuit of FIG. 4 for use in a current drive mode of operation;

FIG. 8 presents a series of graphs that may be used to understand the benefits and capabilities of the drive circuits disclosed herein;

FIG. 9A is a schematic diagram of the modified drive circuit of FIG. 2;

FIG. 9B is a schematic diagram corresponding to the modified drive circuit of FIG. 2 but using current source control rather than voltage source control; and is

FIG. 10 is a schematic diagram of a host device according to one embodiment.

Detailed Description

Before introducing the embodiments, the operation of the LRA will be considered in more detail. As above, the LRA is just a convenient type of electromechanical load or electromechanical device, which is of particular interest when considering haptic systems. It will be appreciated that the teachings herein are generally applicable to driving electromechanical loads, such as other types of actuators that may be used in a haptic system.

When the LRA is driven by a voltage across its two electrical terminals, current flows through or is drawn by the voice coil (inductor), generating an electromotive force (EMF) on the movable magnetic mass and thus controlling its motion. The movable magnetic mass is connected to a spring, which thus also influences its movement. Moving the magnetic mass in turn generates a back emf (bemf) voltage proportional to its velocity reflected at the electrical terminals. The setup is similar to a driving (damping) harmonic oscillator.

Accordingly, it is helpful to consider the driving of the LRA in electrical terms. Fig. 1 is a schematic diagram of an equivalent circuit 1 of a driving circuit that drives an LRA under open loop control, and graphs and equations that can be used to understand its operation.

The equivalent circuit 1 of fig. 1 comprises an AC voltage source (voltage amplifier) 10 connected to an LRA (electromechanical) load 20, the AC voltage source 10 modeling the drive circuit, the LRA load 20 modeling the LRA. For simplicity, LRA load 20 will be referred to herein as LRA20 only. The drive circuit 10 generates a reference voltage ref (drive signal), which ref appears across the LRA20 and induces a load current iload to be drawn by the LRA 20.

The LRA20 includes a coil impedance zcoil that models the voice coil; and a mechanical impedance zmech that models the movable mass and the spring arrangement. The coil impedance zcoil is modeled as an inductance le in series with a resistance re. The mechanical impedance zmech appears to be in series with the coil impedance zcoil and is modeled as a parallel network of capacitance cmes, inductance lces, and resistance res. Capacitance cmes models magnetic mass, inductance Ices models spring, and resistance res models mechanical damping. The bemf voltage appears across the mechanical impedance zmech as indicated (recall that the bemf voltage is induced by the moving magnetic mass).

The user haptic experience is defined by sensing the motion of the moving mass, and in particular the force generated by the acceleration of said moving mass (retrospective newton's second law, F ═ ma). Therefore, it is desirable to control the acceleration or proxy of the moving mass, such as the position or velocity of the moving mass (based on which the acceleration may be controlled). It is particularly desirable to control acceleration to produce one or more of the following: a) clear haptic effects (e.g., rapid acceleration and braking of mass, e.g., to mimic a click or button press); b) wide bandwidth effects (e.g., for audio to haptic or to replicate textures); and c) consistent effects (e.g., from LRA to LRA or changing environmental conditions). It is desirable to make the onset of the LRA's response to the tactile input pulse agile and reduce ringing of the LRA (and for example a smartphone screen in the context of surface audio/tactile applications) after the tactile input pulse has ceased.

The bemf voltage is proportional to the speed of the moving mass as mentioned above, however, control by the drive circuit as in fig. 1 controls the reference voltage ref, not the bemf voltage itself. Such open loop voltage drive produces a highly resonant behavior indicated by the graph in fig. 1.

In particular, the ref to bemf transfer function (bemfTF) of the driven LRA load is set by a voltage divider defined by zcoil and zmech as is apparent from the equivalent circuit of fig. 1. Similarly, the load current transfer function (iloadTF) is set by the series connection of zcoil and zmech. These relationships are expressed in the equations of FIG. 1, where zmech is denoted zBemf and zCoil is denoted zCoil.

Because the mechanical system is resonant with a high Q (quality factor) and the mechanical impedance is much smaller than the coil impedance (i.e., zmech > > zcoil), the ref to bemf transfer function bemfTF has a very narrow bandwidth. The velocity effectively follows zmech (expressed as zBemf) away from resonance (where zBemf < < zcoil), and such driving is only available in practice for simple vibration effects. In order to generate a large acceleration, the vibration frequency needs to be close to the resonance frequency.

The present inventors have considered adjusting the drive circuit 10 by adjusting its output impedance to achieve control of the LRA20 and in particular the bemf voltage.

Fig. 2 is a schematic diagram of an equivalent circuit 2, the equivalent circuit 2 corresponding to the equivalent circuit 1, except that a target output impedance 30 has been inserted between the AC voltage source (voltage amplifier) 10 and the LRA 20. The combination of the AC voltage source 10 and the target output impedance 30 is then referred to as a modified drive circuit 40, the drive output signal of which modified drive circuit 40, i.e. the drive voltage drv (drive signal), is provided at an output node 42 (between node 42 and ground) between the modified drive circuit 40 and the LRA load 20 to drive the LRA load 20 as indicated based on the reference signal ref. It should be noted that the target output impedance 30 is referred to in fig. 2 as a "virtual" impedance (as discussed in more detail later) and is provided along a current path that carries a load current iload flowing through or drawn by the LRA20 based on the drive voltage drv (drive output signal).

It is assumed in fig. 2 that the AC voltage source 10 itself is ideal (i.e. has zero output impedance). Thus, the target output impedance 30 may be considered the output impedance of the modified drive circuit 40. Of course, in practical implementations, the AC voltage source 10 may be non-ideal (i.e., it itself has a certain (albeit small) output impedance). In this case, the target output impedance 30 may be considered to be a portion (e.g., a substantial portion or a major portion) of the output impedance of the modified drive circuit 40. This may be represented in fig. 2 by a certain further impedance (not shown) in series between the AC voltage source 10 and the target output impedance 30, which may be taken into account when determining the desired target output impedance 30.

The target output impedance 30 is presented in equivalent circuit form in equivalent circuit 2 as comprising a series resistor ser _ r, a series capacitor ser _ c, a series inductor ser _ l and a parallel impedance network connected together in series. The parallel impedance network comprises a parallel resistor par _ r, a parallel capacitor par _ c and a parallel inductor par _ l which are connected together in parallel.

The target output impedance 30 is presented in fig. 2 as one example of how complex it may be to include all of these impedances as target output impedances. However, the inventors have considered variations in which some of these impedances are not, in fact, or actually present (i.e., absent or removed) to define a less complex target output impedance 30.

A variety of such variations are presented as examples in fig. 3A-3E. Each of the variations may be considered a particular configuration of the target output impedance 30 of fig. 2.

Fig. 3A is a schematic diagram of an equivalent circuit of a target output impedance 30A as a variation of the target output impedance 30, the target output impedance 30A including only the series resistor ser _ r. If the target output impedance 30 in fig. 2 is replaced with (or configured to form) the target output impedance 30A and the series resistance ser _ r is given the value-re (negative resistance), then it can be seen from fig. 2 that the series resistance ser _ r will then 'cancel' the series resistance re of the coil impedance zcoil (as if there were no impedance). An implementation of such a negative resistance will be explained later.

At low frequencies (e.g., <1kHz), the inductance le of the coil impedance zcoil is negligible and assumed to be absent. In this case, as is apparent from fig. 2, the reference voltage ref will appear across the mechanical impedance zmech such that the bemf voltage follows the reference voltage ref. This enables the bemf voltage itself, and thus the velocity of the magnetic mass of the LRA (and thus its acceleration, as well as the force or haptic effect generated by that acceleration), to be controlled with the reference voltage ref. For example, the reference voltage ref may take the form of a haptic signal, with the modified drive circuit 40 having a target output impedance 30A, thereby enabling a wider bandwidth control of the speed (or position or acceleration) of the LRA mass to produce the haptic effect of interest.

Incidentally, it should be noted in FIG. 3A that it may be desirable to assign a value of about (e.g., a deviation of up to 5% or about 1%) -re to the series resistance ser _ r. This is due to the following example: where the damping factor zeta _ LRA for an LRA is equal to 1 (i.e., to make the LRA critically damped), it is determined that ser _ r should be set to have a value of about 99% of-re. The skilled person will appreciate that in a given application, the value of ser _ r for critical damping can be found. Where the value-re is used later herein, it will be understood that this value may be adjusted in some arrangements to achieve critical damping. Critical damping is desirable to make the onset of the haptic pulse in the LRA (driven by means of the reference signal ref) agile and to reduce ringing of the LRA after the haptic pulse in the reference signal ref has ceased.

Fig. 3B is a schematic diagram of an equivalent circuit of a target output impedance 30B as a variation of the target output impedance 30, the target output impedance 30B including only a series resistance ser _ r and a series inductance ser _ l. If the target output impedance 30 in fig. 2 is replaced with (or configured to form) a target output impedance 30B, and the series resistance ser _ r and series inductance ser _ l are given respective values-re and-le (negative resistance and negative inductance), then the target output impedance 30B will then 'cancel' the coil impedance zcoil, as can be seen from fig. 2, even if the inductance le cannot be ignored at low frequencies. As is apparent from fig. 2, the reference voltage ref will again appear across the mechanical impedance zmech, with the bemf voltage following the reference voltage ref (but within a larger bandwidth than with the target output impedance 30A).

Fig. 3C is a schematic diagram of an equivalent circuit of a target output impedance 30C as a variation of the target output impedance 30, in which the series capacitance ser _ C has been omitted in the target output impedance 30C. In this case, it can be appreciated that the type of impedances and their interconnections in the target output impedance 30C "reflect" to some extent the type and interconnection of the LRA 20.

If the target output impedance 30 in fig. 2 is replaced with (or configured to form) a target output impedance 30C and the series resistance ser _ r and series inductance ser _ l are assigned respective values-re and-le (negative resistance and negative inductance), those components will again cancel out the coil impedance zcoil in terms of the target output impedance 30B. The parallel RLC section of the target output impedance 30C (i.e. the parallel resistance par _ r, the parallel capacitance par _ C and the parallel inductance par _ l) may then be used to cause the mechanical impedance zmech to appear electrically different from the AC voltage source 10, i.e. to effectively synthesize the required LRA load.

Fig. 3D is a schematic diagram of an equivalent circuit of a target output impedance 30D as a variation of the target output impedance 30, the target output impedance 30D including only a series resistor ser _ r and a series capacitor ser _ c. If the target output impedance 30 in fig. 2 is replaced with (or configured to form) the target output impedance 30D and the series resistance ser _ r is given the value-re (negative resistance) as previously described, the series resistance ser _ r will 'cancel' the series resistance re of the coil impedance zcoil (as if there were no impedance). The series capacitance ser _ c of the coil impedance zcoil and the inductance le then effectively form an LC resonant tank in series with the mechanical impedance zmech, which may increase damping to bring the magnetic mass of the LRA to a stop faster.

Fig. 3E is a schematic diagram of an equivalent circuit of a target output impedance 30E as a variation of the target output impedance 30, wherein the target output impedance 30E includes only the series resistance ser _ r as in fig. 3A, but wherein the series resistance ser _ r is given a value (e.g., ser _ r > > res and even ser _ r > > re) that is much larger (e.g., >10 times) than the resistance res of the mechanical impedance zmech. In this arrangement, the magnetic mass of the LRA is located proportional to the reference voltage ref at frequencies below resonance and its acceleration is proportional to the reference voltage ref at frequencies above resonance.

In this context, fig. 4 is a schematic diagram of a driving circuit 40A for driving the LRA20 according to one embodiment. As will become apparent, the drive circuit 40A implements a plurality of control loops.

The drive circuit 40A includes a functional block 50, a driver 60, and a controller 70. The controller 70 is optional-it may be provided separately from the driver circuit 40A (function block 50 and driver 60), for example, in some applications. The combination of functional block 50, driver 60 and controller 70 corresponds to modified circuit 40 and thus outputs its driving output signal at output node 42 to LRA20 for consistency with fig. 2. For convenience, drive circuit 40A is shown connected at output node 42 to drive LRA20, but it will be understood that drive circuit 40A need not actually include LRA20 (LRA 20 may be provided separately for connection to drive circuit 40A).

Generally, for convenience, digital signals will be referred to below using upper case letters (e.g., MON), and analog signals will be referred to in lower case letters (e.g., MON).

The functional block 50 is configured to generate the (digital) control signal CS from the (digital) reference signal RS and the (digital) monitoring signal MON (which-although not shown-may be generated from the corresponding analog monitoring signal MON). The reference signal RS is generated by the controller 70 and is intended for controlling the LRA 20. For example, the reference signal RS may exhibit a haptic pulse to be used to control the LRA 20. The reference signal RS may be indicative of (e.g. proportional to, or having a predefined, defined or linear relationship with) an expected mechanical property of the LRA20 (electromechanical load). In this sense, the controller 70 and the reference signal RS may be compared with the driving circuit 10 and the reference voltage ref, respectively.

The driver 60 is configured to convert the control signal CS into a (analog) driving output signal dos (voltage signal), which is output via the output node 42 to drive the LRA 20. The LRA20 draws a load current iload that is attributed to driving the output signal dos. The load current iload is thus the current (flowing) through the LRA 20. One or more of the reference signal RS (including any signal on which the reference signal RS is generated based), the control signal CS, and the drive output signal dos may be referred to as an actuation signal. Recall that LRA20 is an example of an electromechanical load or electromechanical device. The driver 60 may comprise a digital-to-analog converter (not shown) to convert the digital control signal CS into an analog control signal CS and an amplifier (also not shown) to amplify the analog control signal CS for generating the analog drive output signal dos.

The monitor signal MON may include a current monitor signal IMON indicative of (e.g., proportional to, or having a predefined, defined, or linear relationship with) the load current iload flowing through the LRA20 or being drawn by the LRA 20. The monitor signal MON may (additionally or alternatively) include a voltage monitor signal VMON indicative of a voltage induced across the LRA20 due to the current flowing through the LRA20 (effectively, a driving output signal dos, wherein the driving output signal dos is applied only across the LRA 20) (e.g., proportional, or having a predefined, defined, or linear relationship to the voltage). Thus, the drive circuit 40A may include a monitoring circuit 80 to monitor the current flowing through the LRA20 (and optionally also the voltage across the LRA) and to generate a monitoring signal MON (or its analog equivalent MON).

It should be emphasized that monitoring circuit 80 need not be part of (e.g., housed within) LRA20 and may actually be considered separate from LRA20, such that LRA20 may be provided without any sensing technology (i.e., it may be a "sensorless" LRA). This will become more apparent in conjunction with fig. 5 described below.

As schematically indicated with respect to the controller 70, the controller 70 is configured to generate the reference signal RS based on the driving input signal DIS. The drive input signal DIS may be generated within the controller 70 or received from a separate system or control (e.g., from an application processor). The drive input signal DIS may be generated within the controller 70 based on, for example, one or more received signals from a separate system or controller (e.g., from an application processor).

The controller 70 may be configured to receive the monitor signal MON or a portion thereof and to control one or more of its signals based on the monitor signal MON or a portion thereof. For example, the controller 70 may be configured to receive the current monitoring signal IMON and/or the voltage monitoring signal VMON and control one or more of the signals it generates based on the current monitoring signal IMON and/or the voltage monitoring signal VMON.

The controller 70 may be configured to generate the reference signal RS based on the current monitoring signal IMON and/or the voltage monitoring signal VMON. The current monitoring signal IMON and/or the voltage monitoring signal VMON may, for example, indicate a performance of the LRA20, such as its mechanical properties. The current monitoring signal IMON and the voltage monitoring signal VMON may together be used to assess, for example, the start of the response of the LRA20 to a tactile input pulse (expressed by the drive input signal DIS and/or the reference signal RS) or the degree of ringing of the LRA20 after the tactile input pulse has ceased. The current monitoring signal IMON and the voltage monitoring signal VMON may be used together to evaluate, for example, the resonant frequency f0, the quality factor Q, the impedance, and/or the operating state (including fault conditions) of the LRA 20. The current monitor signal IMON and the voltage monitor signal VMON may, for example, indicate the validity of the current (current or existing) configuration of the target output impedance 30 and indicate how the configuration should be changed to meet performance targets. The implementation of the target output impedance 30 in the driver circuit 40A is described in more detail below.

In this way, a first control loop may be formed, wherein the drive output signal dos is controlled based on the drive input signal DIS. In such a control loop, it can be understood that the monitoring signal MON (the current monitoring signal IMON and/or the voltage monitoring signal VMON) serves as a feedback signal for feedback control (by the controller 70) of the reference signal RS and thus also of the control signal CS and the drive output signal dos. This feedback control may be used to keep the performance of the LRA20 (as indicated by the current monitoring signal IMON and/or the voltage monitoring signal VMON, e.g., its mechanical performance) within performance limits.

The first control loop may also incorporate (by the controller 70) a feed forward control of the reference signal RS and thus also of the control signal CS and the drive output signal dos. There are a number of possibilities, for example, using high pass filtering to remove low frequency components that may result in inefficient driving of LRA20, or low pass filtering to handle false sounds that may be emitted by some real-life machinery integration or audio-to-haptic analyzers that convert audio content into haptic content. Of course, these are merely examples.

A second control loop may also be considered to be present, wherein the drive output signal dos is controlled based on the monitoring signal MON (current monitoring signal IMON and/or voltage monitoring signal VMON). In such a control loop, it can be understood that the monitor signal MON (in particular, the current monitor signal IMON) serves as a feedback signal for feedback control (by the functional block 50) of the control signal CS and thus also of the drive output signal dos. The control by the function block 50 will be described in more detail below.

A third control loop may also be considered to be present in which the function of the functional block 50 (described below) is controlled based on the monitor signal MON (the current monitor signal IMON and/or the voltage monitor signal VMON). In such a control loop, it can be appreciated that the monitor signals MON (in particular, the current monitor signal IMON and the voltage monitor signal VMON) serve as feedback signals for feedback control (by the controller 70) of the configuration signal CONFIG supplied to the functional block 50 to define or influence or control the operation thereof. As above, the control by the function block 50 will be described in more detail below.

A fourth control loop may also be considered to be present, wherein the function of the driver 60 is controlled based on the monitoring signal MON (the current monitoring signal IMON and/or the voltage monitoring signal VMON). In such a control loop, it can be understood that the monitoring signal MON (in particular the voltage monitoring signal VMON) serves as a feedback signal for feedback control of the drive output signal dos (by the driver 60), e.g. such that the drive output signal dos has a defined or predefined (e.g. linear, proportional or proportional) relationship with the control signal CS. This control may be used, for example, to achieve linear operation of the driver 60 (which may be considered an amplifier).

It will be apparent that it may be desirable to operate the various control loops with different (relative) delays. More particularly, it may be desirable to have a low delay for one or more of the control loops, e.g., so that analog operation is closely mimicked (across a bandwidth of interest-which may be, e.g., a haptic or audio bandwidth as mentioned later), while for one or more other of the control loops, it may be acceptable to operate with a higher delay (or desirable for power consumption and complexity considerations).

For example, the second control loop may have a lower delay than the first control loop and/or the third control loop. The fourth control loop may have a lower delay than the first control loop and/or the third control loop. The second control loop may have the same or substantially the same delay as the fourth control loop. The delay of the control loop may be defined by the sampling rate (update rate, response rate) of the corresponding digital signal of the control loop, as will become more apparent in connection with fig. 5 (described below). The term delay herein may thus describe how quickly (e.g., at what rate, speed, or frequency) a particular control loop responds to interference or control inputs.

The above control loops may be referred to as (or considered to encompass) control paths or control systems or control networks. Each of the control loops may incorporate one or more of feedback control, feedforward control, and open loop control.

In general, the functional block 50 controls the difference between the control signal CS and the reference signal RS so as to mimic the presence of a (simulated) target output impedance of the drive circuit 40A corresponding to the target output impedance 30 of fig. 2 (the impedance value of which may be set to configure the target output impedance 30 as, for example, any of the target output impedances 30A-30E). For convenience, the target output impedance that is modeled will simply be referred to as the target output impedance 30.

Because the functional block 50 controls the difference between the control signal CS and the reference signal RS in the digital domain (i.e., digitally using digital signals and digital operations/calculations), the relationship between the control signal CS and the reference signal RS may be configured (e.g., over time) to define and/or adjust the configuration of the target output impedance 30 (e.g., which of the target output impedances 30A-30E is being used). In this way, in the case of a haptic system, the response of LRA20 to reference signal RS may be controlled, enabling control of haptic effects (expressed by reference signal RS).

The functional block 50 is configured to digitally determine, based on the monitor signal MON (in particular, the current monitor signal IMON), an adjustment signal AS indicative of a voltage signal to be induced by the load current iload across the target output impedance 30 of the drive circuit 30 (i.e., in case the load current will flow through the target output impedance 30). Indeed, the function block 50 is configured to digitally determine (e.g., calculate) the adjustment signal AS based on the load current iload. The driver 60 is then configured to generate the drive output signal dos based on the reference signal RS and the adjustment signal AS (or based on a control signal CS which is itself generated based on the reference signal RS and the adjustment signal AS) such that the drive output signal dos behaves AS if the output impedance of the drive circuit has been adjusted to include the target output impedance 30.

In more detail, the functional block 50 is configured to control the relationship or difference between the control signal CS and the reference signal RS based on the monitor signal MON (in particular, the current monitor signal IMON). In particular, the functional block 50 controls the relationship such that the drive output signal dos (when driving the LRA 20) has a target behavior in which it behaves as if the output impedance of the drive circuit has been configured or adapted or adjusted to include (or simply include) a target output impedance, such as the target output impedance 30 (e.g., configured to form any of the variation patterns 30A-30E), relative to a desired analog drive output signal that is desired to be generated with the control signal CS as the reference signal RS (i.e., when CS ═ RS). It is desirable to generate a desired analog drive output signal in case the driver 60 generates the drive output signal dos based on the reference signal RS without the adjustment signal AS (in fact without control of the second control loop, which may be considered AS comprising the adjustment signal AS).

Thus, the functional block 50 adjusts the control signal CS relative to the reference signal RS such that the drive circuit 40A behaves as if its output impedance (measured at node 42) includes the target output impedance 30 (which otherwise does not include the target output impedance 30, i.e., when CS ═ RS). For example, where CS ═ RS, drive circuit 40A may be able to operate at zero output impedance (measured at node 42) due to operation of driver 60, in which case functional block 50 adjusts CS relative to RS based on IMON so that the output impedance of drive circuit 40A is substantially equal to the target output impedance.

In this sense, the functional block 50 mimics or simulates the presence of the target output impedance 30 by making adjustments (via the adjustment signal AS) in the signal path between the controller 70 and the driver 60 such that the output impedance of the drive circuit 40A appears to (and indeed does in fact) include the target output impedance 30. The target output impedance 30 in these terms may be considered a "virtual" impedance as mentioned earlier, since it is not achieved by providing analog discrete passive impedance components, but by means of signal conditioning determined (i.e. made or determined digitally) in the digital domain.

For example, the functional block 50 may be configured to receive and/or store one or more configuration values defining a target output impedance, and thus govern how the control signal CS is generated from the reference signal RS and the current monitoring signal IMON. The configuration values may be set by means of a third control loop based on a (digital) configuration signal CONFIG received from the controller 70 (as indicated in fig. 4).

Incidentally, instead of or in addition to the control by means of the third control loop, the (digital) configuration signal CONFIG may be controlled by a separate impedance control signal (not shown) received, for example, from a separate system. The configuration of the target output impedance may thus vary with (or be controlled or set by) a separate impedance control signal in this manner.

Returning to fig. 4, a useful example to understand the "virtual" aspect of the target output impedance 30 is where the target output impedance 30 is configured to form a target output impedance 30A, where its resistance ser _ r has a value-re (i.e., a negative resistance) as mentioned earlier. Referring to fig. 2, such a target output impedance 30A (negative resistance) may be expected to have a voltage rise (rather than a fall) across it in the direction from the driver circuit 10 to the LRA load 20, the voltage rise being defined by the product of the resistance value re and the current iload flowing through the LRA load 20 in that direction (recall ohm's law, V ═ IR).

Thus, in this example, the functional block 50 mimics the presence of the target output impedance 30A between the controller 70 and the driver 60 by adding an amount represented by the adjustment signal AS (based on the product of the resistance value re and the load current iload flowing through or drawn by the LRA load 20, AS indicated by the current monitoring signal IMON) to the reference signal RS to form the control signal CS (i.e., CS ═ RS + AS) such that the output resistance of the driver circuit 40A appears to (and does so) comprise the target output impedance 30A.

In this case, the adjustment signal AS may be considered AS a function of iload re or IMON re. In this way, the functional block 50 enables the negative resistance to be implemented digitally. The CONFIG signal may, for example, simply provide the value-re (or re) to the functional block 50 to define the series resistance ser _ r, possibly as well as other configuration values that define the target output impedance 30 as having the form of (or being configured as) the target output impedance 30A (rather than, for example, the target output impedance 30C).

The drive output signal dos is a voltage signal appearing across the LRA 20. The target behavior may then be defined by the manner of variation of the voltage level of the driving output signal dos when the LRA20 (or the voltage across the LRA 20) is driven with the current flowing through the LRA20 (i.e. the load current iload).

Incidentally, in the fig. 4 embodiment, the control signal CS, the reference signal RS, the adjustment signal AS and the monitor signal MON are present AS digital signals, AS a convenient implementation for enabling the functional block 50 to be considered a (fully) digital block. However, the control signal CS, the adjustment signal AS and the reference signal RS may for example be replaced by analog equivalent signals CS, AS and RS, respectively. In this case, the functional block 50 may digitally (e.g., by calculation or using a look-up table) figure out how to adjust the analog control signal cs (i.e., what the adjustment signal should be) relative to the analog reference signal rs to mimic or simulate the presence of the target output impedance 30. For example, the functional block 50 may digitally generate (e.g., by calculating or using a look-up table, followed by digital-to-analog conversion) a suitable analog adjustment signal that will be added in the analog domain to the analog reference signal rs to generate the analog control signal cs. It will be appreciated that by digitally calculating how to adjust the analog control signal cs relative to the analog reference signal rs, it is possible to achieve the target output impedance 30 (including in the form of a target output impedance 30A having a negative resistance) in an efficient and highly adaptable manner.

For convenience, the examples using the digital control signal CS, the digital adjustment signal AS, the digital reference signal RS and the digital monitor signal MON will proceed.

It was earlier mentioned that there may be one or more analog output impedances (e.g., discrete or parasitic components) in the drive circuit 40A. The target output impedance 30 may be configured to take this into account. For example, if there is some analog (positive) resistance of magnitude R1 (not shown) in the output impedance of the driver circuit 40A, and it is desired that the output impedance of the driver circuit 40A have a total resistance of magnitude-R2 (negative resistance), the target output impedance 30 (assuming the fig. 3A configuration) may be configured to take this into account by setting ser _ R — (R1+ R2), i.e., to compensate for (or allow for) the analog impedance R1.

As another example, the functional block 50 may be configured to control an analog variable impedance (discrete component — not shown) in a current path, such as the load current iload located between the output node 42 and the driver 60, such that the output impedance of the drive circuit 40A and the variable impedance (actual discrete impedance component) are controlled or adjusted in part. Again, the target output impedance 30 may be configured to take this into account, i.e., adjusted or configured to compensate for (or allow for) the variable impedance. For example, the impedance formed by (or equivalent to) the combination of the variable impedance and the target output impedance 30 may be controlled.

Fig. 5 is a schematic diagram of a drive circuit 40B for driving the LRA20 as a detailed exemplary implementation of the drive circuit 40A. Like elements and signals are denoted by like reference numerals and repeated description is omitted. The function block 50 is referred to as function block 50A in the implementation of fig. 5.

It will become apparent that in this detailed implementation, some digital signals have a relatively high sampling (update) rate and other digital signals have a relatively low sampling (update) rate, and this is indicated by the suffixes "(H)" and "(L)", respectively. In this way, some signals and corresponding control loops may be considered "fast" (or high bandwidth, or low delay), and some signals and corresponding control loops may be considered "slow" (or low bandwidth, or high delay), as mentioned earlier. Signals with low sampling rates may be considered to have the same sampling rate as one another, and signals with high sampling rates may similarly be considered to have the same sampling rate as one another, but this is not essential. Also, the various sampling rates may depend on the application and vary over time, for example.

The functional block 50A of the drive circuit 40B includes a current monitor ADC 510, a voltage monitor ADC 520, a current monitor decimator 530, a voltage monitor decimator 540, an Adjustment Signal (AS) determiner 550, an adder 560, and a limiter 570. The functional block 50A is a digital block (except for the analog front end portions of the ADCs 510 and 520) and may be implemented using "hardwired" circuits, logic gates, and/or a processor executing a computer program. For example, in some arrangements, the functional block 50A may be implemented as part of a controller 70, which controller 70 may be a processor or microprocessor such as a Digital Signal Processor (DSP). Thus, the division of the functional block 50A into interconnected components in fig. 5 may be considered as schematic and may be used to understand its function.

In some arrangements, the controller 70 may be considered part of the drive circuit 40B, for example, provided as part of the same integrated circuit as the other elements of the drive circuit 40B. In other arrangements, the controller 70 may be considered to be separate from the drive circuit 40B, for example, provided as an integrated circuit separate from the integrated circuit that includes the other elements of the drive circuit 40B.

It is assumed here that the monitoring circuit 80 is configured to monitor the current flowing through the LRA20 and output an analog current monitoring signal imon, and also monitor the voltage across the LRA20 and output an analog voltage monitoring signal vmon. It is also emphasized that monitoring circuit 80 may be separate from LRA20, where LRA20 is in this case shown connected across terminals 82 and 84 of monitoring circuit 80 (the terminals 82 and 84 may be considered as terminals of drive circuit 40B). Thus, the driver circuit 40B including the monitoring circuit 80 (but not including the LRA 20) may be implemented as an integrated circuit, e.g. on an IC chip, wherein the terminals 82 and 84 are (external) terminals of the integrated circuit.

As an example, the monitoring circuit 80 may comprise a resistor (not shown) connected in series with the LRA20, such as between the nodes 42 and 82 (the known resistance of which will be taken into account when evaluating the resistance re of the coil impedance zcoil), wherein the voltage across the resistor is proportional to the load current iload flowing through the LRA20 and thus forms the current monitoring signal imon. The voltage monitoring signal vmon may be formed from a load voltage vload taken across the LRA20 (e.g., across terminals 82 and 84). Of course, there are other ways to obtain the signals vmon and imon for the LRA 20.

The current monitor ADC 510 is connected to receive the analog current monitor signal imon and output a corresponding digital current monitor signal imon (h), i.e., having a high sampling rate. The current monitoring decimator 530 is connected to receive the current monitoring signal imon (h) and output a corresponding digital current monitoring signal imon (l), i.e., having a low sampling rate. The voltage monitoring ADC 520 is connected to receive the analog voltage monitoring signal vmon and output a corresponding digital voltage monitoring signal vmon (h), i.e., having a high sampling rate. The voltage monitoring decimator 540 is connected to receive the voltage monitoring signal vmon (h) and output a corresponding digital voltage monitoring signal vmon (l), i.e., having a low sampling rate. The decimator functions in this sense to reduce the sampling rate between its input and output signals, e.g., by outputting one input sample every few input samples or averaging over successive groups of samples.

Controller 70 is connected to receive signals imon (l) and vmon (l), AS determiner 550 is connected to receive signals imon (h), and driver 60 is connected to receive one or both of signals vmon and vmon (h). Assume that the controller comprises an interpolator 710, which interpolator 710 converts the digital reference signal rs (l) (i.e. at a low sample rate) into a corresponding digital reference signal rs (h) at a high sample rate. The interpolator acts in this sense to increase the sampling rate between its input signal and output signal, thereby passing through the generation of new samples by interpolation/estimation.

In general, the functional block 50A of the drive circuit 40B is configured to determine, based on the monitor signal MON and one or more configuration values defining the target output impedance 30, an adjustment signal as (h) to be applied to the reference signal rs (h) to form the control signal cs (h) and to cause the drive output signal dos to have a target behavior when driving the LRA20, and to generate the control signal cs (h) by applying the adjustment signal as (h) to the reference signal rs (h). It should be noted that this forms part of the second control loop, which is fast, has a low delay, uses a high sampling (update) rate digital signal, so that the driving output signal dos behaves (within a wide bandwidth) as if the target output impedance 30 had been implemented in analog form.

In detail, AS determiner 550 is configured to generate adjustment signal AS (h) based on signal imon (h) in a form to be added to reference signal rs (h) to form control signal cs (h). The adder 560 is configured to generate the control signal cs (h) by adding the adjustment signal as (h) to the reference signal rs (h). The control signal cs (h) is thus generated to have a defined or predefined (e.g., substantially linear, proportional, or proportional) relationship with the sum of the adjustment signal as (h) and the reference signal rs (h).

Effectively, AS determiner 550 determines (e.g., by calculation or using a look-up table) a voltage that would be induced across target output impedance 30 in the event that current flowing through LRA20 is to flow through target output impedance 30, and generates adjustment signal AS (h) to express this voltage such that adding adjustment signal AS (h) to reference signal rs (h) produces control signal cs (h). Thus, the adjustment signal as (h) may be considered to be indicative of (e.g., proportional to, or having a predefined, defined, or linear relationship with) the load voltage vload that would be induced across the target output impedance 30 if the load current iload flowing through the LRA20 were to flow through the target output impedance 30. In this way, the control signal cs (h), and thus the drive output signal dos, will respond to the load current iload as if the output impedance of the drive circuit 40B had been configured to include the target output impedance 30.

Limiter 570 functions to limit (i.e., remain within limits) the value of control signal cs (h), for example, such that its value is within the linear operating range of driver 60 (e.g., a DAC and/or an analog amplifier of driver 60). As part of a fourth control loop, which is fast like the second control loop, the driver 60 is configured to control the drive output signal dos such that its voltage level has a defined or predefined (e.g. substantially linear, proportional or proportional) relationship with the control signal cs (h) by means of one or both of the signals vmon (h) and vmon as indicated. The limiter 570 is optional in some arrangements.

It should be noted that the controller 70 is connected to receive the monitoring signal MON in the form of a digital current monitoring signal imon (l) and a voltage monitoring signal vmon (l), both having a low sampling rate. Thereby, the first control loop generates the reference signal rs (l) based on the drive output signal dis (l) as indicated, thereby acting as a relatively slow control loop. Interpolator 710 converts reference signal rs (l) into a corresponding reference signal rs (h) for use in the second control loop and the fourth control loop as already mentioned being fast control loops. Further, the third control loop generates a configuration signal config (l) (i.e., having a low sample rate) to be used by the functional block 50A (in particular, the AS determiner 550) to define the target output impedance 30 (i.e., by means of one or more configuration values) to act AS a relatively slow control loop.

The first control loop and the third control loop may, for example, only need to respond to relatively slow (low frequency) disturbances, such as temperature changes of the LRA 20. On the other hand, the second control loop and the fourth control loop may require very low latency to mimic or simulate analog performance (within a given bandwidth).

Looking further at the first control loop and the third control loop, it will be appreciated that the controller 70 accesses the monitor signal MON in the form of a digital current monitor signal imon (l) and a voltage monitor signal vmon (l), as mentioned earlier. Based on these signals, controller 70 may be configured in some arrangements to partially or fully determine or estimate the configuration of LRA20, e.g., to determine (see fig. 2) the impedance values (or estimate their impedance values) of some or all of the values re, le, cmes, lces, and res. Analysis of the digital current monitoring signal imon (l) and the voltage monitoring signal vmon (l) may also enable determination or estimation of the resonant frequency f0 or the quality factor Q of the LRA 20.

This information may be used to define or update the configuration of the target output impedance 30 via the config (l) signal and/or to control parameters of the reference signal rs (l). One example may be to determine or estimate the value of the coil resistance re (see fig. 2) in order to set or update (e.g., improve) the value of the series resistance ser _ r for the target output impedance 30 (e.g., in the case of the fig. 3A configuration). Another example is to use an estimated or determined value of the resonance frequency f0 to control the reference signal rs (l) such that the LRA20 is driven very efficiently in terms of power consumption (e.g. at resonance) by the driving output signal dos.

Of course, some of this defining/updating/controlling may be based on preset values or input control signals (e.g., received from another system or user). The present disclosure will be understood accordingly. For example, the value of the resonance frequency f0 and/or the quality factor Q of the LRA20 may be preset or provided from an external system via a control signal.

By way of example only, a relatively high sampling (update) rate indicated with the suffix (H) may be equal to 768kHz (768000 samples/second), and a relatively low sampling (update) rate indicated with the suffix (L) may be equal to 48kHz (48000 samples/second). For example, signals RS (H), (AS), (H), (IMON), (H), (VMON), (H), and CS (H) may be 768kHz digital signals, while signals RS (L), (IMON), (L), and VMON (L) may be 48kHz digital signals. The signal config (l) may be a 48kHz signal, or may have an even lower sampling rate (e.g., in the range of 1kHz to 48kHz, such as 3 kHz). Other sampling rates (see audio signals) of relatively low sampling (update) rates indicated with the suffix (L) may be 44.1kHz, 88.2kHz, 96kHz, and 192kHz (e.g., values in an exemplary range of 10kHz to 200 kHz). Of course, these are merely examples.

Thus, for example, the second control loop (and fourth control loop) may be 16 times faster (e.g., between 4 and 100 times faster) than the first control loop, and 16 or 256 times faster (between 4 and 1000 times faster) than the third control loop. Of course, these are merely examples.

As above, the reference signal rs (l) may be used to express a haptic signal, which may have a bandwidth of at most 500Hz or even at most 1 kHz. It should be noted that for use in audio applications, human hearing in the typical range of 20Hz to 20kHz is recognized — such signals may be expressed by suitable reference signals rs (l) having a sampling rate of 44.1kHz, 48kHz, 88.2kHz, 96kHz or 192kHz, for example. Again, these values are examples.

Incidentally, the adder 560 and (optionally) the limiter 570 may be considered as part of the driver 60, such that the driver 60 receives the reference signal rs (h) and the adjustment signal as (h), and controls the drive output signal dos based on those received signals.

Fig. 6 is a schematic diagram of AS determiner 550A AS a detailed exemplary implementation of AS determiner 550. Thus, consistent with AS determiner 550 of fig. 5, AS determiner 550A is configured to generate an adjustment signal AS (h) at its output node 602 based on the current monitoring signal imon (h) received at its input node 604. The adjustment signal as (h) may be considered an impedance realization signal.

In general, AS determiner 550A includes a first low pass filter section 606, a high pass filter section 608, a computation portion 610, and a second low pass filter section 612 connected in series between an input node 604 and an output node 602.

The first low pass filter section 606 comprises a pair of parallel paths, one of whose outputs may be selected by a selector based on an enable (select) signal low1 En. One of those paths includes a low pass filter such that the enable signal low1En effectively determines whether the output signal of the first low pass filter section 606 has been low pass filtered in that section 606.

Similarly, the high pass filter section 608 comprises a pair of parallel paths, one of whose outputs may be selected by a selector based on the enable (select) signal highEn. One of those paths includes a high pass filter such that the enable signal highEn effectively determines whether the output signal of the high pass filter section 608 has been subjected to high pass filtering in that section 608.

Similarly, the second low pass filter section 612 comprises a pair of parallel paths, one of whose outputs may be selected by a selector based on the enable (select) signal low2 En. One of those paths includes a low pass filter such that the enable signal low2En effectively determines whether the output signal of the second low pass filter section 612 has been low pass filtered in that section 612.

Thus, high-pass filtering and low-pass filtering may be considered optional (and thus need not be provided), and may be employed in different ways in different applications.

The calculation section 610 includes a parallel RLC section 620 connected in parallel with a series RLC section 630. The parallel RLC section 620 comprises a calculation block 622 that operates on the current monitoring signal imon (h) to achieve a parallel connection of the parallel resistance par _ r, the parallel capacitance par _ c and the parallel inductance par _ l of the target output impedance 30 based on the parameters or configuration values a0, a1, a2, b0, b1, b2 as indicated. The series RLC section 630 includes computation blocks 632, 634 and 636 connected together in parallel, which computation blocks 632, 634 and 636 operate on the current monitoring signal imon (h) to achieve a series resistance ser _ r, a series capacitance ser _ c and a series inductance ser _ l, respectively, of the target output impedance 30 based on corresponding parameters or configuration values ser _ r, ser _ c and ser _ l as indicated.

The output of each of the computation blocks 622, 632, 634, 636 is passed via a corresponding AND block, along with corresponding enable signals parEn, rEn, lEn AND cEn, respectively, to an adder/subtractor 640, the output of which adder/subtractor 640 is passed to the second low pass filter section 612. In this way, the contributions of the calculation blocks 622, 632, 634, 636 may be selectively included or removed from the signal received by the low pass filter section 612 by means of the respective enable signals parEn, rEn, lEn and cEn. This, together with the control of the parameters or configuration values as mentioned above, has the following effect: the target output impedance 30 can be configured, for example, in the form of any one of the target output impedances 30A to 30E (see fig. 3A to 3E).

The outputs of the calculation blocks 622, 632, 634, 636 may be referred to as adjustment sub-signals, each of which represents a corresponding portion of the target equivalent circuit representing the target output impedance 30. The adjustment sub-signals may thus be combined to arrive at the adjustment signal as (h). The calculation blocks 622, 632, 634, 636 may, for example, perform calculations or access look-up tables.

Fig. 7 is a schematic diagram of an exemplary implementation 50B of the functional block 50 of fig. 4 for use in a current drive mode of operation. In this context, it is understood that the operations described in connection with fig. 4 to 6 correspond to the impedance driven mode of operation. For consistency with fig. 5 and 6, signals cs (h) and imon (h) proceed onwards.

In the current-driven mode of operation, the functional block 50 is configured to function consistent with the exemplary implementation 50B, and in particular to generate the control signal cs (h) as a result of subtracting (at subtractor 702) a current monitoring signal imon (h) acting as a feedback signal from a reference signal rs (h). This negative feedback operation enables control of the current flowing through the LRA20 based on the reference signal rs (h).

It will be understood that the functional block 50 of fig. 4 may be configured to selectively operate in either an impedance driven mode of operation (consistent with fig. 5 and 6) or a current driven mode of operation (consistent with fig. 7), for example, based on a mode select signal (which may be supplied by the controller 70, e.g., as part of a CONFIG signal).

Fig. 8 presents a series of graphs a-D (labeled clockwise from top left) that may be used to understand the benefits and capabilities of the drive circuits 40A, 40B disclosed herein.

These bode plots compare position, velocity, acceleration and power transfer functions in various modes for driving an exemplary LRA20 at a resonant frequency f0 of 50Hz and a quality factor Q of 3 using drive circuits 40A, 40B.

Graph a considers driving LRA20 without simulating the presence of target output impedance 30 or by simulating the presence of target output impedance 30 when configured to have zero impedance. This is equivalent to driving the LRA20 in correspondence with fig. 1. This drive pattern provides relatively poor mechanical control of the LRA 20.

Graph B considers driving the LRA20 (in impedance driven mode) with the modeled target output impedance 30 configured in the variation 30A of fig. 3A, i.e., configured as a negative impedance (negative resistance). This drive form exhibits a constant speed transfer function from 20Hz to 200 Hz.

Graph C considers driving the LRA20 (in an impedance driven mode) with the modeled target output impedance 30 configured in the variation 30E of fig. 3E, i.e., as a positive impedance (positive resistance) with an impedance (resistance) value much larger (i.e., 10 times) than the impedance (resistance) value of the LRA 20. This drive form exhibits a constant position transfer function below resonance (from DC to 20Hz) and a constant acceleration transfer function above resonance (from 200Hz to 1KHz) but at the expense of high impedance.

Graph D considers driving the LRA20, but using a current-driven mode of operation consistent with fig. 7 (i.e., without simulating the presence of the target output impedance 30). This drive form exhibits a constant position transfer function below resonance (from DC to 20Hz) and a constant acceleration transfer function above resonance (from 200Hz to 1KHz) similar to graph C but without high impedance.

The acceleration waveform of a typical LRA20 with low Q can be accurately controlled within the full haptic sensitivity range (DC to 500Hz) using negative impedance around resonance (20Hz to 200Hz) (plot B) and current drive above resonance (>200Hz) (plot D). So-called "beggar versions (pore man's)" current drive can be achieved by configuring the negative resistance circuit to have a large positive resistance (graph C).

At this time, it should be noted that the drive circuit arrangement has been described so far based on voltage source driving of the LRA20 (electromechanical load), i.e. where the drive output signal dos is the voltage signal vload (and the reference signal RS is configured for voltage driving). This driving output signal dos induces a load current iload to be drawn by the LRA20 (or to flow through said LRA). In view of this drive form, the load current iload is monitored (e.g., using the signal IMON) and used to determine the voltage that will be induced across the target output impedance 30 in order to generate the adjustment signal AS. The driver 60 is configured to generate the drive output signal based on the reference signal RS and the adjustment signal AS such that the drive output signal dos behaves AS if the output impedance of the drive circuit has been adjusted to comprise the target output impedance. Fig. 9A is a schematic diagram of the modified drive circuit 40 of fig. 2 as implied by this voltage source control, and for completeness, LRA20 is shown connected to the modified drive circuit.

However, current source driving based on LRA20 also contemplates driving circuit arrangements. It will be appreciated (taking into account the principle of source transformation) that it will be possible to actively control the load current iload (rather than the load voltage vload) by current source control to drive the LRA20 in an equivalent manner to driving by voltage source control.

Fig. 9B is a schematic diagram of a modified drive circuit 40C, the drive circuit 40C being equivalent to the modified drive circuit 40 of fig. 9A but using current source control. Like elements are denoted by like reference numerals. The voltage source 10 of fig. 9B has been replaced with a current source 10C providing a current reference signal Iref. Further, instead of providing a target output impedance (virtual impedance) 30 in series with the voltage source 10 as in fig. 9A, a reconfiguration format is provided in fig. 9B, in which series components (ser _ r, ser _ l, ser _ C) are connected in series with the current source 10C, and parallel components (par _ r, par _ l, par _ C) are connected in parallel with the current source 10C. The LRA20 (separate from the modified driver circuits 40 and 40C) is connected in the same way in both cases.

Thus (for the consideration of fig. 9B), the drive circuits 40A and 40B of fig. 4 to 6 may be converted into equivalent drive circuits based on current source driving of the LRA20 in line with the drive circuit 40C, i.e. where the drive output signal dos is the current signal iload (and the reference signal RS is configured for current driving). The driving output signal dos includes a load voltage vload across the LRA 20. In view of this drive style, the load voltage vload may be monitored (e.g., using signal VMON) and used to determine the current that will be induced to flow through the target output impedance in order to generate the adjustment signal AS (i.e., so that the adjustment signal AS represents current rather than voltage). The driver 60 (current amplifier, in particular a high speed or wide bandwidth current amplifier) may then be configured to generate a driving output (current) signal dos based on the (current-based) reference signal RS and the (current-based) adjustment signal AS, such that the driving output signal dos behaves AS if the output impedance of the driving circuit has been adjusted to comprise the target output impedance.

Accordingly, the descriptions of fig. 4-6 may be considered and understood accordingly to apply with appropriate modifications to the equivalent current source drive arrangement. That is, the drive circuits 40A and 40B will be understood to have current source drive equivalents to which the techniques described herein are similarly applicable.

For example, in the voltage source drive arrangement described earlier, the AS determiner 550 determines (e.g., by calculating or using a look-up table) the voltage that would be induced across the target output impedance 30 in the event that the current flowing through the LRA20 is to flow through the target output impedance 30. In an equivalent current source drive arrangement, the AS determiner 550 determines (e.g., by calculating or using a look-up table) the current to be drawn by the target output impedance 30 in view of the voltage across the LRA 20. Similarly, the adjustment sub-signal is described in terms of voltage in a voltage source drive arrangement, but would be current in an equivalent current source drive arrangement.

As another example, in the voltage source drive arrangement described earlier, the second control loop (to achieve the target output impedance) uses the current monitor signal IMON to adjust the voltage signal, and the fourth control loop (to achieve linear operation of the driver 60) uses the voltage monitor signal VMON to adjust the voltage signal. In an equivalent current source drive arrangement, the second control loop (to achieve the target output impedance) uses the voltage monitoring signal VMON to adjust the current signal, and the fourth control loop (intended to achieve linear operation of the driver 60) uses the current monitoring signal IMON to adjust the current signal. Indeed, those skilled in the art will appreciate that the logic for the second and fourth control loops of the voltage source drive arrangement may effectively be swapped (with appropriate changes to the reference signal RS) to arrive at the current source drive arrangement.

Fig. 10 is a schematic diagram of a host device 1000, the host device 1000 comprising drive circuits 40A and 40B (assuming either a voltage source controlled version as explained in connection with fig. 4 and 5 or a current source controlled version as introduced in connection with fig. 9B) and an LRA20, wherein either drive circuit 40A or 40B is connected to drive the LRA 20. The host device 1000 may of course include other components (not shown) for controlling or operating with the driver circuit, such as an application processor.

The skilled person will recognise that some aspects of the above-described apparatus (circuits) and methods may be embodied as processor control code, for example, on a non-volatile carrier medium such as a magnetic disk, CD-ROM or DVD-ROM, programmed memory such as read-only memory (firmware), or on a data carrier such as an optical or electrical signal carrier.

For some applications, such aspects will be implemented on a DSP (digital signal processor), an ASIC (application specific integrated circuit), or an FPGA (field programmable gate array). Thus, the code may comprise conventional program code or microcode or, for example, code for setting up or controlling an ASIC or FPGA. The code may also include code for dynamically configuring a reconfigurable device, such as a re-programmable gate array. Similarly, the code may include code for a hardware description language (such as Verilog (TM) or VHDL). As the skilled person will appreciate, the code may be distributed between a plurality of coupled components in communication with each other. Such aspects may also be implemented, where appropriate, using code running on a field-programmable analog array or similar device in order to configure analog hardware.

Some embodiments of the invention may be arranged as part of a haptic circuit, such as may be provided in host device 1000 as discussed above. A circuit or circuitry, such as drive circuits 40A or 40B, according to embodiments of the present invention may be implemented, at least in part, as an Integrated Circuit (IC), e.g., on an IC chip. One or more input or output transducers, such as LRA20, may be connected to the integrated circuit when in use.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim, "a" or "an" does not exclude a plurality, and a single feature or other element may fulfil the functions of several elements recited in the claims. Any reference signs or signs in the claims should not be construed as limiting their scope.

The present disclosure extends to set a set of the following statements:

A1. a drive circuit for driving an electromechanical load with a drive output signal at a first sampling rate based on a digital reference signal, the drive output signal inducing a first amount of power at the electromechanical load, the drive circuit comprising:

a function block configured to digitally determine, based on the first quantity of power, an adjustment signal at a second sampling rate higher than the first sampling rate, the adjustment signal indicating a second quantity of power to be induced at a target output impedance of the drive circuit as a result of the first quantity of power; and

a driver configured to generate the drive output signal based on the reference signal and the adjustment signal to cause the drive output signal to behave as if an output impedance of the drive circuit has been adjusted to include the target output impedance,

wherein the first electrical quantity is a current and the second electrical quantity is a voltage, or vice versa.

A2. The drive circuit of statement a1, wherein:

the drive output signal is a voltage signal, the first amount of power is a current drawn by the electromechanical load, and the second amount of power is a voltage across the target output impedance; or

The drive output signal is a current signal, the first amount of power is a voltage across the electromechanical load, and the second amount of power is a current drawn by the target output impedance.

A3. The drive circuit of statement a1 or a2, wherein the functional block is configured to digitally determine the adjustment signal based on the first quantity of power and a definition of the target output impedance.

A4. The driver circuit according to statement a3, wherein the definition comprises one or more configuration values.

A5. The drive circuit of statement a4, comprising: a storage device to store the one or more configuration values, wherein an impedance value of the target output impedance is maintained while maintaining the one or more configuration values stored in the storage device.

A6. The drive circuit of any of statements a4 or a5, wherein:

a target equivalent circuit representing the target output impedance comprises one or more impedance components and a circuit structure for connecting the one or more impedance components together; and is

The one or more configuration values define at least one of the impedance component and/or the circuit structure.

A7. The drive circuit of statement a6, wherein:

the target equivalent circuit includes a plurality of impedance components connected together; and is

The function block is configured to, based on the first amount of power and the one or more configuration values:

determining a plurality of adjustment sub-signals, each adjustment sub-signal representing a corresponding portion of the target equivalent circuit and indicating a portion of the second electrical quantity that would be induced at the corresponding portion of the target equivalent circuit if the second electrical quantity were induced at the target equivalent circuit; and is

Determining the adjustment signal by combining the plurality of adjustment sub-signals,

and optionally wherein:

if the second amount of power is the voltage across the target output impedance, then the portion of the second amount of power is the voltage across the corresponding portion of the target equivalent circuit; and is

If the second amount of power is the current drawn by the target output impedance, then the portion of the second amount of power is the current drawn by the corresponding portion of the target equivalent circuit.

A8. The drive circuit of statement a6 or a7, wherein:

the one or more configuration values define the target equivalent circuit as comprising at least one of a series resistor, a series capacitor, a series inductor, and a parallel impedance network comprising at least two of a parallel resistor, a parallel capacitor, and a parallel inductor connected together in parallel, each of those resistors, capacitors, and inductors being the impedance component,

optionally wherein those of the series resistor, the series capacitor, the series inductor and the parallel impedance network present in the target equivalent circuit are connected in series.

A9. The drive circuit of statement A8, wherein the one or more configuration values define the target equivalent circuit as optionally including only:

the series resistor, wherein the series resistor has a negative resistance;

the series resistor and the series inductor connected together in series, wherein the series resistor has a negative resistance and the series inductor has a negative inductance;

the series resistor and the series inductor connected together in series and to the parallel impedance network, wherein the series resistor has a negative resistance and the series inductor has a negative inductance, and wherein the parallel impedance network comprises the parallel resistor, the parallel capacitor, and the parallel inductor connected together in parallel;

the series resistor and the series capacitor connected together in series, wherein the series resistor has a negative resistance and the series capacitor has a positive capacitance; or

The series resistor, wherein the series resistor has a positive resistance, and wherein the positive resistance is substantially greater than a resistance of the electromechanical load, or a resistance of a resistor in the electromechanical load equivalent circuit representing a mechanical impedance of the electromechanical load.

A10. The drive circuit of any of the preceding statements a, comprising: a controller configured to:

generating the reference signal based on a drive input signal and based on a current drawn by the electromechanical load and/or a voltage across the electromechanical load; and/or

Controlling the definition of the target output impedance based on the current drawn by the electromechanical load and/or the voltage across the electromechanical load to cause a performance, such as a mechanical performance, of the electromechanical load to meet a performance target; and/or

Controlling the definition of the target output impedance based on the current drawn by the electromechanical load and/or the voltage across the electromechanical load to cause the target output impedance to cancel an impedance of at least one electrical component of the electromechanical load, optionally a coil such as a voice coil; and/or

Controlling the definition of the target output impedance based on an impedance control signal to cause the performance of the drive circuit to vary with the impedance control signal.

A11. The drive circuit of any of the preceding statements a, wherein the driver is configured to generate the drive output signal such that the drive output signal has a predefined relationship to a sum of the adjustment signal and the reference signal.

A12. The drive circuit of any of the preceding statements a, wherein:

the functional block is configured to generate a control signal having a predefined relationship to a sum of the adjustment signal and the reference signal; and is

The driver is configured to generate the drive output signal such that the drive output signal has a predefined relationship with the control signal.

A13. The drive circuit of statement a12, wherein:

the drive circuit is selectively operable in an impedance drive mode or a current drive mode;

generating the control signal based on the reference signal and the adjustment signal such that the drive output signal behaves as if the output impedance of the drive circuit has been adjusted to include the target output impedance when the drive circuit is in the impedance drive mode; and is

In the current drive mode, the functional block is configured to generate the control signal in dependence on a current control reference signal and a current drawn by the electromechanical load, and to adjust the control signal based on the current drawn by the electromechanical load such that the current drawn by the electromechanical load has a predefined relationship to the current control reference signal.

A14. The drive circuit of statement a12 or a13, wherein:

at least one of the control signal and the adjustment signal is a digital signal;

the control signal and the adjustment signal are digital signals and the functional block is a digital functional block; and/or

The drive output signal is an analog signal.

A15. The drive circuit of any of statements a 12-a 14, wherein:

the control signal is a digital signal; and is

The driver includes a digital-to-analog converter and an analog amplifier connected together to convert the control signal to an analog signal and then amplify the analog signal to form the drive output signal.

A16. The drive circuit of any of the preceding statements a, comprising: a monitoring unit configured to generate a current monitoring signal indicative of a current drawn by the electromechanical load and/or a voltage monitoring signal indicative of a voltage across the electromechanical load, wherein the functional block is configured to digitally determine the adjustment signal based on the current monitoring signal and/or the voltage monitoring signal.

A17. The drive circuit of any of the preceding statements a, wherein:

the reference signal is indicative of an expected mechanical property of the electromechanical load; and/or

The behavior of the drive output signal as if the output impedance of the drive circuit had been adjusted to include the target output impedance is an expected behavior relative to an expected drive output signal expected to be generated by the driver based on the reference signal in the absence of the adjustment signal; and/or

The driver circuit comprises one or more analog impedance components connected to contribute to the output impedance of the driver circuit; and/or

The target output impedance is configured to cancel the impedance of at least one electrical component of the electromechanical load, optionally a ground coil such as a voice coil; and/or

The electromechanical load is an electromechanical device, such as an actuator; and/or

The electromechanical load is a resonant electromechanical load such as a linear resonant actuator, a loudspeaker or a micro-loudspeaker.

A18. The drive circuit of any of the preceding statements a, wherein:

the driver forms part of a first control loop operable to control the drive output signal based on the reference signal;

the driver and the functional block forming part of a second control loop operable to control the drive output signal based on a current drawn by the electromechanical load and/or a voltage across the electromechanical load; and is

The second control loop is configured to have a lower delay than the first control loop.

A19. The drive circuit of statement a18, wherein at least a portion of the first control loop and at least a portion of the second control loop are implemented as digital circuits, and wherein the delays of the first control loop and the second control loop are defined by sampling rates of respective digital signals of the first control loop and the second control loop.

A20. The drive circuit of any of the preceding statements a, comprising: an analog impedance configured to form a portion of the output impedance of the drive circuit,

optionally wherein the analog impedance is a controllable analog impedance and the functional block is configured to control the controllable analog impedance to adjust the output impedance of the drive circuit.

A21. The driver circuit according to statement a20, configured to control a definition of the target output impedance and/or an impedance of the analog impedance to control the output impedance of the driver circuit.

A22. The driver circuit according to any of the preceding statements a, implemented as an integrated circuit, such as on an IC chip.

A23. An IC chip comprising a driver circuit according to any of the preceding statements a.

A24. A control system, comprising:

the drive circuit of any of the preceding statements a; and

the electro-mechanical load is a load of the machine,

wherein the electromechanical load is connected to be driven by the drive output signal.

A25. A haptic system comprising the control system according to statement a24, wherein the electromechanical load is a linear resonant actuator coupled to a physical structure or surface of the system to produce a haptic effect for a user.

A26. A host device, such as a portable electrical or electronic device, comprising a drive circuit according to any one of statements a 1-a 22, or an IC chip as recited in statement a23, or a control system as recited in statement a24, or a haptic system as recited in statement a25.

A27. A method performed by a drive circuit to drive an electromechanical load with a drive output signal that induces a first amount of power at the electromechanical load based on a digital reference signal, the method comprising:

digitally determining an adjustment signal based on the first quantity of power at a second sampling rate that is higher than the first sampling rate, the adjustment signal indicating a second quantity of power that would be induced at a target output impedance of the drive circuit as a result of the first quantity of power; and

generating the drive output signal based on the reference signal and the adjustment signal to cause the drive output signal to behave as if the output impedance of the drive circuit had been adjusted to include the target output impedance,

wherein the first electrical quantity is a current and the second electrical quantity is a voltage, or vice versa.

The present disclosure extends to set B set forth below:

B1. a drive circuit for driving an electromechanical load with a drive output signal, the drive circuit comprising:

a first control loop operable to control the drive output signal based on a drive input signal; and

a second control loop operable to control the drive output signal based on a current flowing through the electromechanical load and/or a voltage induced across the electromechanical load,

wherein the second control loop is configured to have a lower delay than the first control loop.

B2. The drive circuit of statement B1, wherein the second control loop is configured to control the drive output signal to compensate for an impedance of the electromechanical load.

B3. The drive circuit of statement B1 or B2, wherein the second control loop is configured to control the drive output signal such that the drive output signal behaves as if the output impedance of the drive circuit has been adjusted to include a target output impedance.

B4. The drive circuit of statement B3, wherein the drive output signal is a voltage signal and the second control loop is configured to perform its control on the drive output signal based on a voltage signal to be induced by the current across the target output impedance,

optionally wherein the second control loop is configured to determine an adjustment signal indicative of the voltage signal based on the current and to control the drive output signal based on the adjustment signal.

B5. The drive circuit according to statement B3, wherein the drive output signal is a current signal, and the second control loop is configured to perform its control on the drive output signal based on a current signal that is to induce a current by the voltage to flow through the target output impedance,

optionally wherein the second control loop is configured to determine an adjustment signal indicative of the current signal based on the voltage and to control the drive output signal based on the adjustment signal.

B6. The drive circuit of any of the preceding statements B, comprising a third control loop operable to:

determining one or more configuration values for defining the target output impedance based on the current and/or the voltage; and is

Providing the determined configuration value to the second control loop to define the target output impedance.

B7. The drive circuit of statement B6, wherein the delay of the second control loop is lower than a delay of the third control loop.

B8. The drive circuit of any of the preceding statements B, wherein the first control loop is configured for feedback control of the electromechanical load based on the current and/or the voltage.

B9. The drive circuit of any of the preceding statements B, wherein the first control loop is configured for feed forward control of the electromechanical load.

B10. The drive circuit according to any of the preceding statements B, wherein the second control loop is a feedback control loop, the current and/or the voltage being a feedback signal in the second control loop.

B11. The drive circuit of any of the preceding statements B, wherein at least a portion of the first control loop and at least a portion of the second control loop are implemented as digital circuits, and wherein the delays of the first control loop and the second control loop are defined by sampling rates of respective digital signals of the first control loop and the second control loop.

B12. The drive circuit of any of the preceding statements B, comprising:

a monitoring unit configured to monitor the current and/or the voltage and to generate a monitoring signal indicative of the current and/or the voltage;

a controller operable to generate a reference signal based on the drive input signal and the monitor signal;

a function block operable to generate an adjustment signal based on the monitoring signal; and

a driver operable to generate the drive output signal based on the reference signal and the adjustment signal.

B13. The drive circuit of statement B12, wherein:

the first control loop includes a first signal path extending from the monitor unit to the driver via the controller, the first signal path carrying the monitor signal and the reference signal;

the second control loop includes a second signal path extending from the monitor unit to the driver via the functional block, the second signal path carrying the monitor signal and the adjustment signal;

at least one signal carried by the first control loop and one or more signals carried by the second control loop are digital signals; and is

The one or more digital signals carried by the second control loop have a higher sampling rate than the at least one digital signal carried by the first control loop.

B14. The drive circuit of statement B13, wherein:

at least one signal carried by the first control loop between the monitoring unit and the controller and at least one signal carried by the first control loop between the controller and the driver are digital signals; and is

The one or more digital signals carried by the second control loop have a higher sampling rate than the at least one digital signal carried by the first control loop between the monitoring unit and the controller and/or the at least one signal carried by the first control loop between the controller and the drive.

B15. The drive circuit of any of statements B12-B14, wherein:

the functional block is operable to generate a control signal based on the adjustment signal and the reference signal; and is

The driver is operable to generate the drive output signal based on the control signal.

B16. The drive circuit of any of the preceding statements B, wherein:

the reference signal and/or the drive input signal are indicative of an expected mechanical property of the electromechanical load; and/or

The electromechanical load is an electromechanical device, such as an actuator; and/or

The electromechanical load is a resonant electromechanical load such as a linear resonant actuator, a loudspeaker or a micro-loudspeaker.

B17. The driver circuit according to any of the preceding statements B, implemented as an integrated circuit, such as on an IC chip.

B18. An IC chip comprising a driver circuit according to any of the preceding statements B.

B19. A control system, comprising:

the drive circuit of any of the preceding statements B; and

the electro-mechanical load is a load of the machine,

wherein the electromechanical load is connected to be driven by the drive output signal.

B20. A haptic system comprising the control system according to statement B19, wherein the electromechanical load is a linear resonant actuator coupled to a physical structure or surface of the system to produce a haptic effect for a user.

B21. A host device, such as a portable electrical or electronic device, comprising a drive circuit according to any one of statements B1-B17, or an IC chip as recited in statement B18, or a control system as recited in statement B19, or a haptic system as recited in statement B20.

B22. A method of driving an electromechanical load with a drive output signal, the method comprising:

controlling, by a first control loop, the drive output signal based on a drive input signal; and

controlling, by a second control loop, the drive output signal based on a current flowing through and/or a voltage induced across the electromechanical load,

wherein the second control loop is configured to have a lower delay than the first control loop.

The present disclosure extends to set C set forth below:

C1. a drive circuit for driving an electromechanical load with a drive output signal based on a reference signal, the drive output signal inducing a first electrical quantity at the electromechanical load, the drive circuit comprising:

a function block configured to digitally determine an adjustment signal based on the first quantity of power, the adjustment signal indicating a second quantity of power to be induced at a target output impedance of the drive circuit as a result of the first quantity of power; and

a driver configured to generate the drive output signal based on the reference signal and the adjustment signal to cause the drive output signal to behave as if an output impedance of the drive circuit has been adjusted to include the target output impedance,

wherein:

the drive output signal is a voltage signal, the first amount of power is a current drawn by the electromechanical load, and the second amount of power is a voltage across the target output impedance; or

The drive output signal is a current signal, the first amount of power is a voltage across the electromechanical load, and the second amount of power is a current drawn by the target output impedance.

C2. A drive circuit for driving an electromechanical load with a drive output signal based on a reference signal, the drive output signal being a voltage signal and causing a current to be drawn by the electromechanical load, the drive circuit comprising:

a functional block configured to digitally determine an adjustment signal based on the current, the adjustment signal indicative of a voltage signal to be induced by the current across a target output impedance of the drive circuit; and

a driver configured to generate the drive output signal based on the reference signal and the adjustment signal to cause the drive output signal to behave as if the output impedance of the drive circuit has been adjusted to include the target output impedance.

C3. A drive circuit for driving a linear resonant actuator, the drive circuit comprising:

a function block configured to generate a digital control signal from a digital reference signal and a monitoring signal intended for controlling the linear resonant actuator; and

a driver configured to convert the digital control signal into an analog drive signal to drive the linear resonant actuator,

wherein:

the monitoring signal is indicative of a current flowing through the linear resonant actuator and/or a voltage across the linear resonant actuator; and is

The functional block is configured to control a difference between the digital control signal and the digital reference signal based on the monitor signal such that the analog drive signal has a target manifestation in driving the linear resonant actuator in which the analog drive signal behaves as if the output impedance of the drive circuit had been adjusted to include a target output impedance relative to a desired analog drive signal that is desired to be generated with a digital control signal as a digital reference signal.

C4. A drive circuit for driving an electromechanical load with a drive output signal based on a reference signal, the drive circuit being configured to generate the drive output signal based on a digital operation from the reference signal and an amount of power induced at the electromechanical load so as to cause the drive output signal to behave as if an output impedance of the drive circuit has been adjusted to include a target output impedance.

C5. A drive circuit for driving an electromechanical load with a drive output signal based on a reference signal, the drive output signal inducing a first electrical quantity at the electromechanical load, the drive circuit comprising:

a function block configured to digitally determine an adjustment signal based on the first quantity of power, the adjustment signal indicating a second quantity of power to be induced at a target output impedance of the drive circuit as a result of the first quantity of power; and

a driver configured to generate the drive output signal based on the reference signal and the adjustment signal to cause the drive output signal to behave as if the output impedance of the drive circuit has been adjusted to include the target output impedance.

C6. A drive circuit for driving an electromechanical load with a drive output signal based on a reference signal, the drive circuit being configured to digitally control the drive output signal based on the reference signal so as to cause the drive output signal to behave as if the output impedance of the drive circuit has been adjusted to include a predefined or predetermined target output impedance.

C7. A drive circuit for driving an electromechanical load with a drive output signal based on a reference signal, the drive circuit being configured to digitally control the drive output signal based on the reference signal and an amount of power at the electromechanical load to cause the drive output signal to behave as if an output impedance of the drive circuit has been adjusted to include a predefined or predetermined target output impedance.