阅读说明：本技术 采样电路、采样阵列、存算一体芯片以及电子设备 (Sampling circuit, sampling array, integrated storage and calculation chip and electronic equipment ) 是由 徐明禄 于 2021-07-19 设计创作，主要内容包括：本发明实施例提供一种采样电路、采样阵列、存算一体芯片以及电子设备,该采样电路采用差分结构,包括：第一电压钳位电路、第二电压钳位电路、第一负载电阻、第二负载电阻、第一采样电容、第二采样电容、第一开关以及第二开关,第一输入电流通过该第一电压钳位电路加载在该第一负载电阻上；第二输入电流通过该第二电压钳位电路加载在该第二负载电阻上；该第一采样电容一端通过该第一开关连接在该第一电压钳位电路与该第一负载电阻之间,该第二采样电容一端通过该第二开关连接在该第二电压钳位电路与该第二负载电阻之间,没有引入放大器的失调,提高了采样阵列中各采样电路之间的匹配度,使阵列读出的精度提高,满足高精度运算的需求。(The embodiment of the invention provides a sampling circuit, a sampling array, a storage and calculation integrated chip and electronic equipment, wherein the sampling circuit adopts a differential structure and comprises: the circuit comprises a first voltage clamping circuit, a second voltage clamping circuit, a first load resistor, a second load resistor, a first sampling capacitor, a second sampling capacitor, a first switch and a second switch, wherein a first input current is loaded on the first load resistor through the first voltage clamping circuit; a second input current is loaded on the second load resistor through the second voltage clamping circuit; one end of the first sampling capacitor is connected between the first voltage clamping circuit and the first load resistor through the first switch, one end of the second sampling capacitor is connected between the second voltage clamping circuit and the second load resistor through the second switch, and the imbalance of an amplifier is not introduced, so that the matching degree of each sampling circuit in the sampling array is improved, the reading precision of the array is improved, and the requirement of high-precision operation is met.)

1. A sampling circuit, in a differential configuration, comprising: the circuit comprises a first voltage clamping circuit, a second voltage clamping circuit, a first load resistor, a second load resistor, a first sampling capacitor, a second sampling capacitor, a first switch and a second switch;

a first input current is loaded on the first load resistor through the first voltage clamp circuit; a second input current is loaded on the second load resistor through the second voltage clamping circuit; one end of the first sampling capacitor is connected between the first voltage clamping circuit and the first load resistor through the first switch, and one end of the second sampling capacitor is connected between the second voltage clamping circuit and the second load resistor through the second switch.

2. The sampling circuit of claim 1, further comprising: the other end of the first sampling capacitor is connected between the second voltage clamping circuit and the second load resistor through the third switch; the other end of the second sampling capacitor is connected between the first voltage clamping circuit and the first load resistor through the fourth switch.

3. The sampling circuit of claim 1, wherein the other terminal of the first sampling capacitor is coupled to a first reference voltage, and the other terminal of the second sampling capacitor is coupled to the first reference voltage.

4. The sampling circuit of claim 1, wherein the first load resistor and the second load resistor are both connected to a power source.

5. The sampling circuit of claim 1, wherein the first load resistance and the second load resistance are both grounded.

6. The sampling circuit of any of claims 1 to 5, wherein the first voltage clamp circuit comprises: the first operational amplifier and the first MOS tube; the inverting input end of the first operational amplifier is connected with the source electrode of the first MOS tube and serves as a first current input end, the non-inverting input end of the first operational amplifier is connected with reference voltage, the output end of the first operational amplifier is connected with the grid electrode of the first MOS tube, and the drain electrode of the first MOS tube is connected with the first load resistor;

the second voltage clamp circuit includes: the second operational amplifier and the second MOS tube; the inverting input end of the second operational amplifier is connected with the source electrode of the second MOS tube and serves as a second current input end, the non-inverting input end of the second operational amplifier is connected with the reference voltage, the output end of the second operational amplifier is connected with the grid electrode of the second MOS tube, and the drain electrode of the second MOS tube is connected with the second load resistor.

7. The sampling circuit according to any one of claims 1 to 5, wherein the load resistor comprises a plurality of resistors and at least one switch, and the switch is used for controlling the connection topology of the plurality of resistors to realize the adjustment of the resistance value of the load resistor.

8. A sampling array, comprising: a plurality of sampling circuits as claimed in any one of claims 1 to 7.

9. A computing integrated chip, comprising: an input conversion circuit, an array of memory cells, a sampling array according to claim 8, and an output conversion circuit connected in series.

10. The memory chip of claim 9, wherein the input conversion circuit is implemented by a current steering DAC, and a load resistor in the current steering DAC and a load resistor in the sampling circuit are implemented by the same type of resistor.

11. An electronic device, comprising: the sampling circuit of any one of claims 1 to 7 or the sampling array of claim 8 or the memory chip of claim 8 or 9.

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a sampling circuit, a sampling array, a storage and calculation integrated chip and electronic equipment.

Background

In recent years, in order to solve the bottleneck of memory wall of the traditional von neumann computing architecture, a memory-computing integrated chip architecture is widely concerned, and the basic idea is to directly utilize a memory to perform computing, so as to reduce or even eliminate data transmission between the memory and a processor, reduce power consumption and improve performance.

The storage and calculation integrated chip architecture is considered to be one of high-energy-efficiency hardware platforms for solving real-time intelligent processing of big data at present, the storage and calculation integrated unit array is adopted for carrying out storage calculation, then a sampling circuit in the sampling array is utilized to convert the calculation result of the storage and calculation integrated unit column into a voltage value and store the voltage value on a sampling capacitor for subsequent ADC (analog to digital converter) quantization, the sampling array is composed of a plurality of sampling circuits, the higher the matching degree among the sampling circuits is, the higher the reading precision of the array is, and the higher the calculation precision is.

As shown in fig. 1, a circuit structure of a conventional sampling circuit is implemented by a typical transimpedance amplifier (TIA) to convert current into voltage and sample the voltage onto a capacitor CS, and an output voltage Vx-Vy is (vref-I _ inx × R1) - (vref-I _ iny × R2), and when R1 is R2, Vx-Vy is (R1 × (I _ iny-I _ inx). Due to process deviation in the production process, the operational amplifier can have disorder, and the resistance can also have mismatch, so that Vx-Vy is (I _ iny x (R2+ Rmy) + Vosy) - (I _ inx x (R1+ Rmx) + Vosx), wherein Rmy represents the mismatch of the resistance R2, Rmx represents the mismatch of the resistance R1, Vosy represents the disorder of op2, and Vosx represents the disorder of op 1. If the proper type and size are selected, the offset of the resistor is small and can reach one thousandth, so that Rmx and Rmy can be ignored, the deviation of Vosy and Vosx is related to the offset between differential input tubes in the operational amplifier and the offset between differential load tubes, the offset is difficult to be small, the typical value is dozens of mV, the matching degree between sampling circuits in the sampling array is greatly reduced, the reading precision of the array is reduced, and the requirement of high-precision operation cannot be met.

Disclosure of Invention

In view of the problems in the prior art, the present invention provides a sampling circuit, which can at least partially solve the problems in the prior art.

In order to achieve the purpose, the invention adopts the following technical scheme:

in a first aspect, a sampling circuit is provided, which employs a differential structure, and includes: the circuit comprises a first voltage clamping circuit, a second voltage clamping circuit, a first load resistor, a second load resistor, a first sampling capacitor, a second sampling capacitor, a first switch and a second switch;

a first input current is loaded on the first load resistor through the first voltage clamping circuit; a second input current is loaded on the second load resistor through the second voltage clamping circuit; one end of the first sampling capacitor is connected between the first voltage clamping circuit and the first load resistor through the first switch, and one end of the second sampling capacitor is connected between the second voltage clamping circuit and the second load resistor through the second switch.

Further, the sampling circuit further comprises: the other end of the first sampling capacitor is connected between the second voltage clamping circuit and the second load resistor through the third switch; the other end of the second sampling capacitor is connected between the first voltage clamping circuit and the first load resistor through the fourth switch.

Furthermore, the other end of the first sampling capacitor is connected to a first reference voltage, and the other end of the second sampling capacitor is connected to the first reference voltage.

Furthermore, the first load resistor and the second load resistor are both connected with a power supply.

Further, the first load resistor and the second load resistor are both grounded.

Further, the first voltage clamp circuit includes: the first operational amplifier and the first MOS tube; the inverting input end of the first operational amplifier is connected with the source electrode of the first MOS tube and serves as a first current input end, the non-inverting input end of the first operational amplifier is connected with reference voltage, the output end of the first operational amplifier is connected with the grid electrode of the first MOS tube, and the drain electrode of the first MOS tube is connected with the first load resistor;

the second voltage clamp circuit includes: the second operational amplifier and the second MOS tube; the inverting input end of the second operational amplifier is connected with the source electrode of the second MOS tube and serves as a second current input end, the non-inverting input end of the second operational amplifier is connected with the reference voltage, the output end of the second operational amplifier is connected with the grid electrode of the second MOS tube, and the drain electrode of the second MOS tube is connected with the second load resistor.

Further, the load resistor comprises a plurality of resistors and at least one switch, and the switch is used for controlling the connection topology of the plurality of resistors to realize the resistance value adjustment of the load resistor.

In a second aspect, there is provided a sampling array comprising: a plurality of sampling circuits as described above.

In a third aspect, a computing integrated chip is provided, comprising: the input conversion circuit, the integrated storage unit array, the sampling circuit and the output conversion circuit are connected in sequence.

Further, the input conversion circuit adopts a current steering DAC, and the load resistance in the current steering DAC and the load resistance in the sampling circuit are realized by adopting the same type of resistance.

In a fourth aspect, an electronic device is provided, comprising: such as the sampling circuit described above or the memory chip described above.

The sampling circuit provided by the embodiment of the invention adopts a differential structure and comprises: the circuit comprises a first voltage clamping circuit, a second voltage clamping circuit, a first load resistor, a second load resistor, a first sampling capacitor, a second sampling capacitor, a first switch and a second switch, wherein a first input current is loaded on the first load resistor through the first voltage clamping circuit; a second input current is loaded on the second load resistor through the second voltage clamping circuit; this first sampling electric capacity one end is connected between this first voltage clamp circuit and this first load resistance through this first switch, this second sampling electric capacity one end is connected between this second voltage clamp circuit and this second load resistance through this second switch, the maladjustment of amplifier is not introduced, make the sampling voltage error only by load resistance's mismatch decision, the mismatch of resistance is under present technological condition, it can be done very little to select appropriate resistance type and size, be less than the mismatch of mos pipe far away, in addition, the differential structure can be fine weakens common mode noise and power noise's influence, simultaneously and the fine matching of subsequent difference ADC, the matching degree between each sampling circuit in the sampling array has been improved, make the precision that the array reads out improve, satisfy the demand of high accuracy operation.

In order to make the aforementioned and other objects, features and advantages of the invention comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. In the drawings:

FIG. 1 is a circuit diagram of a sampling circuit of a conventional memory integrated chip;

FIG. 2 is a circuit diagram of a sampling circuit according to an embodiment of the present invention;

FIG. 3 shows a circuit diagram of the sampling circuit of the non-sampling phase of FIG. 2;

FIG. 4 shows a circuit diagram of the sampling circuit of the sampling phase of FIG. 2;

FIG. 5 shows a circuit diagram of the sampling circuit of FIG. 2 sampling a single input;

FIG. 6 shows a first circuit diagram of an operational amplifier in a voltage clamp circuit in a sampling circuit according to an embodiment of the present invention;

FIG. 7 is a circuit diagram II of the operational amplifier of the voltage clamp circuit in the sampling circuit according to the embodiment of the present invention;

FIG. 8 is a circuit diagram III showing the operational amplifier of the voltage clamp circuit of the sampling circuit in an embodiment of the present invention;

FIG. 9 is a circuit diagram four of the operational amplifier of the voltage clamp circuit of the sampling circuit according to the embodiment of the present invention;

fig. 10 is a circuit configuration diagram showing another sampling circuit in the embodiment of the present invention;

FIG. 11 shows a circuit diagram of the sampling circuit of FIG. 10 during the non-sampling phase;

FIG. 12 shows another circuit diagram that can sample a single input;

fig. 13 is a circuit diagram showing a case where one sampling circuit corresponds to one ADC circuit;

fig. 14 and 15 show circuit diagrams when two sampling circuits share one ADC circuit;

FIG. 16 is a circuit diagram of a memory integrated chip according to an embodiment of the present invention;

fig. 17 is a circuit configuration diagram of a sampling array in an embodiment of the present invention.

Detailed Description

In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

It should be noted that the terms "comprises" and "comprising," and any variations thereof, in the description and claims of this application and the above-described drawings, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

In an electronic circuit, it is often necessary to convert the current into a digital code, for example, a memory chip needs to convert the analog current of a memory cell column into a digital code through an ADC (analog-to-digital converter) for subsequent processing, and one memory cell column corresponds to one ADC. In order to save power consumption, a plurality of memory cell columns can share one ADC, and the output of 2 memory cell columns can be quantized by one differential ADC.

At this time, a sampling circuit is required to be arranged at the front end of the ADC, and the sampling circuit is used for converting the current analog quantity into a voltage value, and storing the voltage value on a capacitor in the sampling circuit for quantization of the subsequent ADC.

FIG. 2 is a circuit diagram of a sampling circuit according to an embodiment of the present invention; as shown in fig. 2, the sampling circuit adopts a differential structure, and includes: a voltage clamp circuit 11, a voltage clamp circuit 12, a load resistor R1, a load resistor R2, a sampling capacitor CS1, a sampling capacitor CS2, a switch S1, and a switch S4;

the input current I _ inx is loaded on the load resistor R1 through the voltage clamp circuit 11; an input current I _ iny is loaded on the load resistor R2 through the voltage clamp circuit 12; one end of the sampling capacitor CS1 is connected between the voltage clamp circuit 11 and the load resistor R1 through the switch S1, and one end of the sampling capacitor CS2 is connected between the voltage clamp circuit 12 and the load resistor R2 through the switch S4.

The ADC quantization is generally an analog voltage value, and for the convenience of ADC quantization, the sampling circuit converts an analog current value into an analog voltage value.

Point X, Y is 2 current input terminals of the sampling circuit, Vx and Vy are output terminals, currents flowing through load resistors R1 and R2 are determined by input currents at point X, Y, the mismatch of resistors is small and can reach one thousandth if an appropriate type and size are selected, so that the mismatch between R1 and R2 is ignored, and R1 is approximately equal to R2, so that Vx-Vy is (I _ inx-I _ iny) × R1.

By adopting the technical scheme, the maladjustment of the amplifier is not introduced, so that the sampling voltage error is only determined by the mismatching of the load resistor, the mismatching of the resistor is under the current process condition, the proper resistor type and size can be selected to be very small and are far smaller than the mismatching of the mos tube, in addition, the differential structure can well weaken the influence of common-mode noise and power supply noise, and simultaneously, the differential structure is well matched with a subsequent differential ADC (analog to digital converter), the matching degree between sampling circuits in a sampling array is improved, and the requirement of high-precision operation is met. The sampling array comprises a plurality of sampling circuits.

In an alternative embodiment, with continued reference to fig. 2, the load resistor R1 is connected to the power source along with the load resistor R2.

In another alternative embodiment, the load resistor R1 and the load resistor R2 may both be grounded.

It is worth noting that when sampling a column of memory cells, I _ inx and I _ iny are negative currents due to the pull-out current from the memory cells, and R1 and R2 are connected to a power supply, see fig. 2. If in other applications I _ inx and I _ iny are positive currents, R1 and R2 are grounded.

In an alternative embodiment, with continued reference to fig. 2, the sampling circuit further comprises: a switch S2 and a switch S3, and the other end of the sampling capacitor CS1 is connected between the voltage clamp circuit 12 and the load resistor R2 through the switch S2; the other end of the sampling capacitor CS2 is connected between the voltage clamp circuit 11 and the load resistor R1 via the switch S3.

In an alternative embodiment, referring to fig. 3, voltage clamp 11 includes: an operational amplifier OP3 and a MOS transistor M1; the inverting input terminal of the operational amplifier OP3 is connected to the source of the MOS transistor M1 and serves as the first current input terminal X, the non-inverting input terminal thereof is connected to the reference voltage vref, the output terminal of the operational amplifier OP3 is connected to the gate of the MOS transistor M1, and the drain of the MOS transistor M1 is connected to the load resistor R1;

voltage-clamping circuit 12 includes: an operational amplifier OP4 and a MOS transistor M2; the inverting input terminal of the operational amplifier OP4 is connected to the source of the MOS transistor M2 and serves as the second current input terminal Y, the non-inverting input terminal is connected to the reference voltage vref, the output terminal of the operational amplifier OP4 is connected to the gate of the MOS transistor M2, and the drain of the MOS transistor M2 is connected to the load resistor R2.

The voltage values of the X point and the Y point are clamped at a reference voltage value vref through negative feedback of the operational amplifier, so that the stability of the voltage values of the X point and the Y point is kept, and the mismatch of the column currents of the memory cells is reduced. In addition, since the operational amplifier is used for clamping and does not affect the current on the load resistor, the mismatch of the sampling circuit is not affected.

In the sampling phase, the switches S1, S2, S3 and S4 are closed, referring to fig. 4, the sampling circuit performs sampling, the a terminal of the sampling capacitor CS1 and the C terminal of the sampling capacitor CS2 are charged to (I _ inx × R1), the B terminal of the sampling capacitor CS1 and the D terminal of the sampling capacitor CS2 are charged to (I _ iny × R2) after a period of time elapses, the sampling is finished, the switches S1, S2, S3 and S4 are opened, the off state referring to fig. 3, so that the analog current value is converted into an analog voltage value, the charges are stored on the sampling capacitors CS1 and CS2, and the charges on the CS1 and CS2 are used for quantization of subsequent ADCs.

It should be noted that the sampling circuit provided in the embodiment of the present invention can perform differential sampling and can also sample 1 output, specifically referring to fig. 5, one input terminal X of the sampling circuit is connected to the output of the memory cell column 1, and the other input terminal Y is connected to the reference current Iref, so that sampling of the output of the memory cell column 1 can be achieved.

It should be noted that, in the embodiment of the present invention, the amplifier in the voltage clamp circuit may adopt a circuit structure as shown in any one of fig. 6 to 9.

In an alternative embodiment, referring to fig. 10 and 11, the other end of the sampling capacitor CS1 and the other end of the sampling capacitor CS2 both receive a reference voltage VR (VR may be any value between 0 and VDD, and may be chosen appropriately according to the reference voltage of the ADC).

By adopting the technical scheme, the number of switches can be effectively reduced, and the control complexity and the number of circuit components are further reduced.

In an alternative embodiment, the sampling circuit provided in the embodiment of the present invention may further sample the output of one memory cell column, and the circuit structure is as shown in fig. 12.

Through the technical scheme, the precision can be improved when the single signal is sampled.

In an optional embodiment, the load resistor includes a plurality of resistors and at least one switch, the switch is used for controlling the connection topology of the plurality of resistors, and the adjustment of the resistance value of the load resistor is realized by controlling the series connection and the parallel connection of the plurality of resistors.

It should be noted that, in the embodiment of the present invention, the resistance of the load resistor and the capacitance of the sampling capacitor are selected according to an application scenario, each switch is controlled by sequential logic, and when sampling 2 inputs, the ADC converts the voltage difference between the two capacitors into a digital code.

In addition, the switches S1 to S4 are the same switches, such as mos switches or bootstrap switches, R1 and R2 are the same resistors, CS1 and CS2 are the same capacitors, OP3 and OP4 are the same operational amplifiers, and M1 and M2 are the same transistors.

In an alternative embodiment, one sampling circuit corresponds to one ADC circuit, and the circuit connection relationship is shown in fig. 13, where the ADC is a differential sampling ADC.

In another optional embodiment, the plurality of sampling circuits correspond to one ADC circuit, and in the sampling stage, since the sampling circuits in the sampling array are independent from each other, all the sampling circuits in the sampling array can sample simultaneously, which can shorten sampling time and increase sampling speed. After sampling is completed, the capacitors in the sampling circuits in the sampling array are sequentially connected to the input end of the ADC for quantization according to the timing control, as shown in fig. 14, the ADC quantizes the charges on the capacitors in the sampling circuit 1, and in the next clock cycle, the ADC quantizes the charges on the capacitors in the sampling circuit 2, as shown in fig. 15, the capacitors in the sampling circuit 2, and in the next clock cycle, the capacitors in the sampling circuit 1, VIP-VIN-2 (Vx2-Vy 2).

An embodiment of the present invention further provides a sampling array, including: a plurality of sampling circuits as described above.

By sampling the sampling circuit, the matching degree of the sampling array is improved, and the sampling precision is further improved.

The embodiment of the invention also provides a storage and calculation integrated chip, which comprises: the input conversion circuit, the integrated storage unit array, the sampling circuit and the output conversion circuit are connected in sequence.

Specifically, referring to fig. 16, the input conversion circuit may be a DAC module, which is used to convert a digital input signal into an analog signal and transmit the analog signal to the memory cell array, and the memory cell array is used to perform a multiply-add operation on the analog signal.

The signal to be operated can be a digital signal and is provided with a plurality of digital bits, each digital bit is converted into an analog signal through one DAC, the digital bits are respectively converted into a plurality of analog signals through the DACs, the analog signals are respectively input into a plurality of word lines WL corresponding to the storage unit array, after analog vector-matrix multiplication operation is carried out on the storage unit array, the sampling circuits in the sampling array corresponding to the output end of the storage unit array sample the current of the corresponding column, and after the current signals are converted into voltage signals, the ADC converts the voltage signals into digital quantity to be output.

Through adopting above-mentioned sampling circuit, the maladjustment of amplifier is not introduced for sampling voltage error is only decided by load resistance's mismatch, and the mismatch of resistance is under present technological condition, selects appropriate resistance type and size to accomplish very little, is less than the mismatch of mos pipe far away, and in addition, the influence of common mode noise and power noise can fine weaken to the difference structure, simultaneously with the fine matching of subsequent difference ADC, has improved the matching degree between each sampling circuit in the sampling array, satisfies the demand of high accuracy operation. The sampling array comprises a plurality of sampling circuits.

In an alternative embodiment, referring to fig. 17, the sampling array may further include a multiplexer MUX, where one end of the multiplexer is connected to the plurality of inputs, and the output end of the multiplexer is connected to a sampling circuit, so that the sampling circuit is multiplexed to sample the plurality of inputs in a time-sharing manner, thereby improving the utilization rate of the sampling circuit.

In an alternative embodiment, the memory integrated chip may use a current steering DAC, and the load resistor in the current steering DAC is implemented by using the same type of resistor as the load resistor in the sampling circuit.

It is worth noting that the sampling circuit in the embodiment of the present invention needs to correspond to the memory cell columns one to one, so as to improve the parallelism, so that all the memory cell columns can sample at the same time, and the equivalent sampling time is shortened. Of course, in some specific cases, one sampling circuit may be time-division multiplexed by a plurality of memory cell columns to reduce the number of sampling circuits, and further reduce the circuit scale and power consumption.

The performance of each sampling circuit in the sampling array needs to be consistent as much as possible, so that the mismatch value between the sampling circuits is the key of the ADC conversion precision, and the mismatch introduced by the sampling array needs to be controlled to meet the requirement of the array current reading precision.

In an alternative embodiment, the ADC may be a sar ADC, a pipelined ADC, a FLASHADC, a Sigma-delta ADC, etc., which is not limited in this embodiment of the invention.

In summary, as can be seen from the formula Vx-Vy (I _ inx-I _ iny) × R1, the sampling voltage error between the sampling circuits in the sampling array is determined only by mismatch of the resistor R, and under the current process conditions, the selection of the appropriate resistor type and size can be made small, which is much smaller than that of mos transistor. The differential structure can well weaken the influence of common mode noise and power supply noise and is well matched with a subsequent differential ADC.

When the storage and computation integrated chip works, the current change range of the storage unit is very wide and can be from dozens of nA to dozens of muA, the quantization range of the ADC is generally fixed or adjustable in a very small range, and in order to improve the quantization precision, the current change of the storage unit can be adapted by dynamically adjusting the resistance value of a load resistor in the sampling circuit, so that Vx-Vy is as large as possible under the condition that the Vx-Vy does not exceed the input range of the ADC, and the quantization precision is improved. The resistance adjustment can be controlled by a logic unit, and is adjusted according to the current range. For example, if a current of 1 microampere is inputted, the resistance can be modulated to 10K, and at the next moment, if a current of 10 microamperes is inputted, the resistance can be adjusted to 1K, so as to maximally limit the range of using the ADC

The load resistor of the current steering DAC at the front stage of the memory cell can be selected to be the same as the resistor in the circuit, so that the influence of the process of the resistor R on the gain of the whole signal channel (DAC-mem cell-ADC) can be eliminated.

An embodiment of the present invention further provides an electronic device, including: such as the sampling circuit described above or the memory chip described above. The electronic device may be, for example, a personal computer, a laptop computer, a cellular telephone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a gaming console, a tablet computer, a wearable device, or a combination of any of these devices.

In a typical example, the electronic device specifically includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor executes the program to implement the steps of the pipeline control method for parallel operation of the integrated chip.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the system embodiment, since it is substantially similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment.

The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.