阅读说明：本技术 一种引脚重布局的无源器件及其制作方法 (Passive device with rearranged pins and manufacturing method thereof ) 是由 不公告发明人 于 2021-08-06 设计创作，主要内容包括：本发明公开了一种引脚重布局的无源器件的制作方法,包括以下步骤：S1在衬底片上制作体通孔；S2在衬底片上下表面分别制作位于下表面的第一金属层和位于上表面的第二金属层,并在第一金属层上旋涂第一介质层；S3在第二金属层上旋涂第二介质层,在第二介质层上电镀第三金属层,并在第三金属层上旋涂第三介质层；S4在第三介质层上刻蚀出第一通孔；S5制作第四金属层,并在第四金属层上旋涂第四介质层,在第四介质层上刻蚀出第二通孔；S6制作第五金属层,并在第五金属层上旋涂第五介质层；S7在第一介质层上刻蚀出焊盘开窗。本发明通过高孔径比的体通孔和较厚的表面布线层,将集成无源器件表面分布不规则的焊盘重新分配,且焊盘可与基板直接。(The invention discloses a method for manufacturing a passive device with a rearranged pin, which comprises the following steps: s1, manufacturing a body through hole on the substrate sheet; s2, respectively manufacturing a first metal layer on the lower surface and a second metal layer on the upper surface and the lower surface of the substrate sheet, and spin-coating a first dielectric layer on the first metal layer; s3 spin-coating a second dielectric layer on the second metal layer, electroplating a third metal layer on the second dielectric layer, and spin-coating a third dielectric layer on the third metal layer; s4, etching a first through hole on the third dielectric layer; s5, manufacturing a fourth metal layer, spin-coating a fourth dielectric layer on the fourth metal layer, and etching a second through hole on the fourth dielectric layer; s6, manufacturing a fifth metal layer, and spin-coating a fifth dielectric layer on the fifth metal layer; s7 etching a pad window on the first dielectric layer. The invention redistributes the irregularly distributed bonding pads on the surface of the integrated passive device through the body through hole with high aperture ratio and the thicker surface wiring layer, and the bonding pads can be directly connected with the substrate.)

1. A manufacturing method of a passive device with rearranged pins is characterized by comprising the following steps:

s1, manufacturing a body through hole on the substrate sheet, and carrying out physical vapor deposition on the wall of the body through hole and the upper and lower surfaces of the substrate sheet;

s2, respectively manufacturing a first metal layer on the lower surface and a second metal layer on the upper surface and the lower surface of the substrate sheet, and spin-coating a first dielectric layer on the first metal layer;

s3 spin-coating a second dielectric layer on the second metal layer, electroplating a third metal layer on the second dielectric layer, and spin-coating a third dielectric layer on the third metal layer;

s4, etching a first through hole on the third dielectric layer;

s5, repeating the step S2 on the upper surface of the substrate, manufacturing a fourth metal layer, enabling the fourth metal layer and the third metal layer to be connected through the first through hole, spin-coating a fourth dielectric layer on the fourth metal layer, and etching a second through hole on the fourth dielectric layer;

s6, repeating the step S2 on the upper surface of the substrate sheet, manufacturing a fifth metal layer, connecting the fifth metal layer and the fourth metal layer through a second through hole, and spin-coating a fifth dielectric layer on the fifth metal layer;

s7 etching a pad window on the first dielectric layer.

2. The method of claim 1, further comprising:

prior to step S3, welding a carrier under the first dielectric layer;

before step S7, the carrier is removed.

3. The method as claimed in claim 1, wherein the substrate is made of glass.

4. The method of claim 1, wherein the first to fifth dielectric layers are PI or BCB.

5. The method as claimed in claim 1, wherein the physical vapor deposition on the wall of the body via hole and the upper and lower surfaces of the substrate wafer in step S1 comprises:

and plating metal copper on the wall of the through hole of the body.

6. The method for manufacturing a passive device with re-arranged pins as claimed in claim 1, wherein the step S1 is to manufacture a body via on the substrate, specifically:

the body vias are fabricated on the substrate sheet using TGV technology.

7. A passive device manufactured according to the method of any of claims 1-6.

Technical Field

The invention relates to the technical field of semiconductors, in particular to a passive device with a rearranged pin and a manufacturing method thereof.

Background

The current mobile device and internet of things device market is experiencing an unprecedented high-speed growth. Although digital circuits continue to increase in integration driven by moore's law, rf circuits cannot be reduced in size on the same scale. Therefore, further integration of rf circuits, especially passive device parts, has become a key to system-in-package technology. In order to meet the increasing demand, reduce size and cost, and increase functions, the Through Glass Via (TGV) technology has become a feasible technology for rf front-end design.

The existing integrated passive device process is a technology for realizing the resistance, the capacitance and the inductance of the passive device by adopting a semiconductor post process, and has the advantages that the high-precision resistance, the high-precision capacitance and the low-process-error wiring can be designed; but limited by the integrated circuit technology, the devices including resistors, capacitors, inductors and the like can be only concentrated in a thin layer of tens of microns, and therefore, the placement of the bonding pads is not facilitated. The TGV process adopts low-dielectric-constant material glass as a substrate material, and can realize a substrate through hole with high aperture ratio and a thicker surface wiring layer. But how to combine the two is still a problem.

Disclosure of Invention

The invention aims to provide a passive device with a rearranged pin and a manufacturing method thereof, so as to overcome the defects in the prior art.

In order to solve the technical problems, the technical scheme of the invention is as follows:

a manufacturing method of a passive device with rearranged pins comprises the following steps:

s1, manufacturing a body through hole on the substrate sheet, and carrying out physical vapor deposition on the wall of the body through hole and the upper and lower surfaces of the substrate sheet;

s2, respectively manufacturing a first metal layer on the lower surface and a second metal layer on the upper surface and the lower surface of the substrate sheet, and spin-coating a first dielectric layer on the first metal layer;

s3 spin-coating a second dielectric layer on the second metal layer, electroplating a third metal layer on the second dielectric layer, and spin-coating a third dielectric layer on the third metal layer;

s4, etching a first through hole on the third dielectric layer;

s5, repeating the step S2 on the upper surface of the substrate, manufacturing a fourth metal layer, enabling the fourth metal layer and the third metal layer to be connected through the first through hole, spin-coating a fourth dielectric layer on the fourth metal layer, and etching a second through hole on the fourth dielectric layer;

s6, repeating the step S2 on the upper surface of the substrate sheet, manufacturing a fifth metal layer, connecting the fifth metal layer and the fourth metal layer through a second through hole, and spin-coating a fifth dielectric layer on the fifth metal layer;

s7 etching a pad window on the first dielectric layer.

In a preferred embodiment of the present invention, the method further comprises:

prior to step S3, welding a carrier under the first dielectric layer;

before step S7, the carrier is removed.

In a preferred embodiment of the present invention, the substrate sheet is made of glass.

In a preferred embodiment of the present invention, the first to fifth dielectric layers are made of PI or BCB.

In a preferred embodiment of the present invention, the physical vapor deposition on the walls of the through-body via and the upper and lower surfaces of the substrate sheet in step S1 comprises:

and plating metal copper on the wall of the through hole of the body.

In a preferred embodiment of the present invention, the step S1 is to fabricate a through-body via on the substrate, specifically:

the body vias are fabricated on the substrate sheet using TGV technology.

The other technical scheme is as follows:

a passive device manufactured according to any of the above methods.

Compared with the prior art, the invention has the beneficial effects that:

the invention utilizes the characteristics of TGV process, designs a metal layer and a dielectric layer on a substrate to form a passive device, redistributes irregularly distributed bonding pads on the surface of the integrated passive device through a body through hole with high aperture ratio and a thicker surface wiring layer, adapts to surface mount packaging processes such as grid array packaging (LGA) and the like, and realizes the development of pin pairs of competitive products; meanwhile, the flexibility of the internal layout of the device can be further improved, coupling effects among inductors, routing wires and the like are effectively utilized or shielded, and the device with higher performance is realized.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of a manufacturing process of the present invention;

fig. 2 is a schematic perspective view of a passive device of the present invention.

Specifically, 101, a substrate sheet;

201. a body through hole; 202. a first through hole; 203. a second through hole; 204. windowing a welding disc;

301. a first metal layer; 302. a second metal layer; 303. a third metal layer; 304. a fourth metal layer; 305. a fifth metal layer; 306. a pad;

401. a first dielectric layer; 402. a second dielectric layer; 403. a third dielectric layer; 404. a fourth dielectric layer; 405. a fifth dielectric layer;

501. and (3) a carrier.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are used merely for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore, should not be taken as limiting the scope of the present invention. Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the invention, the meaning of "a plurality" is two or more unless otherwise specified.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art through specific situations.

As shown in fig. 1, a method for manufacturing a passive device with rearranged pins includes the following steps:

s1 is to form the body through-hole 201 on the substrate sheet 101 according to the drawing, and to perform Physical Vapor Deposition (PVD) on the wall of the body through-hole 201 and the upper and lower surfaces of the substrate sheet 101.

Preferably, the substrate sheet 101 is made of glass to achieve a high aperture ratio and a thick surface wiring layer with its large thickness.

Further, the wall of the body through hole 201 is plated with copper metal to realize the connection of the upper and lower surfaces of the subsequent substrate sheet 101.

Still further, a body through-hole 201 is made on the substrate sheet 101 using TGV technology.

S2, a first metal layer 301 on the bottom surface and a second metal layer 302 on the top surface are respectively formed on the top and bottom surfaces of the substrate sheet 101, and a first dielectric layer 401 is spin-coated on the first metal layer 301.

Specifically, a first metal layer 301 and a second metal layer 302 are manufactured through a photolithography and electroplating process, and the first metal layer 301 and the second metal layer 302 are connected through the body via 201.

S3 spin coats second dielectric layer 402 on second metal layer 302, electroplates third metal layer 303 on second dielectric layer 402, and spin coats third dielectric layer 403 on third metal layer 303. Second metal layer 302, second dielectric layer 402, and third metal layer 303 form a MIM capacitor.

Preferably, a carrier 501 is bonded under the first dielectric layer 401 before step S3 to reinforce the strength of the substrate sheet 101 and prevent the substrate sheet 101 from being damaged during the manufacturing process.

S4 etches a first via 202 in the third dielectric layer 403.

Specifically, the first via 202 is etched by a photolithography process.

S5 repeating step S2 on the top surface of the substrate sheet 101, fabricating the fourth metal layer 304, connecting the fourth metal layer 304 and the third metal layer 303 through the first via 202, spin-coating the fourth dielectric layer 404 on the fourth metal layer 304, and etching the second via 203 on the fourth dielectric layer 404.

S6 repeating step S2 on the top surface of the substrate sheet 101, forming a fifth metal layer 305 such that the fifth metal layer 305 and the fourth metal layer 304 are connected through the second via 203, and spin-coating a fifth dielectric layer 405 on the fifth metal layer 305.

S7 etches a pad window 204 in the first dielectric layer 401. The pad window 204 corresponds to the body via 201, and a pad 306 is formed on the pad window 204.

Specifically, before step S7, the carrier 501 is removed, and the pad windowing 204 is etched again, so that the pads 306 on the integrated passive device, which cannot be placed according to the index due to device wiring, are placed again, and the pads 306 can be directly connected to the substrate, so that the surface of the integrated passive device is smoother, and pin-to-pin development of competitive products is realized, and the pads 306 can make full use of the lower surface of the substrate sheet 101, which is relatively abundant, to manufacture the pads 306 with a relatively large area, thereby improving the heat dissipation performance of the passive device.

In addition, the bonding pad 306 is led to the lower surface through the body through hole 201, and the body through hole 201 has a certain height, so that compared with the common design (namely the bonding pad 306 is placed near the inductor and on the same plane), the passive device manufactured by the method has the advantages that the inductor is farther from the reference ground, the inductor Q value is higher, and the performance of the integrated passive device is better.

In this embodiment, the material of the first dielectric layer 401 to the fifth dielectric layer 405 is preferably PI or BCB, i.e., polyimide or benzocyclobutene.

As shown in fig. 2, the present invention also discloses a passive device manufactured according to the above method, the upper surface of the passive device is connected to the adjacent through holes in sequence through a second metal layer 302, a third metal layer 303, a fourth metal layer 304 and a fifth metal layer 305, thereby forming a three-dimensional multilayer spiral structure, and the lower surface first metal layer 301 is connected to the upper surface second metal layer 302 through a body through hole 201, thereby realizing pin redistribution.

In summary, the invention utilizes the characteristics of the TGV process to design a metal layer and a dielectric layer on a substrate to form a passive device, redistributes irregularly distributed pads on the surface of the integrated passive device through a body through hole with a high aperture ratio and a thicker surface wiring layer, and adapts to surface mount package processes such as grid array package (LGA) and the like to realize the development of pin pairs of competitive products; meanwhile, the flexibility of the internal layout of the device can be further improved, coupling effects among inductors, routing wires and the like are effectively utilized or shielded, and the device with higher performance is realized.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.