阅读说明：本技术 功率估计系统 (Power estimation system ) 是由 A·韦克菲尔德 K·阿卜杜勒-哈菲兹 于 2021-04-27 设计创作，主要内容包括：本申请案涉及一种功率估计系统。一种用于集成电路设计的功率估计的方法包含：在扫描模式中将测试向量加载到第一触发器序列中；在扫描模式中评估所述测试向量且将所述评估的结果保存在第二触发器序列中；将结果从所述第二触发器序列读出到扫描链；及基于所述结果来计算功率生成。在一个实施例中,从自动测试型式生成器接收所述测试向量。(The present application relates to a power estimation system. A method for power estimation for an integrated circuit design comprising: loading a test vector into a first sequence of flip-flops in a scan mode; evaluating the test vector in a scan mode and saving a result of the evaluation in a second sequence of flip-flops; reading out the result from the second flip-flop sequence to a scan chain; and calculating power generation based on the result. In one embodiment, the test vector is received from an automatic test pattern generator.)

1. A method for power estimation of a portion of an integrated circuit design, comprising:

loading a test vector into a first sequence of flip-flops in a scan mode;

evaluating the test vector in a scan mode and saving a result of the evaluation in a second sequence of flip-flops;

reading out the result from the second flip-flop sequence to a scan chain; and

calculating power used by the portion of the integrated circuit design based on the result.

2. The method of claim 1, wherein the test vectors are loaded using a serial scan chain.

3. The method of claim 1, wherein an automatic test pattern generator provides the test vectors for the power estimation, the test vectors including initial states of a plurality of elements in the integrated circuit design such that gate level simulation is not used.

4. The method of claim 3, wherein the automatic test pattern generator generates the test vectors of a pattern of interest for evaluation by the power estimate.

5. The method of claim 1, wherein:

the test vectors are concatenated to form a series of scan tests; and

each of the test vectors overlaps with a next set of the test vectors and a previous set of the test vectors.

6. The method of claim 1, further comprising:

the result used to evaluate the power of each test vector;

reordering the powers calculated for each test vector; and

calculating the power for all pattern combinations.

7. The method of claim 6, wherein the combination is calculated using a power matrix.

8. The method of claim 7, further comprising:

elements representing power levels above a threshold are removed from the power matrix.

9. The method of claim 8, further comprising:

the evaluation is iterated over the power matrix and each entry in the power matrix is labeled with a priority such that the maximum power value in the matrix is the starting point.

10. A power estimation system for an integrated circuit design, comprising:

scan logic configured to load a test vector into a first sequence of flip-flops in a scan mode;

a waveform evaluator configured to evaluate the test vector in a scan mode and save a result of the evaluation in a second sequence of flip-flops;

the scan logic further configured to read out results from the second sequence of flip-flops to a scan chain; and

a power estimator configured to calculate a power used by the portion of the integrated circuit design based on the result.

11. The system of claim 10, further comprising:

a serial scan chain, wherein the test vectors are loaded using the serial scan chain.

12. The system of claim 10, further comprising:

an automatic test pattern generator configured to provide initial states of elements of the integrated circuit design, the initial states including the test vectors, such that gate level simulation is not used.

13. The system of claim 12, wherein the automatic test pattern generator generates the test vectors of a pattern of interest for evaluation by the power estimation system.

14. The system of claim 10, wherein the test vectors are concatenated to form a series of scan tests, and each of the test vectors overlaps a next set of the test vectors and a previous set of the test vectors.

15. The system of claim 10, further comprising:

a combined node calculator configured to use the results to evaluate the power of each test vector;

matrix logic configured to reorder the power calculated for each test vector; and

the power estimator configured to calculate the power for all pattern combinations.

16. The system of claim 15, wherein the combination is calculated using a power matrix.

17. The system of claim 16, further comprising:

the matrix logic further configured to remove elements from the power matrix representing power levels above a threshold.

18. A power estimation system, comprising:

an automatic test pattern generator configured to generate test vectors for a plurality of elements in the circuit for evaluation against the selected pattern;

a power analysis system for receiving the test vectors from the automatic test pattern generator, the power analysis system comprising:

scan logic configured to load a test vector into a first sequence of flip-flops in a scan mode;

a waveform evaluator configured to evaluate the test vector in a scan mode and save a result of the evaluation in a second sequence of flip-flops;

the scan logic further configured to read out results from the second sequence of flip-flops to a scan chain; and

a power estimator configured to calculate a power generation based on the result.

19. The system of claim 18, wherein the automatic power test pattern generator receives a selected one or more cycles as input for evaluation.

20. The system of claim 18, wherein the power analysis system further comprises:

matrix logic configured to select a pairing pattern from a power matrix that includes power values for all pattern combinations, wherein the matrix logic selects a lowest power pattern combination.

Technical Field

The present disclosure relates to power analysis, and in particular, to power estimation based on analysis of test patterns without simulation or emulation.

Background

The test pattern is used to verify the integrity of the fabricated silicon circuits. The manufactured chip is placed into a tester and the pattern is input into the device using a scan chain. Test pattern input is optimized to provide maximum control and visibility of manufacturing defects.

During scan testing, test patterns are loaded into the circuit serially via a set of scan chains. During this loading process, the number of switches inside the circuit is high and the peak glitch power may overload the tester or damage the silicon.

To eliminate these power problems, Standard Delay Format (SDF) delays may be utilized to simulate a circuit with a test pattern, followed by performing power calculations. This gate level simulation and power estimation is slow and due to the length of the test vectors, this process can take a significant amount of time (e.g., several weeks) to perform even with the computational grid.

Simulation does not solve this problem because detailed delay information is required, which is not typically supported by the simulator.

Detailed and accurate power calculations using all waveforms are slow but are required using simulated or analog outputs.

Disclosure of Invention

A method for power estimation of a portion of an integrated circuit design, comprising: loading a test vector into a first sequence of flip-flops in a scan mode; evaluating the test vector in a scan mode and saving a result of the evaluation in a second sequence of flip-flops; reading out the result from the second flip-flop sequence to a scan chain; and calculating power used by the portion of the integrated circuit design based on the result.

Drawings

The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

FIG. 1A illustrates one embodiment of a method for testing power estimation of vector stimulation.

FIG. 1B illustrates one embodiment of an improved method for power estimation.

FIG. 2 is a block diagram of one embodiment of a power estimation system.

Fig. 3 is an overview flow diagram of one embodiment of a power estimation process.

FIG. 4 is a flow diagram of one embodiment of a power analysis system using an integrated waveform and power engine method.

FIG. 5 illustrates a simplified diagram of one embodiment of the elements involved in the process.

FIG. 6 illustrates one embodiment of loading scan data.

FIG. 7 is a block diagram of one embodiment of evaluation between sequential elements.

FIG. 8 illustrates example values for sequential elements.

Fig. 9 illustrates an evaluation sequence over time.

Fig. 10A-10C illustrate example peak power patterns.

FIG. 11A illustrates an exemplary matrix.

FIG. 11B illustrates the matrix of FIG. 11A after processing.

Fig. 12 depicts a flow diagram of various processes used during the design and manufacture of integrated circuits, according to some embodiments of the present disclosure.

FIG. 13 depicts a diagram of an example computer system in which embodiments of the present disclosure may operate.

Detailed Description

The present application addresses the power analysis problem of test vectors by eliminating gate level simulation or emulation. Test pattern data is directly calculated using an integrated waveform and power engine approach. In one embodiment, test pattern data is received from an automatic test pattern generator that computes correlation data enabling simulation of a particular pattern or cycle of interest without serially simulating previous cycles to reach the cycle of interest. Using initial state data generated by an automatic test pattern generator enables faster simulation and partial simulation and also eliminates the need to decompress compressed scan chains. The test pattern includes a series of 0/1 values shifted into the silicon device using a serial scan chain. This pattern data set is the value of each sequential cell in the scan chain. From the test pattern data, the system can directly identify the values of all scan elements in the design for the entire test.

If the order values are known, then the values of all the combination units are calculated using waveform calculation techniques. The values of all sequential cells are known from the scan chain; thus, this approach may efficiently compute all nodes in the design. The integrated power engine may then perform a fast approximate power estimation on the gate-level netlist using the waveform values of each node.

This provides fast power estimation. Because the initial state data is applicable to the relevant subset of transitions, the power estimator will provide the data much faster. This power calculation may be performed after each test vector is generated, and any vectors that exceed the maximum power value may be regenerated. This results in a set of test vectors that meet the power requirements.

In one embodiment, the scan vectors are also cascaded to form a series of scan tests. Each of these vectors overlaps with the next/previous set. One vector is read out of the silicon and the next vector is loaded into the silicon. The power calculation is a combination of the switching during the vector read and the switching during the next vector load. Calculating the power of each vector individually allows the system to reorder and calculate the power of all pattern combinations, achieving an optimal order to meet power requirements. Thus, the power estimation system provides a fast, correlated and accurate power estimation for all pattern combinations, enabling the selection of an optimal pattern order for the power requirements of the integrated circuit.

FIG. 1A illustrates one embodiment of a method for testing power estimation of vector stimulation. In one embodiment, the process includes generating a test vector using a test pattern generator at 110. The process further includes simulating or emulating the test vectors on the gate-level netlist with SDF delays at 120. The process further includes saving the waveform in a Fast Signal Database (FSDB) or another waveform format at 130, and performing a cycle-based power analysis using a power analysis system at 140. As will be described in more detail below, the power analysis system determines the peak power and determines whether the test vector meets the power requirements of the circuit.

In one embodiment, a serial scan chain is used to load test vectors into the design. This allows any sequential flip-flop to be controlled by loading the required data through the scan chain. Otherwise, it is difficult or impossible to control these sequential cells using design logic.

FIG. 1B illustrates one embodiment of the present system and method for providing a power estimate. The test pattern generator 150 generates a test pattern and passes the data 160 to the power analyzer 170, which power analyzer 170 generates a peak power map 180. In contrast to the method illustrated in fig. 1A, this method does not utilize gate level simulation. This makes it more efficient in terms of time and computational cost.

FIG. 2 is a block diagram of one embodiment of a power estimation system. The power estimation system 200 includes an automatic test pattern generator 220 and a power analysis system 230. In one embodiment, power estimation system 200 is implemented in a computer system. In one embodiment, different portions of the power estimation system 200 may be implemented in different systems. The power estimation system 200 is used in integrated circuit design and/or verification to ensure that power requirements can be met, as will be discussed below. The present system provides an improved power estimation system that provides technical improvements in the design and testing of circuits such as Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), and the like.

The input to automatic test pattern generator 220 is a design, typically in netlist format 205. The netlist represents the integrated circuit design or a portion of the integrated circuit design. In one embodiment, the test targets are selected by a user via the user interface 210. The test target identifies a subset of the cycles of interest for evaluation. In one embodiment, the test target also identifies portions of the integrated circuit of interest for evaluation. In one embodiment, the system is used to evaluate a subset of cycles that may cause power spikes or exceed capacity. In one embodiment, a user may identify such a cycle. In another embodiment, the other system 215 may identify such loops for evaluation.

An Automatic Test Pattern Generator (ATPG)220 receives a request for the state of sequential elements of a selected shift and/or capture cycle. ATPG 220 provides a value output for the power analysis system. ATPG 220 utilizes test pattern generation to determine the state of the relevant elements of the selected pattern/cycle. The dependent elements may include one or more of scan elements, non-scan elements (sequential or combined). ATPG 220 may output any combination of the initial and final states of the elements.

In one embodiment, the ATPG 220 outputs initial states for all scan elements and non-scan elements whose values can be determined. In one embodiment, this covers most non-scanning elements of the design. In another embodiment, ATPG 220 provides the initial and final states of all the scan and non-scan elements in the design. In another embodiment, ATPG 220 provides the initial states of all the scan and non-scan elements and the initial states of all the combination elements. In another embodiment, ATPG 220 provides the initial and final states of the scan and non-scan elements, and the initial and final states of the combination elements. ATPG 220 is capable of providing the initial states of all scan elements, the initial states of non-scan elements, and the initial states of sequential elements for selected pattern/cycle selection.

In one embodiment, power analysis system 230 receives a value output from ATPG 220. In one embodiment, the value output is uncompressed. In one embodiment, the value output is an initial state of some or all of the elements in the relevant segment of the circuit. In one embodiment, the initial states of the sequential scan, sequential non-scan, and combination elements may be provided to the power analysis system 230. In one embodiment, ATPG 220 provides the compressed output to silicon tester system 280 for manufacturing testing, diagnostics, and failure analysis after the chips are produced. The silicon tester system 280 applies an ATPG pattern to the manufactured devices to verify chip functionality.

Scan logic 235 scans data into scan chain 240. The data used by scan logic 235 is the initial state data provided by ATPG 220. The data in scan chain 240 is then evaluated by waveform evaluator 245 before being scanned out by scan logic 235. The scan input and output may be done in parallel, as will be discussed below. Waveform evaluator 245 can be any waveform evaluator. The waveform evaluator evaluates the design logic between sequential elements to calculate a value of a destination sequential element for one or more cycles of a design evaluation clock.

The combination node calculator 250 uses scan chain based evaluation to calculate the power generated as a combination of the two test patterns, as will be described in more detail below. Matrix logic 255 identifies the ordering of the patterns to select the lowest power value and identifies the lowest power path. Matrix logic 255 utilizes a power matrix that includes power values as an NxN matrix-one row for each pattern to be run first and one column for each pattern to be run second. Matrix logic 255 analyzes the power logic to identify the ordering of the patterns based on the lowest combined power value.

The power estimator 260 performs the tests in the identified order and measures power with the overlapping pattern. In one embodiment, scan chain 240 is used by power estimator 260. The power result is evaluated by the evaluator 265 to determine whether it meets the power criterion. If not, then the regeneration trigger 270 triggers regeneration of the pattern. In one embodiment, the power analysis system 230 may trigger the automatic test pattern generator 220 through an Application Programming Interface (API)275 to generate an updated pattern, or to provide subsequent data.

FIG. 3 is a flow diagram of one embodiment of using a power estimation system. The process begins at 310. In one embodiment, this process is part of the logic design and functional verification process of the circuit design.

At 320, a particular pattern of interest for a given shift and/or acquisition cycle is received by the system. In one embodiment, this data may be selected by the user. In one embodiment, other systems may identify particular patterns that may cause power surges or spikes, and use those patterns.

At 330, ATPG computes state data to be communicated to the power estimator. The state data may include some or all of the sequential scan, sequential non-scan, and combination element initial states for a selected shift/capture cycle. The state data may additionally or alternatively include the final states of these elements.

At 340, the state data is passed to a power estimator. In one embodiment, data is passed from the ATPG in its uncompressed state. In another embodiment, a separate system may be used to decompress the data.

At 350, the scan chain is used to evaluate the power of the pattern of interest. Fig. 4 provides one embodiment of such a calculation. Other methods of calculating power based on the starting and/or ending state of the elements may be used.

At 360, the process determines whether the value is within a range. If the value does not exceed the maximum power nor is it below the threshold, the value is considered to be within the range. If the results are within range, then at 370, the results are output for evaluation. In one embodiment, this may include outputting a power curve for the user on the user interface. The process then ends at 380.

If the result is not within range, the result is discarded at 390 and regeneration of the status data is triggered. In one embodiment, the system may alert the user that the results are out of range. In one embodiment, these results may also be used for evaluation and may be flagged.

FIG. 4 is a flow diagram of one embodiment for evaluating power using a scan chain. In one embodiment, FIG. 4 corresponds to 350 of FIG. 3. Returning to FIG. 4, the process begins at 410 with receiving data from the ATPG.

At 415, the scan data is serially loaded into the flip-flops. The scan data represents the initial state of the element being evaluated as received from the ATPG. The scan data is initial state data received from the ATPG.

At 420, the design is clocked for one or more cycles in normal mode. This moves the state forward for a certain number of cycles.

At 425, the system evaluates the loop and saves the values in sequential units.

At 430, the process determines whether there is more data to evaluate. I.e. whether there is still any unevaluated data. If so, the process continues to 435.

At 435, the result is read out and in parallel, the value for the next evaluation is shifted into the flip-flop. This may enable parallel processing of data and speed up evaluation. The process then returns to 420 to time control the design with additional scan data.

If no further unevaluated data is found at 430, then at block 440, the final set of values is read out of the scan chain. The saved data is then used to calculate power at 445. The process then ends at 450.

FIG. 5 illustrates a simplified diagram of one embodiment of the elements involved in the power estimation process. The scan-in data 510 is serially loaded into flip-flops 520FF _ A1 through FF _ A4.

This scan chain is a set of sequential elements connected and controlled by scan logic. In 'scan mode', the input of each flip-flop is driven from the previous flip-flop in the scan chain. Using this method, sequential elements can be loaded serially using the scan _ enable and scan _ in data pins. For a scan chain with 1000 sequential elements, 1000 clock cycles are required to load all data into the design serially.

The test pattern generator typically generates a set of compressed patterns, which are then decompressed by circuitry present on the silicon. This allows the test pattern to be smaller and, in many cases, multiple scan chain data can be derived from a single compressed test pattern. The uncompressed version is then provided to the present waveform and power calculation system and method.

A subset of the uncompressed version may be provided to the present waveform and power calculation system and method. The test pattern generator may perform some switch-based analysis on the uncompressed pattern to determine which patterns or slices of patterns are more likely to cause peak power events. These patterns or slices can then be analyzed using the described process.

The design is then clocked for one or more cycles in a normal (non-scanning) mode. All design logic 530 will be evaluated and the new design values will be saved in sequential cells FF _ B1 through FF _ B4540. The scan chains are then shifted again, and in one embodiment, the results from the design evaluation phase are shifted out of the design using the same scan chain logic as scan out data 550. For a scan chain with 1000 sequential elements, 1000 clock cycles would be used to read all data serially from the design.

The values of all sequential elements are known during the scan load phase. As shown in FIG. 6, as scan data is loaded into the design, each sequential element at scan chain position # N will have a value specified by scan _ data [ T-N ].

During the evaluation phase of the design, all sequential elements are known. The waveform evaluator may evaluate the design logic between sequential elements to calculate the value of the destination sequential element, as illustrated in FIG. 7. This may be for one cycle, or for any number of design evaluation clocks.

During the scan read phase, the scan chain is used to read out the sequential values from the design. The values of each sequential element flow through the scan chain, and as these values are known from a previous step, each sequential element at position T has a scan _ data [ T + N ], as illustrated in FIG. 8.

In one embodiment, the scan load and scan read phases occur in parallel. When the data values of vector M are read out of the design, the scan chain values of vector M +1 are loaded into the design. A combination of the two versions is used to calculate power. Fig. 9 illustrates a simplified example of this sequence over time. In this example, data is shifted in for four cycles, and then evaluated for one cycle. In this manner, the data is evaluated over time.

To compute the power of the gate level design during the scan load/read phase, the value of each sequential element is used. Waveform evaluation techniques are then applied to calculate the value of each combination node in the circuit without the need for sequential simulation of the design.

To calculate the value of each sequential cell, in one embodiment, two methods are used.

As data is scanned into the design, test vector data will flow through the scan chain. All sequential element values may be determined from the test vector data, e.g., sequential element value [ N ] ═ scan _ vector [ T-N ]

Shifting values from the evaluation phase through the scan chain as data is read out of the design. All sequential element values may be determined from design evaluation data, e.g., sequential element value [ N ] ═ evaluation _ value [ T + N ]

The values of all sequential cells may be determined using the methods described above. Since the order values are now known to the full test vector load/store phase, the values of all the combination nodes can be calculated. This can be achieved by running a simulation method for evaluating all nodes at times t1, t2, t3 or by a waveform evaluation method.

If waveform evaluation is used in one embodiment, each gate in the circuit may be evaluated once. The input pin values are known and the unit can be evaluated once for all output pin values. This has the advantage of eliminating contention and allowing the design to be efficiently scheduled on a multi-threaded or multi-host computing environment. Dynamic scheduling of tasks is simplified because there is no cycle-by-cycle communication between compute threads.

Design evaluation then occurs when the design is brought into normal mode and evaluated for one or more clock cycles. In this case, the design logic is evaluated and the value of each flip-flop is driven, except for the design logic (non-test/scan logic). In one embodiment, evaluation of the design occurs using the same techniques as the scan load/read phase.

Since the waveform is now known to all sequential and combined cells in the design, it can be used in different types of power estimation methods. The method may be more accurate, but more complex and slower, or less accurate, but less complex and faster. This will result in average and peak power results for the test pattern.

In one embodiment, this power calculation may be initiated by the test pattern generator to calculate power. If the power exceeds the maximum value, the test pattern may be discarded and regenerated with a different sequence of values. This results in a set of test patterns that meet the power target.

The power generated during the execution of the test pattern is a combination of the two test patterns. As the results are read from the first test pattern, the next test pattern is read into the design. To calculate the pattern power, both patterns may be obtained and used simultaneously.

This overlap means that the generated power depends on the order of the patterns, and the power can be optimized by reordering the test patterns. The combination of the two patterns may cause high power spikes, but when each of the individual patterns is paired with a different pattern, no spikes are observed.

In one embodiment, the scan flip-flops in the design are in some arbitrary but fixed order as the scan chains are ordered based on layout or other information. Combinational logic driven by a set of sequential elements will have data from both the new scan pattern and from the results of the previous pattern.

The peak power from the various patterns may occur at different cycles within each pattern. Fig. 10A-10C illustrate example peak power patterns.

For example, if the pattern is performed in 1+2+3 order, the peak power of the scan output (cycle 5) of pattern #2 is aligned with the peak power of the scan input (cycle-5) of pattern # 3. If the patterns are reordered to 3+2+1, these peaks do not align and the maximum power is reduced.

In one embodiment, each pattern may be performed with the next/previous data fixed at 0x0 and 0x1 and the pattern power from both runs may be averaged. The power maps for each pair of versions may then be added, with the scan out + scan in times aligned and the peak power calculated.

In one embodiment, each power value is placed into the NxN matrix-one for each pattern to be run first and one column for each pattern to be run next. When a row is a column, the matrix will have a set of blank entries. This matrix is also referred to as a power matrix.

FIG. 11A illustrates an exemplary matrix.

In one embodiment, the process then removes all entries where the power exceeds the maximum value. FIG. 11B illustrates the matrix after such entries are removed. This pattern with any other pattern will exceed the maximum power value if any of the lines are null. In one embodiment, the solution is to remove this pattern and regenerate the pattern. The system may repeat this process until all rows have one or more valid entries.

In one embodiment, the process iterates over the matrix and marks each entry in the matrix with a priority. In one embodiment, the entry in the matrix with the largest power value is the starting point, and then the process proceeds in descending order. In one embodiment, the system removes the entry with the largest value while maintaining 2 values per column and 2 values per row.

In one embodiment, the evaluation process is as follows:

traverse the matrix to produce a test pattern order.

Starting with the cell having the minimum value (in this example, cell 1120 at row 4, column 5 has a value of 1.11).

Identify the test pattern associated with the cell (in this example, test pattern #4 is followed by pattern #5, represented by rows and columns)

Invalidate entire column #4 because this test pattern is now in the test list.

Find the minimum at the row of the second test pattern (here, row #5) (in this example, cell 1130, row #5 and column #6, have a value of 1.19).

Invalidate column # 5.

Repeat until the matrix traversal is complete.

Selecting the minimum value of the column associated with the minimum cell will select the next pattern with the lowest power. When the system traverses the matrix in this manner, it will end up with the lowest power path or nearly the lowest power path. The lowest power path may not be identified because identifying the absolute lowest power path is a problem of NP incompleteness. However, this process selects the near optimal order, even though it may not be the absolute lowest possible order.

In one embodiment, the process performs power estimation using each of the tests in the test sequence and measures power with an overlap pattern. The test pattern power may be different because this uses the actual pattern value of the previous-next pattern rather than the fixed 0x0/0x1 value used earlier in the algorithm. The pattern is loaded through a serial scan chain, so the power used during this load can be calculated by the value each flip-flop will have during this load. However, in one embodiment, as a pattern is loaded, the previous pattern is unloaded at the same time. For example, if the pattern is 1k flip-flops long — when the system has been loaded with 500 bits, the first 500 bits of the scan chain are known from this pattern. The next 500 bits are still set to the value of the previous version being unloaded because the loading and unloading occur simultaneously. This means that the system cannot easily calculate the active power of the offloaded portion, since that active power can be any value. Power is the flip-flop that drives all the combinational logic in the design. For example, in one design, there is an AND gate using flip-flops 500+ 501. The value at flip-flop 500 is known because it was just loaded, but the value of flip-flop 501 is unknown. Thus, the system can calculate the power of N flip-flops that have been loaded, but must guess 0x0 or 0x1 for the remaining flip-flops (which have not yet been loaded, but are being unloaded).

If any pattern pair exceeds the maximum power, the process updates these values in the matrix and repeats the matrix optimization and traversal to obtain the new pattern order. This process is repeated as necessary until the minimum test pattern power is reached. In this manner, the present system provides a method for evaluating power usage of a design without requiring gate level simulation or emulation.

FIG. 12 illustrates an example set of processes 1200 used to transform and verify design data and instructions representing an integrated circuit during design, verification, and manufacture of an article of manufacture, such as an integrated circuit. Each of these processes may be structured and enabled as a plurality of modules or operations. The term 'EDA' denotes the term 'electronic design automation'. These processes begin with the creation of product ideas 1210 using information supplied by designers that is transformed to create an article of manufacture using the EDA process set 1212. When the design is complete, the design is exited 1234 as the original (e.g., geometric pattern) of the integrated circuit is sent to a fabrication facility to fabricate a set of masks that are then used to fabricate the integrated circuit. After exiting, the semiconductor die are fabricated 1236 and a packaging and assembly process 1238 is performed to produce the finished integrated circuit 1240.

The specifications of a circuit or electronic structure may range from low-level transistor material layouts to high-level description languages. High representation levels can be used to design circuits and systems using hardware description languages ('HDL') such as VHDL, Verilog, systemveilog, SystemC, MyHDL, or OpenVera. The HDL description may be transformed into a logic level Register Transfer Level (RTL) description, a gate level description, a layout level description, or a mask level description. Each lower representation level as a more detailed description adds more useful detail to the design description, e.g., more details of the module that includes the description. The lower representation level, which is described in more detail, may be computer generated, derived from a design library, or created by another design automation process. An example of a specification language at the lower presentation language level for specifying more detailed descriptions is SPICE, which is used for detailed descriptions of circuits with many analog components. The description at each representation level is enabled for use by the corresponding tool (e.g., formal verification tool) at that level. The design process may use the sequence depicted in fig. 12. The described process may be enabled by an EDA product (or tool).

During system design 1214, the functionality of the integrated circuit to be fabricated is specified. The design may be optimized for desired characteristics, such as power consumption, performance, area (number of physical and/or code lines), and cost reduction, among others. The design may be divided into different types of modules or components at this stage.

During logic design and functional verification 1216, modules or components in the circuit are specified in one or more description languages and the specification is checked for functional accuracy. For example, components of a circuit may be verified to generate outputs that match the requirements of the specifications of the circuit or system being designed. Functional verification may use simulators and other programs, such as test platform generators, static HDL checkers, and formal verifiers. In some embodiments, a special system called a component of a 'simulator' or 'prototyping system' is used to accelerate functional verification. In one embodiment, the present power type test falls within logic design and functional verification 1216.

During synthesis and design 1218 for testing, the HDL code is transformed into a netlist. In some embodiments, the netlist may be a graph structure, where edges of the graph structure represent components of the circuit and where nodes of the graph structure represent ways of interconnecting the components. Both the HDL code and the netlist are hierarchical artifacts that can be used by EDA products to verify that an integrated circuit, when manufactured, operates according to a specified design. The netlist can be optimized for the target semiconductor manufacturing technology. In addition, the finished integrated circuit may be tested to verify that the integrated circuit meets specification requirements.

During netlist verification 1220, the netlist is checked for compliance with timing constraints and for correspondence with HDL code. During design planning 1222, an overall floorplan for the integrated circuit is constructed and analyzed for timing and top-level routing.

During placement or physical implementation 1224, physical placement (positioning of circuit components such as transistors or capacitors) and routing (connection of circuit components by multiple conductors) occurs and selection of cells from the library to enable specific logic functions may be performed. As used herein, the term 'cell' may specify a set of transistors, other components, AND interconnects that provide a boolean logic function (e.g., AND, OR, NOT, XOR) OR a storage function (e.g., flip-flop OR latch). As used herein, a circuit 'block' may refer to two or more cells. Both the cells and the circuit blocks may be referred to as modules or components and are enabled both as physical structures and in simulation. Parameters, such as size, are specified for the selected cells (based on 'standard cells') and made accessible in the database for use by the EDA product.

During analysis and extraction 1226, circuit functionality is verified at the layout level, which allows for improved layout design. During physical verification 1228, the layout design is checked to ensure that manufacturing constraints are correct, such as DRC constraints, electrical constraints, lithographic constraints, and that the circuitry functionality matches HDL design specifications. During resolution enhancement 1230, the geometry of the layout is transformed to improve the way in which the circuit design is manufactured.

During retirement, data is created for (after applying lithographic enhancements, where appropriate) production of lithographic masks. During mask data preparation 1232, the 'exit' data is used to produce a photolithographic mask for use in producing a finished integrated circuit.

The storage subsystem of a computer system (e.g., computer system 1200 of FIG. 12 or host system 1007 of FIG. 10) may be used to store programs and data structures used by some or all of the EDA products described herein, as well as products for cell development of libraries and physical and logical design using libraries.

Fig. 13 illustrates an example machine of a computer system 1300 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In alternative implementations, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and/or the internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer computer in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

The machine may be a Personal Computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

The example computer system 1300 includes a processing device 1302, a main memory 1304 (e.g., Read Only Memory (ROM), flash memory, Dynamic Random Access Memory (DRAM) (e.g., synchronous DRAM (sdram)), static memory 1306 (e.g., flash memory, Static Random Access Memory (SRAM), etc.), and a data storage device 1318, which communicate with each other over a bus 1330.

The processing device 1302 represents one or more processors, such as microprocessors, central processing units, and the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, Reduced Instruction Set Computing (RISC) microprocessor, Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. The processing device 1302 may also be one or more special-purpose processing devices such as an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), network processor, or the like. The processing device 1302 may be configured to execute the instructions 1326 to perform the operations and steps described herein.

The computer system 1300 may further include a network interface device 1308 for communicating over a network 1320. Computer system 1300 may also include a video display component 1310 (e.g., a Liquid Crystal Display (LCD) or a Cathode Ray Tube (CRT)), an alphanumeric input device 1312 (e.g., a keyboard), a cursor control device 1314 (e.g., a mouse), a graphics processing component 1322, a signal generation device 1316 (e.g., a speaker), a graphics processing component 1322, a video processing component 1328, and an audio processing component 1332.

The data storage 1318 may include a machine-readable storage medium 1324 (also referred to as a non-transitory computer-readable medium) on which is stored one or more sets of instructions 1326 or software embodying any one or more of the methodologies or functions described herein. The instructions 1326 may also reside, completely or at least partially, within the main memory 1304 and/or within the processing device 1302 during execution thereof by the computer system 1300, the main memory 1304 and the processing device 1302 also constituting machine-readable storage media.

In some implementations, the instructions 1326 include instructions for implementing functionality corresponding to the present disclosure. While the machine-readable storage medium 1324 is shown in an example implementation to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine and processing device 1302 to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is a sequence of operations that can be performed to achieve a desired result. The operations are those requiring physical manipulations of physical quantities. Such quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. As is apparent from the present disclosure, unless specifically stated otherwise, it is appreciated that throughout the description, certain terms refer to the actions and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage devices.

The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purposes, or it may comprise a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), Random Access Memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and each coupled to a computer system bus.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various other systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the method. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the disclosure as described herein.

The present disclosure may be provided as a computer program product or software which may include a machine-readable medium having stored thereon instructions which may be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) -readable storage medium, such as read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, and so forth.

In the foregoing disclosure, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. Detailed description of embodiments of the invention reference is made to the accompanying drawings in which like references indicate similar elements, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Those skilled in the art will understand that other embodiments may be utilized and that logical, mechanical, electrical, functional, and other changes may be made without departing from the scope of the present invention.

It will be evident that various modifications may be made thereto without departing from the broader spirit and scope of embodiments of the disclosure as set forth in the following claims. Where this disclosure refers to some elements in the singular, more than one element may be depicted in the figures and like reference numerals designate like elements. Accordingly, the present disclosure and the figures are to be regarded as illustrative rather than restrictive, and the scope of the disclosure is defined solely by the appended claims.