Quantum feature nuclear alignment
阅读说明：本技术 量子特征核对齐 (Quantum feature nuclear alignment ) 是由 J.M.甘贝塔 J.R.格利克 P.K.特米 T.P.古加拉蒂 于 2020-03-26 设计创作，主要内容包括：说明性实施例提供了一种用于使用混合经典-量子计算系统的量子特征核对齐的方法、系统和计算机程序产品。一种用于混合经典-量子决策器训练的方法的实施例包括接收训练数据集。在实施例中,该方法包括由第一处理器从训练集中选择采样对象,每个对象由至少一个向量表示。在实施例中,该方法包括由量子处理器将量子特征映射集应用于所选择的对象,量子映射集对应于量子核集。在实施例中,该方法包括由量子处理器评估与量子特征映射集中的至少一个量子特征映射相对应的量子特征映射电路的参数集。(The illustrative embodiments provide a method, system, and computer program product for quantum feature core alignment using a hybrid classical-quantum computing system. An embodiment of a method for hybrid classical-quantum decision maker training includes receiving a training data set. In an embodiment, the method includes selecting, by a first processor, a sample object from a training set, each object represented by at least one vector. In an embodiment, the method includes applying, by the quantum processor, a quantum feature mapping set to the selected object, the quantum mapping set corresponding to a quantum core set. In an embodiment, the method includes evaluating, by a quantum processor, a set of parameters of a quantum feature mapping circuit corresponding to at least one quantum feature map of a set of quantum feature maps.)
1. A method for hybrid classical-quantum decision maker training, the method comprising:
receiving a training data set;
selecting, by a first processor, a sample object from the training set, each object represented by at least one vector;
applying, by a quantum processor, a set of quantum feature mappings to the selected object, the set of quantum mappings corresponding to a set of quantum cores;
evaluating, by a quantum processor, a set of parameters of a quantum feature mapping circuit corresponding to at least one quantum feature mapping of the set of quantum feature mappings;
determining, by the first processor, a new set of parameters for the quantum feature mapping circuit; and
parameterizing, by the first processor, the quantum feature mapping circuit using the new set of parameters.
2. The method of claim 1, further comprising:
varying the amplitude of the microwave pulses of the quantum processor to parameterize the quantum feature mapping circuit.
3. The method of claim 1, further comprising:
varying the phase of the microwave pulses of the quantum processor to parameterize the quantum feature mapping circuit.
4. The method of claim 1, further comprising:
determining that the new set of parameters yields an accurate measurement that is greater than a predetermined threshold.
5. The method of claim 1, further comprising:
applying the parameterized quantum feature mapping circuit to the selected sample object to compute a new output vector.
6. The method of claim 1, wherein the quantum feature mapping circuit comprises a set of single qubit rotation gates.
7. The method of claim 6, wherein the subset of the set of single qubit rotation gates comprises a rotation angle.
8. The method of claim 7, wherein the rotation angle corresponds to the new parameter set.
9. The method of claim 1, wherein the first processor is a classical processor.
10. The method of claim 1, wherein the set of parameters corresponds to a set of weights and biases for a neural network.
11. The method of claim 1, wherein the quantum feature mapping circuit comprises a set of controlled phase gates.
12. The method of claim 11, wherein the set of controlled phase gates comprises a phase gate angle.
13. The method of claim 12, wherein the phase gate angle corresponds to the parameter set.
14. A computer usable program product comprising one or more computer readable storage devices and program instructions stored on at least one of the one or more storage devices, the stored program instructions comprising:
program instructions for receiving a training data set;
program instructions for selecting, by a first processor, a sample object from the training set, each object represented by at least one vector;
program instructions for applying, by a quantum processor, a quantum feature mapping set to the selected object, the quantum mapping set corresponding to a quantum core set;
program instructions for evaluating, by a quantum processor, a set of parameters of a quantum feature mapping circuit corresponding to at least one quantum feature map of the set of quantum feature maps;
program instructions for determining, by the first processor, a new set of parameters for the quantum feature mapping circuit; and
program instructions for parameterizing, by the first processor, the quantum feature mapping circuit using the new set of parameters.
15. The computer usable program product of claim 14, further comprising:
program instructions for varying the amplitude of the microwave pulses of the quantum processor to parameterize the quantum feature mapping circuit.
16. The computer usable program product of claim 14, further comprising:
program instructions for changing the phase of the microwave pulses of the quantum processor to parameterize the quantum feature mapping circuit.
17. The computer usable program product of claim 14, further comprising:
program instructions for determining that the new set of parameters yields an accurate measurement that is greater than a predetermined threshold.
18. The computer usable program product of claim 14, wherein the computer usable code is stored in a computer readable storage device in a data processing system, and wherein the program instructions are transmitted from a remote data processing system over a network.
19. The computer usable program product of claim 14, wherein the program instructions are stored in a computer readable storage device in a server data processing system, and wherein the program instructions are downloaded over a network to a remote data processing system for a computer readable storage device associated with the remote data processing system.
20. A computer system comprising one or more processors, one or more computer-readable memories, one or more computer-readable storage devices, program instructions for execution stored on at least one of the one or more storage devices for execution by at least one of the one or more processors via at least one of the one or more memories, the stored program instructions comprising:
program instructions for receiving a training data set;
program instructions for selecting, by a first processor, a sample object from the training set, each object represented by at least one vector;
program instructions for applying, by a quantum processor, a quantum feature mapping set to the selected object, the quantum mapping set corresponding to a quantum core set;
program instructions for evaluating, by a quantum processor, a set of parameters of a quantum feature mapping circuit corresponding to at least one quantum feature mapping of the set of quantum feature mappings;
program instructions for determining, by the first processor, a new set of parameters for the quantum feature mapping circuit; and
program instructions for parameterizing, by the first processor, the quantum feature mapping circuit using the new set of parameters.
21. The system of claim 20, wherein the stored program instructions comprise:
program instructions for varying the amplitude of the microwave pulses of the quantum processor to parameterize the quantum feature mapping circuit.
22. The system of claim 20, wherein the stored program instructions comprise:
program instructions for changing the phase of the microwave pulses of the quantum processor to parameterize the quantum feature mapping circuit.
23. The system of claim 20, wherein the stored program instructions comprise:
program instructions for determining that the new set of parameters yields an accurate measurement that is greater than a predetermined threshold.
24. The system of claim 20, wherein the stored program instructions comprise:
program instructions to apply the parameterized quantum feature mapping circuit to the selected sample object to compute a new output vector.
25. The system of claim 20, wherein the quantum feature mapping circuitry comprises a set of single-qubit rotation gates.
26. The system of claim 25, wherein the subset of the set of single qubit rotation gates comprises a rotation angle.
27. The system of claim 26, wherein the angle of rotation corresponds to the new set of parameters.
28. The system of claim 20, wherein the first processor is a classical processor.
29. The system of claim 20, wherein the set of parameters correspond to a set of weights and biases for a neural network.
30. The system of claim 20, wherein the quantum feature mapping circuitry comprises a set of controlled phase gates.
31. The system of claim 30, wherein the set of controlled phase gates comprises a phase gate angle.
32. The method of claim 31, wherein the phase gate angle corresponds to the parameter set.
33. A computer program comprising program code means adapted to perform the method of any of claims 1 to 13 when said program is run on a computer.
Technical Field
The present invention relates generally to quantum classifier training using quantum computation. More particularly, the present invention relates to a system and method of quantum feature kernel alignment (kernel alignment) for training using classifiers and other quantum decision systems of hybrid classical-quantum computing systems.
Background
In the following, unless expressly distinguished when used, the "Q" prefix in a word or phrase indicates a reference to the word or phrase in a quantum computing context.
Molecular and subatomic particles follow the laws of quantum mechanics, a branch of physics exploring how the physical world works on the most fundamental layers. At this level, the particles behave in a strange way, while assuming more than one state and interacting with other particles very far away. Quantum computing exploits these quantum phenomena to process information.
The computer we now commonly use is referred to as the classic computer (also referred to herein as the "legacy" computer or legacy node, or "CN"). Conventional computers use conventional processors fabricated using semiconductor materials and technologies, semiconductor memory, and magnetic or solid state memory devices, which are known as von neumann architectures. In particular, the processor in the conventional computer is a binary processor, i.e., operates on binary data represented by 1 and 0.
Quantum processors (q-processors) use the unique properties of entangled qubit devices (referred to herein simply as "qubits") to perform computational tasks. In the particular field of quantum mechanical operation, particles of matter can exist in a variety of states, such as "on" states, "off" states, and both "on" and "off" states. Where binary computations using semiconductor processors are limited to using only on and off states (corresponding to 1's and 0's in a binary code), quantum processors utilize the quantum states of these substances to output signals that can be used for data computation.
Conventional computers encode information in bits. Each bit may take a value of 1 or 0. These 1's and 0's serve as switches that ultimately drive the computer functions on/off. Quantum computers, on the other hand, are based on qubits, operating according to two key principles of quantum physics: stacking and entanglement. Superposition means that each qubit can represent a 1 and 0 inference between the possible outcomes of an event. Entanglement means that qubits in a superposition can be related to each other in a non-classical way; that is, the state of one qubit (whether 1 or 0 or both) may depend on the state of the other qubit, and when the two quanta are entangled, they contain more information than the two individual qubits.
Using these two principles, qubits operate as information processors, enabling quantum computers to operate in a manner that allows them to solve certain difficult problems that are difficult to handle using conventional computers.
In conventional circuits, serially arranged boolean logic gates manipulate a series of bits. Gate logic techniques for optimizing binary computations are well known. Circuit optimization software for conventional circuits aims to improve efficiency and reduce complexity of conventional circuits. Circuit optimization software for conventional circuits operates in part by breaking down the overall desired behavior of the conventional circuit into simpler functions. Conventional circuit optimization software is easier to manipulate and handle simpler functions. Circuit optimization software generates an efficient layout of design elements on a conventional circuit. Thus, circuit optimization software for conventional circuits significantly reduces resource requirements, thereby improving efficiency and reducing complexity.
The illustrative embodiments recognize that in quantum circuits, quantum gates manipulate qubits to perform quantum computations. A quantum gate is a unitary matrix transform that acts on a qubit. Due to superposition and entanglement of the qubits, the quantum gates represent a 2n × 2n matrix, where n is the number of qubits manipulated by the quantum gates. Illustrative embodiments recognize that the decomposition of such a matrix transform quickly becomes too complex to be performed manually, since the size of the matrix transform increases exponentially with the number of quantum bits. For example, a 2-qubit quantum computer requires a 4 × 4 matrix operator to represent the quantum gate. A 10-qubit quantum computer requires 1024 x 1024 matrix operators to represent the quantum gates. As a result of the exponential increase, the manual quantum logic gate matrix transformation quickly becomes unmanageable as the number of quantum bits increases.
Circuit optimization for quantum circuits depends on the selected function, resource requirements, and other design criteria for the quantum circuit. For example, quantum circuits are typically optimized to work with a particular device.
Disclosure of Invention
According to one aspect, there is provided a method for hybrid classical-quantum decision maker training, the method comprising: receiving a training data set; selecting, by a first processor, a sample object from a training set, each object represented by at least one vector; applying, by a quantum processor, a quantum feature mapping set to the selected object, the quantum mapping set corresponding to a quantum kernel set; evaluating, by a quantum processor, a set of parameters of a quantum feature mapping circuit corresponding to at least one quantum feature mapping of the set of quantum feature mappings; determining, by the first processor, a new set of parameters for the quantum feature mapping circuit; and parameterizing, by the first processor, the quantum feature mapping circuit using the new set of parameters.
According to another aspect, a computer usable program product is provided that includes one or more computer readable storage devices, and program instructions stored on at least one of the one or more storage devices, the stored program instructions including: program instructions for receiving a training data set; program instructions for selecting, by a first processor, a sample object from a training set, each object represented by at least one vector; program instructions for applying, by a quantum processor, a quantum feature mapping set to the selected object, the quantum mapping set corresponding to a quantum core set; program instructions for evaluating, by a quantum processor, a set of parameters of a quantum feature mapping circuit corresponding to at least one quantum feature map of the set of quantum feature maps; program instructions for determining, by the first processor, a new set of parameters for the quantum feature mapping circuit; and program instructions for parameterizing, by the first processor, the quantum feature mapping circuit using the new set of parameters.
According to another aspect, a computer system is provided that includes one or more processors, one or more computer-readable memories, one or more computer-readable storage devices, program instructions for execution stored on at least one of the one or more storage devices for execution by at least one of the one or more processors via at least one of the one or more memories. The stored program instructions include: program instructions for receiving a training data set; program instructions for selecting, by a first processor, a sample object from a training set, each object represented by at least one vector; program instructions for applying, by a quantum processor, a quantum feature mapping set to the selected object, the quantum mapping set corresponding to a quantum core set; program instructions for evaluating, by a quantum processor, a set of parameters of a quantum feature mapping circuit corresponding to at least one quantum feature map of the set of quantum feature maps; program instructions for determining, by the first processor, a new set of parameters for the quantum feature mapping circuit; and program instructions for parameterizing, by the first processor, the quantum feature mapping circuit using the new set of parameters.
The illustrative embodiments provide a method, system, and computer program product for quantum feature core alignment using a hybrid classical-quantum computing system. An embodiment of a method for hybrid classical-quantum decision maker training includes receiving a training data set. In an embodiment, the method includes selecting, by a first processor, a sample object from a training set, each object represented by at least one vector.
In an embodiment, the method includes applying, by the quantum processor, a set of quantum feature mappings to the selected object, the set of quantum mappings corresponding to a set of quantum cores. In an embodiment, the method includes evaluating, by a quantum processor, a set of parameters of a quantum feature mapping circuit corresponding to at least one quantum feature map of the set of quantum feature maps.
In an embodiment, the method includes determining, by a first processor, a new set of parameters for a quantum feature mapping circuit. In an embodiment, the method includes parameterizing, by the first processor, the quantum feature mapping circuit using the new set of parameters.
In an embodiment, the method includes varying the amplitude of the microwave pulses of the quantum processor to parameterize the quantum feature mapping circuit. In an embodiment, the method includes varying the phase of the microwave pulses of the quantum processor to parameterize the quantum feature mapping circuit.
In an embodiment, the method includes determining that the new set of parameters yields an accurate measurement that is greater than a predetermined threshold. In an embodiment, the method includes applying a parameterized quantum feature mapping circuit to the selected sample object to compute a new output vector.
In an embodiment, the quantum feature mapping circuit comprises a set of single-qubit spin gates. In an embodiment, a subset of the set of single-quantum bit rotation gates includes a rotation angle. In an embodiment, the rotation angle corresponds to a new parameter set. In an embodiment, the first processor is a classical processor.
In an embodiment, the method is embodied in a computer program product comprising one or more computer-readable storage devices and computer-readable program instructions stored on the one or more computer-readable tangible storage devices and executed by one or more processors.
Embodiments include a computer usable program product. The computer usable program product includes a computer readable storage device and program instructions stored on the storage device.
An embodiment includes a computer system. The computer system includes a processor, a computer readable memory, a computer readable storage device, and program instructions stored on the storage device for execution by the processor via the memory.
In an embodiment, the program instructions are stored in a computer readable storage device in the data processing system and the program instructions are transmitted over a network from a remote data processing system.
In an embodiment, the program instructions are stored in a computer readable storage device in a server data processing system, and the program instructions are downloaded over a network to a remote data processing system for use in a computer readable storage device associated with the remote data processing system.
According to a preferred embodiment, the present invention provides an improved method for compilation methods for quantum circuits.
A quantum algorithm represents a set of instructions to be executed on a quantum computer. Illustrative embodiments recognize that quantum algorithms can be modeled as quantum circuits. A quantum circuit is a computational model formed by a set of quantum logic gates that perform respective quantum arithmetic steps.
In Machine learning, a classical Support Vector Machine (SVM) is a supervised learning model associated with a learning algorithm that classifies data into classes. Typically, each of the set of training examples is labeled as belonging to a certain class, and the SVM training algorithm modeling assigns new examples to a particular class. The SVM model represents examples as mapped to points in a feature space such that examples of different classes are divided by gaps in the feature space. Feature mapping refers to a mapping of a set of features representing one or more categories. Feature maps are constructed by specifying a function, called a kernel, that computes the inner product between each pair of data points in the feature space. Using SVM algorithms, new input data is mapped into the same feature space and the class to which it belongs is predicted based on the distance from the new instance to the instance that represents the class with the feature map. Generally, SVMs perform classification by finding a hyperplane that maximizes the boundary between two classes. A hyperplane is a subspace that has one less dimension than its surrounding space, e.g., a three-dimensional space having a two-dimensional hyperplane.
The illustrative embodiments recognize that a quantum decision system (e.g., quantum classifier, quantum regressor, quantum controller, or quantum predictor) may be used to analyze the input data and make decisions about the input data by the quantum classifier. For example, a Quantum classifier (e.g., a Quantum Support Vector Machine (QSVM)) may be used to analyze input data and determine a discrete classification of the input data by a Quantum processor. The quantum processor is capable of generating feature maps that are traditionally difficult to evaluate. The quantum feature map is constructed by specifying a function, called a quantum kernel, which computes the inner product between each pair of data points in the quantum feature space. In other examples, a regressor, controller, or predictor may operate on a continuous spatial entity. A quantum classifier (e.g., QSVM) implements the classifier using a quantum processor with the ability to increase the speed of classification of certain input data. Illustrative embodiments recognize that training quantum classifiers and other quantum decision systems typically require large samples of input data.
One class of problems is known as optimization problems. An optimization problem is a computational problem that is intended to determine the best or optimal solution for different problems, where different problems have multiple possible solutions. For example, the different question may be a famous traveler question that must determine routes between multiple cities so that the traveler covers each of the cities without visiting any of the cities. There are many possible solutions to this problem (routes between cities). The optimization problem associated with the traveler problem is to find the shortest route, i.e., the best or optimal route, from a plurality of possible routes that each satisfy the traveler problem requirements.
Configuring the optimization problem to execute on a computer so that the computer can compute an optimal solution in a limited time is itself a difficult problem. Until recently, the only computing resources available to perform optimization problems were the traditional computers as described herein. Many optimization problems are too difficult or complex for traditional computers to compute in a limited time using reasonable resources. Generally, in this case, an approximate solution that can be calculated in a reasonable time and using reasonable resources is accepted as a near-optimal solution.
The advent of quantum computing has presented the possibility of improvement in many areas of computing, including the computation of optimization problems. Because quantum computing systems can evaluate many solutions from a solution space at once, illustrative embodiments recognize that such systems are particularly well suited for solving optimization problems.
The illustrative embodiments recognize that the kernel determines the geometry of the mapping data in the feature space. The illustrative embodiments also recognize that the kernel thus has a core impact on the performance of the machine learning algorithm. The illustrative embodiments recognize that core alignment is one currently available technique for classical machine learning algorithms to assess the quality of the cores of a given dataset. The core alignment measures the degree of agreement between a given core and a given learning task of a classical machine learning algorithm. The illustrative embodiments recognize that kernel optimization for a given dataset increases the accuracy of the machine learning model.
Drawings
Preferred embodiments of the present invention will now be described, by way of example only, with reference to the following drawings:
FIG. 1 depicts a block diagram of a network of data processing systems in which illustrative embodiments may be implemented;
FIG. 2 depicts a block diagram of a data processing system in which illustrative embodiments may be implemented;
FIG. 3 shows a qubit for a quantum processor in accordance with an illustrative embodiment;
FIG. 4 shows a simplified diagram of a matrix representation of an example generic quantum circuit gate in accordance with an illustrative embodiment;
FIG. 5 shows a block diagram of an example hybrid quantum/classical optimization algorithm for quantum feature kernel alignment using a classical processor and a quantum processor in accordance with an illustrative embodiment;
FIG. 6 shows a block diagram of an example quantum feature mapping circuit for a family of cores using a hybrid classical-quantum computing system in accordance with an illustrative embodiment;
FIG. 7 shows a block diagram of an example quantum feature mapping circuit for another family of cores using a hybrid classical-quantum computing system in accordance with an illustrative embodiment;
FIG. 8 shows a block diagram of an example quantum feature mapping circuit for another family of cores using a hybrid classical-quantum computing system in accordance with an illustrative embodiment;
FIG. 9 shows a block diagram of an example quantum feature mapping circuit for another family of cores using a hybrid classical-quantum computing system in accordance with an illustrative embodiment;
FIG. 10 shows a block diagram of an example configuration of quantum feature core alignment using a hybrid classical-quantum computing system in accordance with an illustrative embodiment;
FIG. 11 shows simulation results of training data for a hybrid classical-quantum system for quantum feature core alignment in accordance with a preferred embodiment; and
FIG. 12 shows a flowchart of an example process for quantum feature core alignment using a hybrid classical-quantum computing system in accordance with an illustrative embodiment.
Detailed Description
Illustrative embodiments used to describe the present invention generally address the above-described problems of using quantum computing to solve computational problems. The illustrative embodiments provide a method and system for quantum feature core alignment using a hybrid classical-quantum computing system.
Embodiments provide a method for quantum feature core alignment using a hybrid classical-quantum computing system. Another embodiment provides a conventional or quantum computer usable program product comprising a computer readable storage device, and program instructions stored on the storage device, the stored program instructions comprising a method for quantum feature core alignment using a hybrid classical-quantum computing system. The instructions can be executed using a conventional or quantum processor. Another embodiment provides a computer system comprising a conventional or quantum processor, a computer readable memory, and a computer readable storage device, and program instructions stored on the storage device for execution by the processor via the memory, the stored program instructions comprising a method for quantum feature core alignment using a hybrid classical-quantum computing system.
One or more embodiments provide a hybrid classical and quantum approach that co-evolves quantum kernels and classical kernel co-optimization. In one or more embodiments, a classical computer is used to store large data sets associated with classification training data and perform kernel alignment optimization, and a quantum computer is used to simultaneously assess the quality of quantum kernels.
In an embodiment, it is assumed that the QSVM constructs the corresponding correct feature map with the correct quantum core exactly. In this embodiment, a limited set of quantum cores is obtained. In a particular embodiment, the quantum core may be based on a circuit description of the quantum circuit. In an embodiment, a classical computer tunes a quantum feature mapping to a dataset. In an embodiment, a classical computer changes parameters of a quantum circuit to tune a quantum feature mapping to a dataset.
For a fixed α, the SVM target (F) is equivalent to the kernel alignment γk： The illustrative embodiments recognize that the support vector weight α is not fixed. Given kernel k, the support vector weights are chosen to maximize F. Learning the boundary-maximization kernel by maximizing alignment:subject to the constraint condition of 0-alpha-C, yTα＝0。
A classical optimizer running on a classical processor learns the boundary-maximization kernel by receiving as input a training sample set S, where: (x)i，yi) I 1, …, n obeys the parameter box constraint C, the number of steps T, the step size { η |)tThe number of gradient rise steps M of the training set is subsampled Step length n'<n is the same as the formula (I). Initializing a random core parameter set, parametersRandom support vector weightsα+＝α，α-α. The optimization program executes the step T ═ 1, … T:
by generating subsets from S random samples
Generating a random vector Δ ∈ { -1,1}m；
Calculating lambda+＝λ+cSPSA，tΔ and λ-＝λ-cSPSA，tΔ, given a constant cSPSA，t；
Computing a quantum-core matrix K on a quantum device+＝K(λ+,S′t) And K-＝K(λ-,S′t)；
Using K+Calculating the gradient g+,t＝▽αF(α+，t，λ+，t) Using K-Calculating the gradient g-,t＝▽αF(α-，t，λ-，t)。
Updating alpha via M-step gradient ascent+,t+1←Proj[α+,t+ηtg+,t]And alpha-,t+1←Proj[α-,t+ηtg-,t]；
Using a cost function F (α)+，t，λ+，t) And F (alpha)-，t，λ-，t) Update λ via SPSA optimization.
Embodiments use an optimized parameter λ*Computing a kernel matrix K (λ)*S). Embodiments calculate support vector weights, biases, and support vectors by solving a standard SVM quadratic.
In an embodiment, a method optimizes the value of an SVM objective function F. In an embodiment, the method minimizes the value of F relative to the quantum core parameter set. In an embodiment, the method maximizes the value of F relative to alignment. In an embodiment, the method maximizes the alignment of the quantum core family.
Accordingly, one or more embodiments provide a system and method of selecting a quantum feature map of a dataset. Various embodiments provide a classical/quantum approach that jointly evolves quantum kernels and a classical kernel alignment function, and a quantum computer is used to simultaneously assess the quality of the quantum kernels.
For clarity of description, and not to imply any limitations on it, some example configurations are used to describe the illustrative embodiments. Numerous variations, adaptations, and modifications of the described configurations to achieve the described objectives will be apparent to those skilled in the art in light of the present disclosure, and are considered to be within the scope of the illustrative embodiments.
Moreover, a simplified diagram of a data processing environment is used in the figures and the illustrative embodiments. In an actual computing environment, there may be additional structures or components not shown or described herein, or structures or components that are different than shown but serve functions similar to those described herein, without departing from the scope of the illustrative embodiments.
Furthermore, the illustrative embodiments are described herein as exemplary only with respect to specific actual or hypothetical components. The steps described by the various illustrative embodiments may be adapted to enhance quantum classification using various components that may be purposefully or repurposed to provide the described functionality within a data processing environment, and such adaptations are considered to be within the scope of the illustrative embodiments.
The illustrative embodiments describe, by way of example, certain types of steps, applications, classical processors, quantum states, classical feature spaces, quantum feature spaces, classical cores, quantum cores, and data processing environments. Any particular manifestation of these and other similar artifacts is not intended to limit the present disclosure. Any suitable representation of these and other similar artifacts may be selected within the scope of the illustrative embodiments.
The examples in this disclosure are for clarity of description only and are not limiting of the illustrative embodiments. Any advantages listed herein are merely examples and are not intended to limit the illustrative embodiments. Additional or different advantages may be realized by the particular illustrative embodiments. Moreover, a particular illustrative embodiment may have some, all, or none of the advantages listed above.
With reference to the figures and in particular with reference to FIGS. 1 and 2, these figures are exemplary diagrams of data processing environments in which the illustrative embodiments may be implemented. Fig. 1 and 2 are only examples and are not intended to assert or imply any limitation with regard to the environments in which different embodiments may be implemented. Particular embodiments may make many modifications to the illustrated environments based on the description below.
FIG. 1 depicts a block diagram of a network of data processing systems in which illustrative embodiments may be implemented. Data processing environment 100 is a network of computers in which the illustrative embodiments may be implemented. Data processing environment 100 includes a network 102. Network 102 is the medium used to provide communications links between various devices and computers connected together within data processing environment 100. Network 102 may include connections, such as wire, wireless communication links, or fiber optic cables.
A client or server is only an example role for certain data processing systems connected to network 102 and is not intended to exclude other configurations or roles of such data processing systems. Classical processing system 104 is coupled to network 102. Classical processing system 104 is a classical processing system. The software application may execute on any quantum data processing system in the data processing environment 100. Any software application executing in the classical processing system 104 described in fig. 1 may be configured to execute in a similar manner in another data processing system. Any data or information stored or generated in the conventional processing system 104 of fig. 1 may be configured to be stored or generated in another data processing system in a similar manner. A classical data processing system (e.g., classical processing system 104) may contain data and may have software applications or software tools that perform classical computational processes on the system.
Server 106 is coupled to network 102 along with storage unit 108. The storage unit 108 includes a database 109, the database 109 configured to store classifier training data as described herein with respect to various embodiments. The server 106 is a conventional data processing system. Quantum processing system 140 is coupled to network 102. The quantum processing system 140 is a quantum data processing system. The software application may execute on any quantum data processing system in the data processing environment 100. Any software application executing in quantum processing system 140 depicted in fig. 1 may be configured to execute in another quantum data processing system in a similar manner. Any data or information stored or generated in quantum processing system 140 in fig. 1 may be configured to be stored or generated in another quantum data processing system in a similar manner. Quantum data processing systems, such as quantum processing system 140, may contain data and may have software applications or software tools that perform quantum computing processes on the system.
Clients 110, 112, and 114 are also coupled to network 102. A conventional data processing system (e.g., server 106 or clients 110, 112, or 114) may contain data and may have software applications or software tools that perform conventional computing processes on the system.
By way of example only, and not to imply any limitations on such architectures, FIG. 1 illustrates certain components that may be used in example implementations of the embodiments. For example, server 106 and clients 110, 112, 114 are depicted as servers and clients merely as examples, and no limitation on the client-server architecture is implied. As another example, embodiments may be distributed across several conventional data processing systems, quantum data processing systems, and data networks shown, while another embodiment may be implemented on a single conventional data processing system or a single quantum data processing system within the scope of the illustrative embodiments. The conventional data processing systems 106, 110, 112, and 114 also represent example nodes in a cluster, partition, and other configuration suitable for implementing embodiments.
Device 132 is an example of a conventional computing device described herein. For example, the device 132 may take the form of a smartphone, tablet computer, laptop computer, fixed or portable form of the client 110, wearable computing device, or any other suitable device. Any software application executing in another conventional data processing system depicted in FIG. 1 may be configured to execute in device 132 in a similar manner. Any data or information stored or generated in another conventional data processing system in fig. 1 may be configured to be stored or generated in device 132 in a similar manner.
Server 106, memory unit 108, classical processing system 104, quantum processing system 140, clients 110, 112, 114, and device 132 may be coupled to network 102 using a wired connection, a wireless communication protocol, or other suitable data connection. Clients 110, 112, and 114 may be, for example, personal computers or network computers.
In the depicted example, server 106 may provide data, such as boot files, operating system images, and applications to clients 110, 112, and 114. Clients 110, 112, and 114 may be clients to server 106 in this example. Clients 110, 112, 114, or some combination thereof, may include their own data, boot files, operating system images, and applications. Data processing environment 100 may include additional servers, clients, and other devices not shown.
In the example shown, memory 124 may provide data, such as boot files, operating system images, and applications to classic processor 122. Classic processor 122 may include its own data, boot files, operating system images, and applications. Data processing environment 100 may include additional memories, quantum processors, and other devices not shown. Memory 124 includes an application 105, which application 105 may be configured to implement one or more classical processor functions described herein for quantum feature kernel alignment on a hybrid classical-quantum computing system according to one or more embodiments.
In the example shown, the memory 144 may provide data, such as boot files, operating system images, and applications to the vector sub-processor 142. Quantum processor 142 may include its own data, boot files, operating system images, and applications. Data processing environment 100 may include additional memory, quantum processors, and other devices not shown. Memory 144 includes an application 146, which application 146 may be configured to implement one or more quantum processor functions described herein, in accordance with one or more embodiments.
In the depicted example, data processing environment 100 may be the Internet. Network 102 may represent a collection of networks and gateways that use the Transmission Control Protocol/internet Protocol (TCP/IP) and other protocols to communicate with one another. At the heart of the Internet is a backbone of data communication links between major nodes or host computers, consisting of thousands of commercial, government, educational and other computer systems that route data and messages. Of course, data processing environment 100 also may be implemented as a number of different types of networks, such as for example, an intranet, a Local Area Network (LAN), or a Wide Area Network (WAN). FIG. 1 is intended as an example, and not as an architectural limitation for different illustrative embodiments.
In other uses, the data processing environment 100 may be used to implement a client-server environment in which the illustrative embodiments may be implemented. The client-server environment enables software applications and data to be distributed across a network such that the applications function using interactivity between a traditional client data processing system and a traditional server data processing system. Data processing environment 100 may also employ a service-oriented architecture in which interoperable software components distributed across a network may be packaged together as a coherent business application. Data processing environment 100 may also take the form of a cloud and employ a cloud computing model of service delivery to enable convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processes, memory, storage, applications, virtual machines, and services) that can be quickly provisioned and released with minimal administrative effort or interaction with a service provider.
With reference to FIG. 2, a block diagram of a data processing system is shown in which illustrative embodiments may be implemented. Data processing system 200 is an example of a conventional computer, such as classic processing system 104, server 106, clients 110, 112, and 114 in FIG. 1, or another type of device in which computer usable program code or instructions implementing the processes may be located to implement the illustrative embodiments.
Data processing system 200 also represents a conventional data processing system or a configuration thereof, such as conventional data processing system 132 in FIG. 1, in which computer usable program code or instructions implementing the processes of the illustrative embodiments may be located. Data processing system 200 is depicted as a computer by way of example only, and is not limited to such. Implementations of other device forms (e.g., device 132 in fig. 1) may modify (e.g., by adding a touch interface) data processing system 200 and even remove certain illustrated components from data processing system 200 without departing from the general description of the operation and functionality of data processing system 200 described herein.
In the depicted example, data processing system 200 employs a Hub architecture including a North Bridge and Memory Controller Hub (NB/MCH)202 and a South Bridge and Input/Output (I/O) Controller Hub (SB/ICH) 204. Processing unit 206, main memory 208, and graphics processor 210 are coupled to north bridge and memory controller hub (NB/MCH) 202. Processing unit 206 may contain one or more processors and may be implemented using one or more heterogeneous processor systems. The processing unit 206 may be a multi-core processor. In some implementations, Graphics processor 210 may be coupled to NB/MCH 202 through an Accelerated Graphics Port (AGP).
In the depicted example, Local Area Network (LAN) adapter 212 is coupled to south bridge and I/O controller hub (SB/ICH) 204. Audio adapter 216, keyboard and mouse adapter 220, modem 222, Read Only Memory (ROM) 224, Universal Serial Bus (USB) and other ports 232, and PCI/PCIe devices 234 couple to south bridge and I/O controller hub 204 through Bus 238. A Hard Disk Drive (HDD) or Solid-State Drive (SSD) 226 and CD-ROM 230 are coupled to south bridge and I/O controller hub 204 through bus 240. PCI/PCIe devices 234 may include, for example, Ethernet adapters, add-in cards, and PC cards for notebook computers. PCI uses a card bus controller, while PCIe does not. ROM 224 may be, for example, a flash Binary Input/Output System (BIOS). Hard disk Drive 226 and CD-ROM 230 may use, for example, Integrated Drive Electronics (IDE), Serial Advanced Technology Attachment (SATA) interfaces, or variants such as external-SATA (eSATA) and micro-SATA (mSATA). Super I/O (SIO) device 236 may be coupled to south bridge and I/O controller hub (SB/ICH)204 through bus 238.
Memories such as main memory 208, ROM 224, or flash memory (not shown) are some examples of computer-usable storage devices. Hard disk drive or solid state drive 226, CD-ROM 230, and other similarly usable devices are some examples of computer usable storage devices including computer usable storage media.
An operating system runs on processing unit 206. The operating system coordinates and provides control of various components within data processing system 200 in FIG. 2. The operating system may be a commercially available operating system for any type of computing platform, including but not limited to server systems, personal computers, and mobile devices. An object oriented or other type of programming system may operate in conjunction with the operating system and provide calls to the operating system from programs or applications executing on data processing system 200.
Instructions for the operating system, the object-oriented programming system, and applications or programs (e.g., application 105 in FIG. 1) are located on storage devices (e.g., in the form of code 226A on hard disk drive 226) and may be loaded into at least one of the one or more memories (e.g., main memory 208) for execution by processing unit 206. The processes of the illustrative embodiments may be performed by processing unit 206 using computer implemented instructions, which may be located in a memory such as, for example, main memory 208, read only memory 224, or in one or more peripheral devices.
Further, in one instance, code 226A can be downloaded from remote system 201B over network 201A, with similar code 201C stored on storage device 201D. In another case, the code 226A may be downloaded to the remote system 201B over the network 201A, where the downloaded code 201C is stored on the storage device 201D.
The hardware in FIGS. 1-2 may vary depending on the implementation. Other internal hardware or peripheral devices, such as flash memory, equivalent non-volatile memory, or optical disk drives and the like, may be used in addition to or in place of the hardware depicted in figures 1-2. Also, the processes of the illustrative embodiments may be applied to a multiprocessor data processing system.
In some illustrative examples, data processing system 200 may be a Personal Digital Assistant (PDA), which is generally configured with flash memory to provide non-volatile memory for storing operating system files and/or user-generated data. A bus system may be comprised of one or more buses, such as a system bus, an I/O bus, and a PCI bus. Of course, the bus system may be implemented using any type of communication fabric or architecture that provides for a transfer of data between different components or devices attached to the fabric or architecture.
A communications unit may include one or more devices used to transmit and receive data, such as a modem or a network adapter. A memory may be, for example, main memory 208 or a cache such as found in north bridge and memory controller hub 202. The processing unit may include one or more processors or CPUs.
1-2 and above-described examples are not meant to imply architectural limitations. For example, data processing system 200 also may be a tablet computer, laptop computer, or telephone device in addition to taking the form of a mobile device or wearable device.
Where a computer or data processing system is described as a virtual machine, virtual appliance, or virtual component, the virtual machine, virtual appliance, or virtual component operates in the manner of data processing system 200 using a virtualized representation of some or all of the components shown in data processing system 200. For example, in a virtual machine, virtual appliance, or virtual component, processing unit 206 appears as a virtualized instance of all or some of the available hardware processing units 206 in a host data processing system, main memory 208 appears as a virtualized instance of all or a portion of main memory 208 available in the host data processing system, and disks 226 appear as virtualized instances of all or a portion of the available disks 226 in the host data processing system. In this case, a host data processing system is represented by data processing system 200.
Referring to fig. 3, a diagram illustrates a qubit for use in a quantum processor (e.g., quantum processor 148 of fig. 1). Qubit 300 includes a capacitor structure 302 and a josephson junction 304. Josephson junctions 304 are formed by separating two thin film superconducting metal layers from a non-superconducting material. When the metal in the superconducting layers becomes superconducting, for example by lowering the temperature of the metal to a certain low temperature, electron pairs can tunnel from one superconducting layer to the other through the non-superconducting layer. In superconducting qubit 300, a Josephson junction 304 having a small inductance is electrically coupled in parallel with a capacitor structure 302 to form a nonlinear resonator.
Referring to fig. 4, a simplified diagram 400 of a matrix representation of an example generic quantum circuit gate is shown, according to an illustrative embodiment. In the illustrated example, matrix representations of bit-flipped non (X), phase-flipped (Z), hadamard (h), phase-shifted (T), controlled non (controlled X or CNOT), and swap gates and corresponding linear equations are shown.
Referring to fig. 5, a block diagram of an example hybrid quantum/classical optimization algorithm for quantum feature nuclear alignment using a classical processor 502 and a quantum processor 504 is shown. In this example, classical processor 502 runs a classical optimization scheme to generate update parameters for the phase alignment algorithm and sends these update parameters to quantum processor 504. The quantum processor 504 prepares a set of quantum feature mapping circuits based on the particular combinatorial problem to be solved and the given update parameters. The quantum processor 504 executes the prepared quantum states and evaluates the set of quantum core families corresponding to the set of quantum feature mapping circuits. In an embodiment, the quantum core set is from a single quantum core family. Classical processor 502 receives these evaluations from quantum processor 504 and evaluates the parameters of the quantum core family to determine whether to update the parameters for the classical optimization scheme.
If classical processor 502 determines that the parameters of the quantum feature core alignment optimization problem are to be updated, classical processor 502 runs a classical optimization scheme using the updated parameters to generate further updated parameters. Classical processor 502 then sends these further updated parameters to quantum processor 504. Typically, this process is repeated until convergence within an acceptable threshold is obtained.
Referring to fig. 6, a block diagram of an example quantum feature mapping circuit 600 using a family of cores of a hybrid classical-quantum computing system is shown in accordance with an illustrative embodiment. In this example, the quantum feature mapping circuit 600 applies a first layer of single qubit single rotation gates followed by a first diagonal phase gate assembly. Diagonal phase gate component computation for quantum feature mapping circuit 600
The quantum feature mapping circuit 600 also applies a second layer of single-qubit single-rotation gates followed by a second diagonal phase-gate assembly. The quantum feature mapping circuit also employs a third diagonal phase gate component followed by a third layer of single qubit single rotation gates. The quantum feature mapping circuit 600 also applies a fourth diagonal phase gate component followed by a fourth layer of single-qubit single-revolution gates. Quantum feature mapping circuit 600 also applies a measurement layer to the set of qubits.
An equivalent circuit is thus obtained to encode both the actual function value of the phase and the fourier transform value of each elementary element. The quantum feature mapping implemented by the quantum feature mapping circuit 600 functions to linearly sort the input data into the classes required by the SVM/QSVM, as it applies a hyperplane to the "boosted" (e.g., eigenmapped applied) data. The rotation angle of each layer of single-qubit single-revolving gates depends on the optimized nuclear parameters.
Referring to fig. 7, a block diagram of an example quantum feature mapping circuit 700 for another family of cores using a hybrid classical-quantum computing system is shown in accordance with an illustrative embodiment. In this example, the quantum feature mapping circuit 700 applies a first tier of single qubit single rotation gates followed by a first tier of controlled phase gates.
The quantum feature mapping circuit 700 also applies a second layer of single-qubit single-rotation gates followed by a second layer of controlled-phase gates. The quantum feature mapping circuit also employs a third layer of single-qubit single-rotation gates. The quantum feature mapping circuit 700 also applies a measurement layer to the set of qubits.
An equivalent circuit is thus obtained to encode both the actual function value of the phase and the fourier transform value of each elementary element. The quantum feature mapping implemented by the quantum feature mapping circuit 700 functions to linearly sort the input data into the classes required by the SVM/QSVM, as it applies a hyperplane to the "boosted" (e.g., eigenmapped applied) data. The rotation angle of each layer of single-qubit single-revolving gates depends on the optimized nuclear parameters.
The quantum feature mapping circuit 700 includes a first portion 702 and a second portion 704. In an embodiment, the first portion 702 is repeated d times, where d is the depth of the quantum feature mapping circuit 700. In an embodiment, second portion 704 is repeated d times, where d is the depth of quantum feature mapping circuit 700.
Referring to fig. 8, a block diagram of an example quantum feature mapping circuit 800 for another family of cores using a hybrid classical-quantum computing system is shown in accordance with an illustrative embodiment. In this example, the quantum feature mapping circuit 800 applies a first layer of Hadamard gates followed by a first diagonal phase gate assembly.
Quantum feature mapping circuit 800 computes the coefficient phi of the classical neural networkS. The classical neural network includes a set of weights and a set of biases. In an embodiment, quantum feature mappingThe quantum core family of circuit 800 includes a set of core parameters that are optimized in the quantum feature core alignment process. In an embodiment, the weight set and the bias set are sets of kernel parameters that are optimized during the quantum feature kernel alignment process. Diagonal phase gate component computation for quantum feature mapping circuit 800
The quantum feature mapping circuit 800 also applies a second layer of Hadamard gates followed by a second diagonal phase gate assembly. The quantum feature mapping circuit also applies a third diagonal phase gate component followed by a third layer of Hadamard gates. The quantum feature mapping circuit 800 also applies a fourth diagonal phase gate component followed by a fourth layer of Hadamard gates.
The quantum feature mapping circuit 800 also applies a measurement layer to the set of qubits. An equivalent circuit is thus obtained to encode both the actual function value of the phase and the fourier transform value of each elementary element. The quantum feature mapping implemented by quantum feature mapping circuit 800 functions to linearly sort the input data into the classes required by the SVM/QSVM because it applies the hyperplane to "boosted"
On the data (e.g., to which the feature map applies). The rotation angle of each layer of single-qubit single-revolving gates depends on the optimized nuclear parameters.
Referring to fig. 9, a block diagram of an example quantum feature mapping circuit 900 for another family of cores using a hybrid classical-quantum computing system is shown in accordance with an illustrative embodiment. In this example, the quantum feature mapping circuit 900 applies a first layer of single qubit single rotation gates in a first direction followed by a second layer of single qubit single rotation gates in a second direction.
The quantum feature mapping circuit 900 also applies a first layer of controlled phase gates followed by a second layer of controlled phase gates. The quantum feature mapping circuit 900 also applies a third layer of single-qubit single-rotation gates in the second direction, followed by a fourth layer of single-qubit single-rotation gates in the first direction. The quantum feature mapping circuit 900 also applies a measurement layer to the set of qubits.
The quantum feature mapping circuit 900 includes a first portion 902 and a second portion 904. In an embodiment, the first portion 902 is repeated d times, where d is the depth of the quantum feature mapping circuit 900. In an embodiment, the second portion 904 is repeated d times, where d is the depth of the quantum feature mapping circuit 900.
An equivalent circuit is thus obtained to encode both the actual function value of the phase and the fourier transform value of each elementary element. The quantum feature mapping operation implemented by the quantum feature mapping circuit 900 will linearly sort the input data into the classes required by the SVM/QSVM, as it applies a hyperplane to the "boosted" (e.g., feature mapped applied) data. The rotation angle of each layer of single-qubit single-revolving gates depends on the optimized nuclear parameters.
Referring to fig. 10, a block diagram of an example configuration 1000 of quantum feature core alignment using a hybrid classical-quantum computing system is shown in accordance with an illustrative embodiment. The example embodiment includes a classical processing system 104 and a quantum processing system 140. Classical processing system 104 includes application 1002. In certain embodiments, application 1002 is an example of application 105 of FIG. 1, application 1002 being configured to receive data 1004. In one or more embodiments, data 1004 includes one or more training data for training a classifier and input data for classification using the trained classifier. Application 1002 includes a sample selection component 1006, a core check component 1008, and a quantum parameter update component 1010. Quantum processing system 140 includes quantum processor 142, quantum mapping function computation component 1012, set of quantum core families 1014, and quantum mapping core evaluation component 1016.
In this embodiment, the sample selection component 1006 is configured to select samples of objects from the training data and provide the sampled objects to the quantum processor 142 of the quantum processing system 140. The quantum mapping function computation component 1012 is configured to apply a set of quantum feature mappings corresponding to a set of quantum core families 1014 to a sample object configured as an input vector to generate an output vector. The quantum core evaluation component 1016 is configured to determine a quality metric for at least one quantum feature map in a set of quantum feature maps corresponding to a set of quantum core families 1014.
A check component 1008 is configured to identify a best quality quantum feature mapping circuit corresponding to data 1004 using the determined quality metrics and parameters from the quantum feature mapping circuit. The quantum parameter update component 1010 is configured to compute a new set of parameters for the quantum feature mapping circuit and determine whether the current function produces a hybrid classical and quantum classifier with acceptable accuracy. In an embodiment, these parameters are managed by a plurality of variable microwave pulses on the quantum processor 142. In a particular embodiment, the microwave pulse is parameterized by varying the amplitude of the microwave pulse. In a particular embodiment, the microwave pulse is parameterized by changing its phase.
Referring to fig. 11, a graph shows simulation results of training data for a hybrid quantum-classical system for quantum feature nuclear alignment. The hybrid quantum-classical system (the training data of which is shown in fig. 11) is based on the quantum feature mapping circuit 400 illustrated in fig. 6.
In fig. 11, these graphs represent the computational cost and alignment of a 2-qubit quantum processor. The alignment map compares the parameterized kernels for the quantum feature mapping circuit with the kernels used to generate the training data. The alignment graph shows the alignment of the parameterized kernel approaching 100%.
Referring to fig. 12, a flowchart of an example process 1200 for quantum feature core alignment using a hybrid classical-quantum computing system is shown in accordance with an illustrative embodiment. In block 1202, the classical processor 122 receives a training data set containing training objects associated with one or more classification categories. In a particular embodiment, the objects within the training data are represented by one or more vectors. In block 1204, classical processor 122 selects a sample of the object from the training dataset. In a particular embodiment, classical processor 122 selects an object from the training set using random sampling. In one or more particular embodiments, classical distance measurements are used to randomly select objects.
In block 1206, classical processor 122 parameterizes the quantum feature mapping circuit. In block 1208, the quantum processor 142 applies a set of quantum feature maps corresponding to the set of quantum cores to the input vector of the sample object to compute an output vector. In an alternative embodiment, classical processing system 104 uses simulation to apply an input vector to a quantum feature map to generate an output vector. In block 1210, the quantum processor 142 evaluates the set of quantum cores.
In block 1212, classical processor 122 determines a new set of parameters for the quantum feature mapping circuit. In block 1214, classical processor 122 reparameterizes the quantum feature mapping circuit with the new set of parameters. In block 1216, classical processor 122 determines whether the new (updated) quantum feature mapping circuit produces an acceptable level of accuracy, e.g., an accurate measurement that is greater than a predetermined threshold. In an embodiment, the hybrid quantum/classical optimization algorithm 500 optimizes the value of the SVM objective function F. In an embodiment, a classical processor changes a set of parameters of a quantum core to minimize a SVM objective function F with respect to the set of quantum core parameters. In an embodiment, the hybrid quantum/classical optimization algorithm 500 maximizes the SVM objective function with respect to the alignment of the quantum kernels.
If the new set of parameters does not result in a quantum feature mapping circuit with an acceptable level of precision, process 1200 proceeds to block 1208. In block 1208, the quantum processor 142 determines a new quantum core that should be applied. Accordingly, portions of process 1200 are iteratively repeated until an acceptable level of accuracy is obtained. If, in block 1216 the exemplary processor 122 determines that an acceptable level of accuracy has been achieved by the updated parameters of the current quantum feature map, the process 1200 ends. Thus, a trained mixed classical-quantum classifier is generated. Upon receiving input data that is desired to be classified, the hybrid classical-quantum classifier classifies the received input data to determine a class of the input data.
Accordingly, a computer-implemented method, system or apparatus, and computer program product are provided in the illustrative embodiments for quantum-space distance assessment trained using classifiers and other quantum decision systems that blend classical-quantum computing systems and other related features, functions or operations. Where an embodiment or a portion of an embodiment is described with respect to a type of device, a computer-implemented method, system or apparatus, computer program product, or portion thereof is adapted or configured for use with an appropriate and comparable representation of the type of device.
Where embodiments are described as being implemented in an application, delivery of the application in a "Software as a Service" (SaaS) model is considered to be within the scope of the illustrative embodiments. In the SaaS model, the capabilities of application embodiments are provided to users by executing applications in the cloud infrastructure. A user may access an application through a thin client interface, such as a web browser (e.g., web-based email) or other lightweight client application, using various client devices. The user does not manage or control the underlying cloud infrastructure, including the network, servers, operating system, or storage of the cloud infrastructure. In some cases, the user may not even manage or control the capabilities of the SaaS application. In some other cases, SaaS implementations of applications may allow for possible exceptions to limited user-specific application configuration settings.
The present invention may be a system, method, and/or computer program product with any possible level of technical detail integration. The computer program product may include a computer-readable storage medium having computer-readable program instructions thereon for causing a processor to perform various aspects of the present invention.
The computer readable storage medium may be a tangible device capable of retaining and storing instructions for use by the instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic memory device, a magnetic memory device, an optical memory device, an electromagnetic memory device, a semiconductor memory device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard Disk, a Random Access Memory (RAM), a Read-Only Memory (ROM), an Erasable Programmable Read-Only Memory (EPROM or flash Memory), a Static Random Access Memory (SRAM), a portable Compact Disc Read-Only Memory (CD-ROM), a Digital Versatile Disc (DVD), a Memory stick, a floppy Disk, a mechanical coding device (e.g., a punch card or a raised structure with instructions recorded in a recess), and any suitable combination of the preceding. Computer-readable storage media, including but not limited to computer-readable storage devices as used herein, should not be construed as inherently transient signals such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., optical pulses through fiber optic cables), or electrical signals propagating through wires.
The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a corresponding computing/processing device, or to an external computer or external storage device via a network (e.g., the internet, a local area network, a wide area network, and/or a wireless network). The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers and/or edge servers. The network adapter card or network interface in each computing/processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium within the respective computing/processing device.
The computer-readable program instructions for carrying out operations of the present invention may be assembler instructions, Instruction Set-Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, or source or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C + +, or the like, and a procedural programming language such as the "C" programming language or a similar programming language. The computer-readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of Network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, to perform aspects of the invention, an electronic circuit (e.g., including a Programmable Logic circuit, a Field-Programmable Gate Array (FPGA), or a Programmable Logic Array (PLA)) may personalize the electronic circuit by executing computer-readable program instructions using state information of the computer-readable program instructions.
Aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.
These computer-readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer-readable storage medium having the instructions stored therein comprises an artifact including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks.
The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.