阅读说明：本技术 卫星火工品等效电路、控制方法和试验装置 (Satellite initiating explosive device equivalent circuit, control method and test device ) 是由 闫奎 孙奎 陈明花 杨磊雨 朱新波 王君磊 于 2021-08-19 设计创作，主要内容包括：本发明提供了一种卫星火工品等效电路、控制方法和试验装置,包括：数字控制电路、恒流负载电路、状态检测电路,所述数字控制电路与恒流负载电路连接,所述状态检测电路与数字控制电路连接。本发明采用采用DA输出控制运算放大器与MOS管模拟火工品恒流负载特性,通过状态检测电路与数字控制电路实现恒流负载持续时间控制,从而模拟卫星火工品起爆过程的瞬态电流特性,适用于各卫星火工品驱动电路调试测试、火工品等效试验。(The invention provides a satellite initiating explosive device equivalent circuit, a control method and a test device, which comprise the following steps: the circuit comprises a digital control circuit, a constant current load circuit and a state detection circuit, wherein the digital control circuit is connected with the constant current load circuit, and the state detection circuit is connected with the digital control circuit. The invention adopts DA output control operational amplifier and MOS tube to simulate the constant current load characteristic of the initiating explosive device, and realizes the constant current load duration control through the state detection circuit and the digital control circuit, thereby simulating the transient current characteristic of the satellite initiating explosive device in the detonation process, and being suitable for debugging test of each satellite initiating explosive device driving circuit and initiating explosive device equivalent test.)

1. A satellite initiating explosive device equivalent circuit, comprising: the circuit comprises a digital control circuit, a constant current load circuit and a state detection circuit, wherein the digital control circuit is connected with the constant current load circuit, and the state detection circuit is connected with the digital control circuit.

2. The satellite initiating explosive device equivalent circuit according to claim 1, wherein: the digital control circuit comprises a first FPGA chip U6, a first DA converter U1 and a first AD converter U2, wherein one end of the first DA converter U1 and one end of the first AD converter U2 are connected with the first FPGA chip U6.

3. The satellite initiating explosive device equivalent circuit according to claim 1, wherein: the constant current load circuit comprises a first operational amplifier U3, a second operational amplifier U4, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first MOS transistor Q1, a first triode Q2 and a second triode Q3; the non-inverting input end of the first operational amplifier U3 is connected with the other end of a first DA converter U1, the inverting input end of the first operational amplifier U3 is connected with the other end of a first AD converter U2, the output end of a second operational amplifier U4 and one end of an eighth resistor R8 respectively, the output end of the first operational amplifier U3 is connected with one end of a third resistor R3, the other end of the third resistor R3 is connected with the base of a first triode Q2 and the collector of a second triode Q3 respectively, the base of the second triode Q3 is connected with a first FPGA chip U6, the emitter of the second triode Q3 is connected with the emitter of a first triode Q2 and grounded, the collector of the first triode Q42 is connected with one end of a second resistor R2, the other end of the second resistor R2 is connected with one end of a first resistor 46R 1 and the gate of a first MOS transistor Q1 respectively, and the other end of the first resistor R1 is connected with the source MOS 57324, the drain electrode of the first MOS transistor is respectively connected with one end of a first resistor R4 and one end of a fifth resistor R5, the non-inverting input end of the second operational amplifier U4 is respectively connected with the other end of the fifth resistor R5 and one end of the second resistor R6, the other end of the sixth resistor R6 is grounded, the inverting input end of the second operational amplifier U4 is respectively connected with one end of a seventh resistor R7 and the other end of an eighth resistor R8, and the other end of the seventh resistor R7 is connected with the other end of the fourth resistor R4 and grounded.

4. The satellite initiating explosive device equivalent circuit according to claim 1, wherein: the state detection circuit comprises a ninth resistor R9, a tenth resistor R10 and a first optical coupler U5, one end of the ninth resistor R9 is connected with a source electrode of a first MOS transistor Q1 and forms a VIN + end, the other end of the ninth resistor R9 is connected with one end of a tenth resistor R10 and an input end of the first optical coupler U5, the other end of the tenth resistor R10 is connected with the other end of a fourth resistor R4 and forms a VIN end, and an output end of the first optical coupler U5 is connected with a first FPGA chip U6.

5. The utility model provides a satellite initiating explosive device test device which characterized in that: comprising the satellite initiating explosive device equivalent circuit according to any one of claims 1 to 4.

6. A satellite initiating explosive device equivalent circuit control method which adopts the satellite initiating explosive device equivalent circuit of any one of claims 1 to 4 and is characterized by comprising the following steps:

step S1: setting an initiating explosive device equivalent current through a first FPGA chip U6 and a first DA converter U1, and collecting a load current waveform of a constant current load circuit through a first FPGA chip U6 and a first DA converter U1;

step S2: when initiating explosive device detonation driving voltage signals are input, the constant-current load circuit works, and the first operational amplifier U3 and the second operational amplifier U4 form a feedback system to control a first MOS transistor Q1 power loop to work according to given current;

step S3: when an initiating explosive device detonation driving voltage signal is input, the first optocoupler U5 detects input voltage and generates a timing trigger signal, the first FPGA chip U6 receives the trigger signal and counts the equivalent current duration of the pneumatic initiating explosive device, the constant current load is turned off through the second triode Q3 after set time is reached, and meanwhile, the given current output of the first DA converter is modified to be 0.

7. The satellite initiating explosive device equivalent circuit control method according to claim 6, characterized in that: in the step S2, the resistance values of the fifth resistor R5 and the seventh resistor R7 are equal, the resistance values of the sixth resistor R6 and the eighth resistor are equal, and the given voltage of the first DA converter U1 is Vref, so that the constant current load current is:

Technical Field

The invention relates to a circuit and a control method thereof, in particular to a satellite initiating explosive device equivalent circuit, a control method and a test device.

Background

The initiating explosive device is widely applied to a satellite unlocking device, the single-path initiating explosive device detonates current of 5A-10A, the current duration is different from 200us to 10ms, and the width of a satellite control instruction is 80ms or 160 ms. The initiating explosive device driving circuit debugging test and the whole-satellite initiating explosive device equivalent realization adopt resistance equivalent, the loop current is influenced by the test loop impedance, and the current duration is the same as the instruction time, so the safety is ensured by reducing the equivalent resistance, and the testing process cannot truly realize the equivalent initiating explosive device characteristics. The testing mode can not meet the requirement of testing the performance of the driving circuit of the initiating explosive device.

In patent document CN200910195295.1, the detection function of the detonation path of a multi-path initiating explosive device can be realized; the intelligent initiating explosive device equivalent device and pulse time sequence signal measuring method CN201210021810.6 can realize the driving voltage and time sequence detection of initiating explosive devices. Compared with the prior art, the invention can not only finish the voltage and instruction time sequence detection of the detonation channel of the multi-channel initiating explosive device, but also simulate the load characteristic of the real initiating explosive device, and can more effectively realize the detection of the functions and the performances of the driving circuit and the loop of the initiating explosive device.

In patent document CN201420642708.2, "an explosive device equivalent device capable of repeatedly using and simulating instantaneous interruption characteristic", a delay relay is used to realize the simulation of instantaneous interruption characteristic of an explosive device, and the simulation time is 100 ms. Compared with the prior art, the method can simulate the real fusing time characteristic of the initiating explosive device, can set the fusing time, is suitable for simulating the instantaneous breaking characteristics of the initiating explosive devices with different characteristics, and can more effectively realize the performance detection of the initiating explosive device driving circuit.

Chinese patent publication No. CN103997031A discloses an initiating explosive device control circuit and a controller using the same, the control circuit comprises an initiating explosive device control branch or a plurality of initiating explosive device control branches connected in parallel, the initiating explosive device control branch circuits are used for controlling initiating explosive devices to detonate, each initiating explosive device control branch circuit comprises one initiating explosive device bridge wire or a plurality of initiating explosive device bridge wires connected in parallel, the common positive end of all the initiating explosive device control branch circuits is connected with the positive end of a power supply through a first control switch, the common negative end of all the initiating explosive device control branch circuits is connected with the negative end of the power supply through a second control switch, the first control switch and the second control switch are used for controlling the on-off of the initiating explosive device control circuit, each initiating explosive device control branch further comprises a detonation switch, and the detonation switch is used for controlling the on-off of each initiating explosive device control branch.

Disclosure of Invention

Aiming at the defects in the prior art, the invention aims to provide a satellite initiating explosive device equivalent circuit, a control method and a test device.

The invention provides a satellite initiating explosive device equivalent circuit, which comprises: the circuit comprises a digital control circuit, a constant current load circuit and a state detection circuit, wherein the digital control circuit is connected with the constant current load circuit, and the state detection circuit is connected with the digital control circuit.

Preferably, the digital control circuit comprises a first FPGA chip U6, a first DA converter U1 and a first AD converter U2, and one end of the first DA converter U1 and one end of the first AD converter U2 are connected to the first FPGA chip U6.

Preferably, the constant current load circuit includes a first operational amplifier U3, a second operational amplifier U4, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first MOS transistor Q1, a first triode Q2, and a second triode Q3; the non-inverting input end of the first operational amplifier U3 is connected with the other end of a first DA converter U1, the inverting input end of the first operational amplifier U3 is connected with the other end of a first AD converter U2, the output end of a second operational amplifier U4 and one end of an eighth resistor R8 respectively, the output end of the first operational amplifier U3 is connected with one end of a third resistor R3, the other end of the third resistor R3 is connected with the base of a first triode Q2 and the collector of a second triode Q3 respectively, the base of the second triode Q3 is connected with a first FPGA chip U6, the emitter of the second triode Q3 is connected with the emitter of a first triode Q2 and grounded, the collector of the first triode Q42 is connected with one end of a second resistor R2, the other end of the second resistor R2 is connected with one end of a first resistor 46R 1 and the gate of a first MOS transistor Q1 respectively, and the other end of the first resistor R1 is connected with the source MOS 57324, the drain electrode of the first MOS transistor is respectively connected with one end of a first resistor R4 and one end of a fifth resistor R5, the non-inverting input end of the second operational amplifier U4 is respectively connected with the other end of the fifth resistor R5 and one end of the second resistor R6, the other end of the sixth resistor R6 is grounded, the inverting input end of the second operational amplifier U4 is respectively connected with one end of a seventh resistor R7 and the other end of an eighth resistor R8, and the other end of the seventh resistor R7 is connected with the other end of the fourth resistor R4 and grounded.

Preferably, the state detection circuit includes a ninth resistor R9, a tenth resistor R10 and a first optical coupler U5, one end of the ninth resistor R9 is connected with the source of the first MOS transistor Q1 and constitutes a VIN + end, the other end of the ninth resistor R9 is connected with one end of the tenth resistor R10 and the input end of the first optical coupler U5, the other end of the tenth resistor R10 is connected with the other end of the fourth resistor R4 and constitutes a VIN-end, and the output end of the first optical coupler U5 is connected with the first FPGA chip U6.

The satellite initiating explosive device testing device comprises the satellite initiating explosive device equivalent circuit.

The invention provides a satellite initiating explosive device equivalent circuit control method, which comprises the following steps:

step S1: setting an initiating explosive device equivalent current through a first FPGA chip U6 and a first DA converter U1, and collecting a load current waveform of a constant current load circuit through a first FPGA chip U6 and a first DA converter U1;

step S2: when initiating explosive device detonation driving voltage signals are input, the constant-current load circuit works, and the first operational amplifier U3 and the second operational amplifier U4 form a feedback system to control a first MOS transistor Q1 power loop to work according to given current;

step S3: when an initiating explosive device detonation driving voltage signal is input, the first optocoupler U5 detects input voltage and generates a timing trigger signal, the first FPGA chip U6 receives the trigger signal and counts the equivalent current duration of the pneumatic initiating explosive device, the constant current load is turned off through the second triode Q3 after set time is reached, and meanwhile, the given current output of the first DA converter is modified to be 0.

Preferably, in the step S2, the fifth resistor R5 and the seventh resistor R7 have the same resistance value, the sixth resistor R6 and the eighth resistor have the same resistance value, and the given voltage of the first DA converter U1 is Vref, so that the constant current load current is:

compared with the prior art, the invention has the following beneficial effects:

1. the invention adopts DA output control operational amplifier and MOS tube to simulate the constant current load characteristic of the initiating explosive device, and realizes the control of the duration time of the constant current load through a state detection circuit and a digital control circuit, thereby simulating the transient current characteristic of the initiating explosive device of a satellite in the process of detonation;

2. the equivalent circuit provided by the invention is suitable for debugging and testing of the driving circuit of the initiating explosive device of each satellite and an initiating explosive device equivalent test;

3. the equivalent circuit provided by the invention has higher test safety.

Drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:

fig. 1 is a schematic diagram of an equivalent circuit of a satellite initiating explosive device and a control method thereof according to an embodiment of the invention.

Detailed Description

The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.

The invention provides a satellite initiating explosive device equivalent circuit, which comprises: the circuit comprises a digital control circuit, a constant current load circuit and a state detection circuit, wherein the digital control circuit is connected with the constant current load circuit, and the state detection circuit is connected with the digital control circuit.

The digital control circuit comprises a first FPGA chip U6, a first DA converter U1 and a first AD converter U2, wherein one end of the first DA converter U1 and one end of the first AD converter U2 are connected with the first FPGA chip U6.

The constant current load circuit comprises a first operational amplifier U3, a second operational amplifier U4, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first MOS transistor Q1, a first triode Q2 and a second triode Q3; the non-inverting input end of the first operational amplifier U3 is connected with the other end of a first DA converter U1, the inverting input end of the first operational amplifier U3 is connected with the other end of a first AD converter U2, the output end of a second operational amplifier U4 and one end of an eighth resistor R8 respectively, the output end of the first operational amplifier U3 is connected with one end of a third resistor R3, the other end of the third resistor R3 is connected with the base of a first triode Q2 and the collector of a second triode Q3 respectively, the base of the second triode Q3 is connected with a first FPGA chip U6, the emitter of the second triode Q3 is connected with the emitter of a first triode Q2 and grounded, the collector of the first triode Q42 is connected with one end of a second resistor R2, the other end of the second resistor R2 is connected with one end of a first resistor 46R 1 and the gate of a first MOS transistor Q1 respectively, and the other end of the first resistor R1 is connected with the source MOS 57324, the drain electrode of the first MOS transistor is respectively connected with one end of a first resistor R4 and one end of a fifth resistor R5, the non-inverting input end of the second operational amplifier U4 is respectively connected with the other end of the fifth resistor R5 and one end of the second resistor R6, the other end of the sixth resistor R6 is grounded, the inverting input end of the second operational amplifier U4 is respectively connected with one end of a seventh resistor R7 and the other end of an eighth resistor R8, and the other end of the seventh resistor R7 is connected with the other end of the fourth resistor R4 and grounded.

The state detection circuit comprises a ninth resistor R9, a tenth resistor R10 and a first optical coupler U5, one end of the ninth resistor R9 is connected with a source electrode of a first MOS transistor Q1 and forms a VIN + end, the other end of the ninth resistor R9 is connected with one end of a tenth resistor R10 and an input end of the first optical coupler U5, the other end of the tenth resistor R10 is connected with the other end of a fourth resistor R4 and forms a VIN end, and an output end of the first optical coupler U5 is connected with a first FPGA chip U6.

The invention provides a control method of an equivalent circuit of a satellite initiating explosive device, which adopts the equivalent circuit of the satellite initiating explosive device and comprises the following steps:

step S1: the equivalent current of the initiating explosive device is set through the first FPGA chip U6 and the first DA converter U1, and the load current waveform of the constant-current load circuit is collected through the first FPGA chip U6 and the first DA converter U1. The current value and the current duration are set through the first FPGA chip U6, the current value is 1A-10A adjustable, the current duration is not more than 80ms, the first FPGA chip U6 and the first DA converter U1 achieve setting of equivalent current of initiating explosive devices, the set current value is output through the first DA converter U1 and serves as current setting of a constant current load circuit, and the first FPGA chip U6 and the first DA converter U1 achieve collection of load current waveforms.

Step S2: when initiating explosive device detonation driving voltage signals are input, the constant current load circuit works, the first operational amplifier U3 and the second operational amplifier U4 form a feedback system to control a first MOS transistor Q1 power loop to work according to given current, R5 is R7, R6 is R8, and when DA given voltage is Vref, the constant current load current is as follows:

step S3: when an initiating explosive device detonation driving voltage signal is input, the first optocoupler U5 detects input voltage and generates a timing trigger signal, the first FPGA chip U6 receives the trigger signal and counts the equivalent current duration of the pneumatic initiating explosive device, the constant current load is turned off through the second triode Q3 after set time is reached, and meanwhile, the given current output of the first DA converter is modified to be 0.

The invention also introduces a satellite initiating explosive device testing device which adopts the satellite initiating explosive device equivalent circuit and is not described herein again.

Those skilled in the art will appreciate that, in addition to implementing the system and its various devices, modules, units provided by the present invention as pure computer readable program code, the system and its various devices, modules, units provided by the present invention can be fully implemented by logically programming method steps in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Therefore, the system and various devices, modules and units thereof provided by the invention can be regarded as a hardware component, and the devices, modules and units included in the system for realizing various functions can also be regarded as structures in the hardware component; means, modules, units for performing the various functions may also be regarded as structures within both software modules and hardware components for performing the method.

The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.