阅读说明：本技术 一种可自调整的过流保护电路 (Self-adjustable over-current protection circuit ) 是由 刘玉山 仝刚 张梁堂 于 2020-05-19 设计创作，主要内容包括：一种可自调整的过流保护电路包括供电电源,N型场效应管MN1、MN2、MN3、MN4、MN5、MN6,P型场效应管MP1、MP2、MP3、MP4、MP5,电阻R1、R2、R3、R4、寄生电阻Rsen和负载LOAD；所述N型场效应管MN1和MN2为电流镜结构,P型场效应管MP2、MP3、MP4同样为电流镜结构,N型场效应管MN3和MN4接成电流镜结构。R4跨接在P型场效应管MP5和N型场效应管MN5组成的反相器的输入和输出两端,用于设定反相器的直流工作点,使其工作于线性区域,该反相器的输出为OCP过流输出控制信号。本发明专利在芯片应用于高电压条件时,减小芯片过流点,而当芯片应用于低电压条件时,增大芯片的过流点,从而在安全可靠的前提下最大限度的发挥电源管理芯片的性能。(A self-adjustable over-current protection circuit comprises a power supply, N-type field effect transistors MN1, MN2, MN3, MN4, MN5 and MN6, P-type field effect transistors MP1, MP2, MP3, MP4 and MP5, resistors R1, R2, R3 and R4, a parasitic resistor Rsen and a LOAD LOAD; the N-type field effect transistors MN1 and MN2 are in current mirror structures, the P-type field effect transistors MP2, MP3 and MP4 are also in current mirror structures, and the N-type field effect transistors MN3 and MN4 are connected into a current mirror structure. R4 is connected across the input and output ends of the inverter composed of P-type FET MP5 and N-type FET MN5, and is used to set the DC operating point of the inverter to make it work in the linear region, and the output of the inverter is the OCP overcurrent output control signal. When the chip is applied to a high voltage condition, the overcurrent point of the chip is reduced, and when the chip is applied to a low voltage condition, the overcurrent point of the chip is increased, so that the performance of the power management chip is exerted to the maximum extent on the premise of safety and reliability.)

1. The utility model provides a but overcurrent protection circuit of self-adjusting which characterized in that: the power supply comprises a power supply source, N-type field effect transistors MN1, MN2, MN3, MN4, MN5 and MN6, P-type field effect transistors MP1, MP2, MP3, MP4 and MP5, resistors R1, R2, R3 and R4, a parasitic resistor Rsen and a LOAD LOAD; the power supply comprises a main power source VCC and a stabilized power source VDD, the main power source VCC follows the change of power supply voltage, and the stabilized power source VDD is a stabilized power source adjusted from the main power source VCC and supplies power to a chip internal function module; the resistors R1 and R2 are connected between the main power VCC and the ground wire in series; the grid electrode of the P-type field effect transistor MP1 is connected between the resistors R1 and R2, the drain electrode of the P-type field effect transistor MP1 is connected with a stable power supply VDD, and the source electrode of the P-type field effect transistor MP1 is grounded after being connected with the N-type field effect transistor MN 1; the N-type field effect transistor MN1 and the N-type field effect transistor MN2 are connected to form a current mirror structure, the grid electrode of the N-type field effect transistor MN1 is connected with two ends of the drain electrode, and the drain electrode of the N-type field effect transistor MN2 is connected with the P-type field effect transistor MP2 and then connected with a stable power supply VDD; the P-type field effect transistors MP2, MP3 and MP4 are connected into a current mirror structure, the grid electrode of the P-type field effect transistor MP2 is connected with two ends of the source electrode, and the source electrode of the P-type field effect transistor MP3 is connected with the drain electrode of the N-type field effect transistor MN 3; the N-type field effect transistor MN3 and the MN4 are connected into a current mirror structure, the grid electrode of the N-type field effect transistor MN3 is connected with two ends of the drain electrode, the source electrode is connected with the resistor R3 and then grounded, the substrate is connected with the source electrode of the N-type field effect transistor MN4, and the drain electrode of the N-type field effect transistor MN4 is connected with the source electrode of the P-type field effect transistor MP 4; the P-type field effect transistor MP5 and the N-type field effect transistor MN5 form an inverter, the input end of the inverter is connected between the N-type field effect transistor MN4 and the P-type field effect transistor MP4, and the output end of the inverter outputs an OCP overcurrent output control signal; the resistor R4 is connected across the input and output ends of the inverter; the drain electrode of the P-type field effect transistor MP5 is connected with the drain electrodes of the P-type field effect transistors MP2, MP3 and MP4, and the source electrode of the N-type field effect transistor MN5 is grounded; the N-type field effect transistor MN6 is an output power transistor, the source electrode of the N-type field effect transistor MN is grounded through a parasitic resistor Rsen, the source electrode of the N-type field effect transistor MN4 is connected, the substrate is grounded, the drain electrode of the N-type field effect transistor MN is connected with a LOAD to a main power VCC, and the grid electrode of the N-type field effect transistor MN is connected with a GATE signal.

Technical Field

The present invention relates to an overcurrent protection circuit, and more particularly, to an overcurrent protection circuit capable of self-adjustment.

Background

The overcurrent protection circuit is a common protection circuit in a power management chip, and has the function of switching off the output of the chip when the chip load is short-circuited or overloaded, so that the safety and reliability of the power chip and the whole system are protected.

With the wider application of electronic products, the operating voltage range of electronic products is also wider. The overcurrent point of the traditional overcurrent protection circuit is a constant value, namely the trigger current of the overcurrent protection is unchanged regardless of the power supply voltage of the chip. The setting of a constant value of the overcurrent causes two problems: 1. when the overcurrent value is set to be higher, if the chip works under the condition of low working voltage, the chip can normally respond to the overcurrent condition, and when the chip works under the condition of high voltage, the chip can be burnt out due to higher power consumption; 2. when the overcurrent value is set to be low, if the chip works under the conditions of high working voltage and low working voltage, the chip can normally respond to the overcurrent condition, but the current output capability of the chip is limited.

Disclosure of Invention

In order to solve the above problems, an object of the present invention is to provide an over-current protection circuit that can be self-adjusted according to the magnitude of the chip supply voltage.

In order to achieve the purpose, the technical scheme of the invention is as follows: an overcurrent protection circuit capable of self-adjusting comprises a power supply, N-type field effect transistors MN1, MN2, MN3, MN4, MN5 and MN6, P-type field effect transistors MP1, MP2, MP3, MP4 and MP5, resistors R1, R2, R3 and R4, a parasitic resistor Rsen and a LOAD LOAD; the power supply comprises a main power source VCC and a stabilized power source VDD, the main power source VCC follows the change of power supply voltage, and the stabilized power source VDD is a stabilized power source adjusted from the main power source VCC and supplies power to a chip internal function module; the resistors R1 and R2 are connected between the main power VCC and the ground wire in series; the grid electrode of the P-type field effect transistor MP1 is connected between the resistors R1 and R2, the drain electrode of the P-type field effect transistor MP1 is connected with a stable power supply VDD, and the source electrode of the P-type field effect transistor MP1 is grounded after being connected with the N-type field effect transistor MN 1; the N-type field effect transistor MN1 and the N-type field effect transistor MN2 are connected to form a current mirror structure, the grid electrode of the N-type field effect transistor MN1 is connected with two ends of the drain electrode, and the drain electrode of the N-type field effect transistor MN2 is connected with the P-type field effect transistor MP2 and then connected with a stable power supply VDD; the P-type field effect transistors MP2, MP3 and MP4 are connected into a current mirror structure, the grid electrode of the P-type field effect transistor MP2 is connected with two ends of the source electrode, and the source electrode of the P-type field effect transistor MP3 is connected with the drain electrode of the N-type field effect transistor MN 3; the N-type field effect transistor MN3 and the MN4 are connected into a current mirror structure, the grid electrode of the N-type field effect transistor MN3 is connected with two ends of the drain electrode, the source electrode is connected with the resistor R3 and then grounded, the substrate is connected with the source electrode of the N-type field effect transistor MN4, and the drain electrode of the N-type field effect transistor MN4 is connected with the source electrode of the P-type field effect transistor MP 4; the P-type field effect transistor MP5 and the N-type field effect transistor MN5 form an inverter, the input end of the inverter is connected between the N-type field effect transistor MN4 and the P-type field effect transistor MP4, and the output end of the inverter outputs an OCP overcurrent output control signal; the resistor R4 is connected across the input and output ends of the inverter; the drain electrode of the P-type field effect transistor MP5 is connected with the drain electrodes of the P-type field effect transistors MP2, MP3 and MP4, and the source electrode of the N-type field effect transistor MN5 is grounded; the N-type field effect transistor MN6 is an output power transistor, the source electrode of the N-type field effect transistor MN is grounded through a parasitic resistor Rsen, the source electrode of the N-type field effect transistor MN4 is connected, the substrate is grounded, the drain electrode of the N-type field effect transistor MN is connected with a LOAD to a main power VCC, and the grid electrode of the N-type field effect transistor MN is connected with a GATE signal.

The invention has the beneficial effects that: when the chip is applied to a high voltage condition, the overcurrent point of the chip is reduced, and when the chip is applied to a low voltage condition, the overcurrent point of the chip is increased, so that the performance of the power management chip is exerted to the maximum extent on the premise of safety and reliability.

Drawings

FIG. 1 is a schematic structural view of the present invention; FIG. 2 is a schematic diagram of the relationship between voltage and current according to the present invention.

Detailed Description

The following detailed description of embodiments of the invention refers to the accompanying drawings.

As shown in fig. 1: an overcurrent protection circuit capable of self-adjusting comprises a power supply, N-type field effect transistors MN1, MN2, MN3, MN4, MN5 and MN6, P-type field effect transistors MP1, MP2, MP3, MP4 and MP5, resistors R1, R2, R3 and R4, a parasitic resistor Rsen and a LOAD LOAD; the power supply comprises a main power source VCC and a stabilized power source VDD, the main power source VCC follows the change of power supply voltage, and the stabilized power source VDD is a stabilized power source adjusted from the main power source VCC and supplies power to a chip internal function module; the resistors R1 and R2 are connected between the main power VCC and the ground wire in series; the grid electrode of the P-type field effect transistor MP1 is connected between the resistors R1 and R2, the drain electrode of the P-type field effect transistor MP1 is connected with a stable power supply VDD, and the source electrode of the P-type field effect transistor MP1 is grounded after being connected with the N-type field effect transistor MN 1; the N-type field effect transistor MN1 and the N-type field effect transistor MN2 are connected to form a current mirror structure, the grid electrode of the N-type field effect transistor MN1 is connected with two ends of the drain electrode, and the drain electrode of the N-type field effect transistor MN2 is connected with the P-type field effect transistor MP2 and then connected with a stable power supply VDD; the P-type field effect transistors MP2, MP3 and MP4 are connected into a current mirror structure, the grid electrode of the P-type field effect transistor MP2 is connected with two ends of the source electrode, and the source electrode of the P-type field effect transistor MP3 is connected with the drain electrode of the N-type field effect transistor MN 3; the N-type field effect transistor MN3 and the MN4 are connected into a current mirror structure, the grid electrode of the N-type field effect transistor MN3 is connected with two ends of the drain electrode, the source electrode is connected with the resistor R3 and then grounded, the substrate is connected with the source electrode of the N-type field effect transistor MN4, and the drain electrode of the N-type field effect transistor MN4 is connected with the source electrode of the P-type field effect transistor MP 4; the P-type field effect transistor MP5 and the N-type field effect transistor MN5 form an inverter, the input end of the inverter is connected between the N-type field effect transistor MN4 and the P-type field effect transistor MP4, and the output end of the inverter outputs an OCP overcurrent output control signal; the resistor R4 is connected across the input and output ends of the inverter; the drain electrode of the P-type field effect transistor MP5 is connected with the drain electrodes of the P-type field effect transistors MP2, MP3 and MP4, and the source electrode of the N-type field effect transistor MN5 is grounded; the N-type field effect transistor MN6 is an output power transistor, the source electrode of the N-type field effect transistor MN is grounded through a parasitic resistor Rsen, the source electrode of the N-type field effect transistor MN4 is connected, the substrate is grounded, the drain electrode of the N-type field effect transistor MN is connected with a LOAD to a main power VCC, and the grid electrode of the N-type field effect transistor MN is connected with a GATE signal.

The resistors R1 and R2 are connected in series to sample the main power VCC voltage, R1>>R2, the gate voltage of the pfet MP1 is small, VCC R2/(R1+ R2), so when | VDS is satisfied_MP1|<<2(|VGS_MP1|-|VTH_PI) condition, P-FET MP1 operates in the deep linear region with drain current ID_MP1The characteristic tends to follow | VGS_MP1The | voltage is linear:

ID_MP1≈u_p*Cox*(W/L)*(|VGS_MP1|-|VTH_P|)*|VDS_MP1| …………………………………（1）

wherein u is_pIs the carrier mobility in P-type field effect transistor, Cox is the unit area gate oxide capacitance, W and L are the gate width and length of P-type field effect transistor, | VGS_MP1| is the absolute value of the gate-source voltage, | VTH of the P-type field effect transistor MP1_PI is the absolute value of the threshold voltage of the P-type field effect transistor, | VDS_MP1And | is the source-drain power supply absolute value of the P-type field effect transistor MP 1. I VDS_MP1I is close to a constant value, so the leakage current ID of the P-type field effect transistor_MP1Magnitude of the gate-source voltage | VGS_MP1| is approximately linear.

The N-type field effect transistors MN1 and MN2 are of current mirror structures, the P-type field effect transistors MP2, MP3 and MP4 are of current mirror structures, the N-type field effect transistors MN3 and MN4 are connected into a current mirror structure, the source electrode of the N-type field effect transistor MN3 is connected with the resistor R3, and the substrate is connected with the source electrode of the N-type field effect transistor MN 4. R4 is connected across the input and output ends of the inverter composed of P-type FET MP5 and N-type FET MN5, and is used to set the DC operating point of the inverter to make it work in the linear region, and the output of the inverter is the OCP overcurrent output control signal. The N-type fet MN6 is an output power transistor, and its GATE is controlled by the GATE signal to turn on or off, the source is connected to the parasitic resistor Rsen to ground, and the drain is connected to the LOAD to the main power VCC.

In practical chip application, the output nfet 6 has a large current flowing through it, which generally reaches several amperes, so that the parasitic resistance (metal top layer resistance is adopted in general integrated circuit) from the source of the output fet MN6 to GND, i.e. Rsen, is not negligible, the chip draws a voltage (which can reflect the power transistor current to some extent) from the parasitic resistance Rsen, sends the voltage to the source of the fet MN4, compares the voltage drop of the source current of the fet MN3 on the resistor R3, and obtains an OCP control signal through an inverter composed of the P-type fet MP5 and the fet MN 5. When the product of the drain current of the output power tube MN6 and the parasitic resistance Rsen is smaller than the product of the drain current of the nfet MN3 and the resistance R3, that is:

ID_MN6*Rsen < ID_MN3*R3 ………………………………………………………………（2）

the output of the OCP control signal is high level, and the output state of the chip is judged to be normal; when the product of the drain current of the output power tube MN6 and the parasitic resistance Rsen is larger than the product of the drain current of the nfet MN3 and the resistance R3, that is:

ID_MN6*Rsen > ID_MN3*R3 ………………………………………………………………（3）

the output of the OCP control signal is low level, the output of the chip is judged to be over-current, the output power tube MN6 is turned off through the processing of other logic part circuits in the chip by the OCP control signal, and the safety of the chip and the load is ensured.

The following describes a schematic relationship between the voltage and the current of the overcurrent protection circuit, as shown in fig. 2: the main power VCC is a chip main power, and power supply voltages are different along with different chip applications. The VDD is a regulated VDD, which is a constant voltage, and supplies power to the internal functional module of the chip. The IMP3 is the source-drain current of the P-type field effect transistor MP3, the value of the source-drain current is in a proportional relation with the source-drain current of the P-type field effect transistor MP1, the value of the source-drain current is equal to the source-drain current of the N-type field effect transistor MN3, and the change of the power supply voltage of the main power supply VCC is reflected. Under the condition that a stable power supply VDD is stable, along with the increase of a main power supply VCC power supply voltage, the current of IMP3 is reduced, the source-drain current of an N-type field effect transistor MN3 is also reduced, and through the fact that the product of the drain current of the N-type field effect transistor MN6 and a parasitic resistor Rsen is smaller than the product relation of the drain current of an N-type field effect transistor MN3 and a resistor R3, the fact that the overcurrent protection point of the whole chip also changes in proportion along with IMP3 can be obtained, and the method is shown in FIG. 2. Therefore, when the voltage of the main power VCC power supply rises, the over-current protection point Ilimit of the whole chip is reduced; when the voltage of a main power VCC power supply is reduced, the over-current protection point Ilimit of the whole chip is increased, so that the function of self-adjusting the over-current protection point of the chip along with the size of the power supply voltage is realized.

While the preferred embodiments of the present invention have been illustrated and described, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.