阅读说明：本技术 电容式感测设备及感测电容的方法 (Capacitive sensing apparatus and method of sensing capacitance ) 是由 于学球 石亦欣 罗挺松 姜英 林楠 彭媛 俞军 于 2020-05-19 设计创作，主要内容包括：本申请实施例提供一种电容式感测设备和感测电容的方法。电容式感测设备包括：电容式传感器,其适于感测接近其的导电物体；开关组,其适于将电容式传感器交替地耦接第一预定电压和参考电容；参考电容,其适于在感测导电物体时与电容式传感器分享电荷；比较器,其具有第一输入端、第二输入端和输出端,第一输入端耦接参考电容,第二输入端耦接参考电压,输出端耦接电荷平衡电路和计数器；电荷平衡电路,其耦接参考电容,并适于在感测导电物体时对参考电容进行充电或放电；计数器,其适于基于比较器输出的第一或第二逻辑电平而计数并且获得计数值。本申请实施例的技术方案有利于感测灵敏度的提高,避免由于感测周期的增大而带来的功耗增加。(Embodiments of the present application provide a capacitive sensing apparatus and a method of sensing capacitance. The capacitive sensing apparatus includes: a capacitive sensor adapted to sense a conductive object proximate thereto; a switch bank adapted to alternately couple the capacitive sensor to a first predetermined voltage and a reference capacitance; a reference capacitance adapted to share charge with the capacitive sensor when sensing a conductive object; the comparator is provided with a first input end, a second input end and an output end, wherein the first input end is coupled with the reference capacitor, the second input end is coupled with the reference voltage, and the output end is coupled with the charge balance circuit and the counter; a charge balance circuit coupled to the reference capacitor and adapted to charge or discharge the reference capacitor when sensing the conductive object; a counter adapted to count based on the first or second logic level of the comparator output and obtain a count value. The technical scheme of the embodiment of the application is favorable for improving the sensing sensitivity, and avoids the increase of power consumption caused by the increase of the sensing period.)

1. A capacitive sensing apparatus, comprising:

a capacitive sensor adapted to sense a conductive object proximate thereto;

a switch bank adapted to alternately couple the capacitive sensor to a first predetermined voltage and a reference capacitance;

the reference capacitance adapted to share charge with the capacitive sensor when sensing the conductive object;

a comparator having a first input terminal coupled to the reference capacitor, a second input terminal coupled to a reference voltage, and an output terminal coupled to the charge balancing circuit and the counter;

the charge balance circuit is coupled with the reference capacitor and is suitable for charging or discharging the reference capacitor when the conductive object is sensed;

the counter is adapted to count based on the first logic level or the second logic level of the comparator output and obtain a count value.

2. The capacitive sensing device of claim 1, wherein a first terminal of the capacitive sensor is coupled to ground and a first terminal of the reference capacitance is coupled to ground, the switch bank comprising a first switch and a second switch, wherein the first switch is coupled between a second terminal of the capacitive sensor and the first predetermined voltage and the second switch is coupled between the second terminal of the capacitive sensor and the second terminal of the reference capacitance.

3. The capacitive sensing apparatus of claim 1, wherein either of the first logic level and the second logic level is a high level or a low level.

4. The capacitive sensing device of claim 1, wherein the charge balancing circuit is adapted to charge or discharge the reference capacitance to maintain the voltage of the reference capacitance near the reference voltage.

5. The capacitive sensing device of claim 1, wherein the first predetermined voltage is low and the charge balancing circuit is adapted to charge the reference capacitance when sensing the conductive object, or the first predetermined voltage is high and the charge balancing circuit is adapted to discharge the reference capacitance when sensing the conductive object.

6. The capacitive sensing device of claim 5, wherein the charge balancing circuit comprises a first power source, a second power source, a first control switch and a second control switch, the first power source and the second power source being coupled to the reference capacitor through the first control switch and the second control switch, respectively, and an output of the comparator being coupled to the first control switch and the second control switch to be selectively closed and opened, thereby alternately charging or discharging the reference capacitor through the first power source and the second power source.

7. The capacitive sensing device as claimed in claim 6, wherein the first power source and the second power source are respectively coupled to a high level to alternately charge the reference capacitor when the first predetermined voltage is a low level, and the first power source and the second power source are both coupled to a low level to alternately discharge the reference capacitor when the first predetermined voltage is a high level.

8. The capacitive sensing apparatus of claim 6, wherein the first and second power sources are first and second current sources, respectively.

9. The capacitive sensing apparatus of claim 6, wherein the first and second power sources are first and second voltage sources, respectively.

10. The capacitive sensing device of claim 9, wherein the charge balancing circuit further comprises a first resistor and a second resistor, the first voltage source coupled to the first control switch through the first resistor, the second voltage source coupled to the second control switch through the second resistor.

11. The capacitive sensing device of claim 9, wherein the first control switch comprises a first and gate and a third switch, the second control switch comprises a second and gate and a fourth switch, the first input of the first and gate and the first input of the second and gate are both coupled to the output of the comparator, the second input of the first and gate and the second input of the second and gate are both coupled to a clock signal, the third switch is coupled between the output of the first and gate and the second end of the reference capacitor, and the fourth switch is coupled between the output of the second and gate and the second end of the reference capacitor.

12. The capacitive sensing device of claim 11, wherein the charge balancing circuit further comprises a first capacitor and a second capacitor, a first terminal of the first capacitor is coupled to the third switch, a second terminal of the first capacitor is coupled to ground, and a first terminal of the second capacitor is coupled to the fourth switch, and a second terminal of the second capacitor is coupled to ground.

13. The capacitive sensing apparatus of claim 6, wherein the first and second power sources are a third current source and a third voltage source, respectively.

14. The capacitive sensing device of claim 13, wherein the charge balancing circuit further comprises a third resistor, the third voltage source coupled to the second control switch through the third resistor.

15. The capacitive sensing device of any one of claims 1 to 14, comprising a timing unit through which the outputs of the comparator are coupled to a charge balancing circuit and a counter, respectively.

16. The capacitive sensing device of any one of claims 1 to 14, comprising a timer coupled to the counter and adapted to determine a sensing period and to output a timing signal to the counter, the counter being adapted to count over the sensing period based on the first or second logic level and the timing signal to obtain a final count value.

17. The capacitive sensing device of claim 16, comprising a control unit coupled to the timer and adapted to output an enable signal or a disable signal to the timer and to receive the timing signal.

18. A method of sensing capacitance, comprising:

a, alternately coupling a capacitive sensor to a first predetermined voltage and a reference capacitance;

b, comparing the voltage of the reference capacitor with a reference voltage to output a first logic level or a second logic level;

and c, counting the counter based on the first logic level or the second logic level to obtain a counting value and charging or discharging the reference capacitor.

19. The method of claim 18, wherein step c comprises charging or discharging a reference capacitor based on the first logic level or the second logic level to maintain a voltage of the reference capacitor near the reference voltage.

20. The method of claim 18, wherein steps a, b and c are performed cyclically within a sensing period determined by a timer and a final count value is obtained.

21. A method according to any one of claims 18 to 20, wherein the first predetermined voltage is low and step a comprises adjusting the voltage of the reference capacitance by charging the capacitive sensor with the reference capacitance.

22. The method of claim 21, comprising adjusting a voltage of the reference capacitance by charging the capacitive sensor with the reference capacitance and charging the reference capacitance with a charge balancing circuit.

23. The method of claim 22, wherein the charge balancing circuit comprises a first power supply and a second power supply that alternately charge the reference capacitance based on the first logic level and the second logic level, respectively.

24. A method according to any one of claims 18 to 20, wherein the first predetermined voltage is high and step a comprises adjusting the voltage of the reference capacitance by charging the reference capacitance with the capacitive sensor.

25. The method of claim 24, comprising adjusting a voltage of the reference capacitance by charging the reference capacitance with the capacitive sensor and discharging the reference capacitance with a charge balancing circuit.

26. The method of claim 25, wherein the charge balancing circuit comprises a first power supply and a second power supply that alternately discharge the reference capacitance based on the first logic level and the second logic level, respectively.

Technical Field

The present invention relates to the field of proximity sensing, and more particularly, to a capacitive sensing apparatus and a method for sensing capacitance.

Background

Capacitive sensing devices are increasingly used in electronic devices such as personal computers, multimedia players, game consoles, consumer electronics, and mobile communication devices.

Taking as an example the existing patent document entitled "capacitive proximity detection using delta/sigma conversion" (patent publication No. CN105379120B, hereinafter referred to as "first patent document"), this patent document describes a specific implementation of capacitive proximity detection. However, this solution has three disadvantages. The first disadvantage is that, in the whole capacitance sensing process, the charging circuit selectively charges and discharges the holding capacitor according to the output result of the comparator, which is equivalent to increasing the capacitance value of the capacitance sensor, thereby being not beneficial to improving the sensing sensitivity; the second disadvantage is that the switch coupled to the capacitive sensor is controlled by the output signal of the comparator, which in principle complicates the formula for measuring the final count value of the capacitance value of the capacitive sensor, and is not conducive to the automatic adjustment of the sensing sensitivity in practical applications; a third disadvantage is that the improvement of the sensing sensitivity is based on an increase of the measurement time period, which increases the power consumption of the sensing process.

Existing capacitive sensing devices need to be improved in terms of power consumption and sensing sensitivity.

Disclosure of Invention

The technical problem solved by the invention is that the existing capacitive sensing equipment needs to be improved in the aspects of power consumption, sensing sensitivity and the like.

To solve the above technical problem, an embodiment of the present invention provides a capacitive sensing apparatus, including: a capacitive sensor adapted to sense a conductive object proximate thereto; a switch bank adapted to alternately couple the capacitive sensor to a first predetermined voltage and a reference capacitance; a reference capacitance adapted to share charge with the capacitive sensor when sensing a conductive object; the comparator is provided with a first input end, a second input end and an output end, wherein the first input end is coupled with the reference capacitor, the second input end is coupled with the reference voltage, and the output end is coupled with the charge balance circuit and the counter; a charge balance circuit coupled to the reference capacitor and adapted to charge or discharge the reference capacitor when sensing the conductive object; a counter adapted to count based on the first logic level or the second logic level of the comparator output and obtain a count value.

Optionally, the first terminal of the capacitive sensor is grounded, the first terminal of the reference capacitor is grounded, and the switch set includes a first switch and a second switch, wherein the first switch is coupled between the second terminal of the capacitive sensor and the first predetermined voltage, and the second switch is coupled between the second terminal of the capacitive sensor and the second terminal of the reference capacitor.

Optionally, either one of the first logic level and the second logic level is a high level or a low level.

Optionally, the charge balancing circuit is adapted to charge or discharge the reference capacitance to maintain the voltage of the reference capacitance near the reference voltage.

Optionally, the first predetermined voltage is low and the charge balancing circuit is adapted to charge the reference capacitance when sensing the conductive object, or the first predetermined voltage is high and the charge balancing circuit is adapted to discharge the reference capacitance when sensing the conductive object.

Optionally, the charge balancing circuit includes a first power supply, a second power supply, a first control switch and a second control switch, the first power supply and the second power supply are coupled to the reference capacitor through the first control switch and the second control switch, respectively, and the output terminal of the comparator is coupled to the first control switch and the second control switch to be selectively closed and opened, so that the reference capacitor is alternately charged or discharged by the first power supply and the second power supply.

Optionally, the first power source and the second power source are respectively coupled to a high level to alternately charge the reference capacitor when the first predetermined voltage is a low level, and both the first power source and the second power source are coupled to a low level to alternately discharge the reference capacitor when the first predetermined voltage is a high level.

Optionally, the first power supply and the second power supply are a first current source and a second current source, respectively.

Optionally, the first power supply and the second power supply are a first voltage source and a second voltage source, respectively.

Optionally, the charge balancing circuit further includes a first resistor and a second resistor, the first voltage source is coupled to the first control switch through the first resistor, and the second voltage source is coupled to the second control switch through the second resistor.

Optionally, the first control switch includes a first and gate and a third switch, the second control switch includes a second and gate and a fourth switch, a first input terminal of the first and gate and a first input terminal of the second and gate are both coupled to the output terminal of the comparator, a second input terminal of the first and gate and a second input terminal of the second and gate are both coupled to the clock signal, the third switch is coupled between the output terminal of the first and gate and the second terminal of the reference capacitor, and the fourth switch is coupled between the output terminal of the second and gate and the second terminal of the reference capacitor.

Optionally, the charge balance circuit further includes a first capacitor and a second capacitor, a first end of the first capacitor is coupled to the third switch, a second end of the first capacitor is coupled to the ground, and a first end of the second capacitor is coupled to the fourth switch, and a second end of the second capacitor is coupled to the ground.

Optionally, the first power supply and the second power supply are a third current source and a third voltage source, respectively.

Optionally, the charge balancing circuit further comprises a third resistor, and the third voltage source is coupled to the second control switch through the third resistor.

Optionally, the capacitive sensing apparatus includes a timing unit, and the output terminal of the comparator is respectively coupled to the charge balancing circuit and the counter through the timing unit.

Optionally, the capacitive sensing device comprises a timer coupled to the counter and adapted to determine a sensing period and output a timing signal to the counter, and the counter is adapted to count within the sensing period based on the first logic level or the second logic level and the timing signal to obtain a final count value.

Optionally, the capacitive sensing device comprises a control unit coupled to the timer, adapted to output an enable signal or a disable signal to the timer, and to receive a timing signal.

The embodiment of the invention also provides a method for sensing the capacitance, which comprises the following steps: a, alternately coupling a capacitive sensor to a first predetermined voltage and a reference capacitance; b, comparing the voltage of the reference capacitor with the reference voltage to output a first logic level or a second logic level; and c, counting the counter based on the first logic level or the second logic level to obtain a counting value and charging or discharging the reference capacitor.

Optionally, step c includes charging or discharging the reference capacitance based on the first logic level or the second logic level to maintain the voltage of the reference capacitance near the reference voltage.

Optionally, steps a, b and c are performed cyclically within a sensing period determined by a timer, and a final count value is obtained.

Optionally, the first predetermined voltage is low level, and step a includes adjusting the voltage of the reference capacitance by charging the capacitive sensor through the reference capacitance.

Optionally, adjusting the voltage of the reference capacitance by charging the capacitive sensor with the reference capacitance and charging the reference capacitance with a charge balancing circuit is included.

Optionally, the charge balancing circuit comprises a first power supply and a second power supply, the first power supply and the second power supply alternately charging the reference capacitance based on the first logic level and the second logic level, respectively.

Optionally, the first predetermined voltage is high level, and step a includes adjusting the voltage of the reference capacitor by charging the reference capacitor through the capacitive sensor.

Optionally, the voltage of the reference capacitance is adjusted by charging the reference capacitance with the capacitive sensor and discharging the reference capacitance with the charge balancing circuit.

Optionally, the charge balancing circuit comprises a first power supply and a second power supply, the first power supply and the second power supply alternately discharging the reference capacitance based on the first logic level and the second logic level, respectively.

Compared with the prior art, the technical scheme of the embodiment of the invention has the beneficial effect. For example, in the whole capacitance sensing process, for the capacitance sensing device having a specific circuit structure in each embodiment of the present invention, the charge balancing circuit continuously charges or discharges the reference capacitance according to the output result of the comparator, instead of selectively charging or discharging the reference capacitance, thereby facilitating the improvement of the sensing sensitivity; the switch group in the embodiment of the invention is not controlled by the logic level output by the comparator, so that the relational expression for measuring the count value of the capacitance value of the capacitive sensor is relatively simple, and the automatic adjustment of the sensing sensitivity in practical application is facilitated, thereby avoiding the increase of power consumption caused by the increase of the sensing period.

Drawings

FIG. 1 is a schematic diagram of an overall structure of a capacitive sensing apparatus according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a capacitive sensing apparatus according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a capacitive sensing apparatus according to a first embodiment of the present invention;

FIG. 4 is a schematic structural diagram of a capacitive sensing apparatus according to a second embodiment of the present invention;

FIG. 5 is a schematic structural diagram of a capacitive sensing apparatus according to a third embodiment of the present invention;

FIG. 6 is a schematic structural diagram of a capacitive sensing apparatus according to a fourth embodiment of the present invention;

FIG. 7 is a schematic structural diagram of a capacitive sensing apparatus according to a fifth embodiment of the present invention;

FIG. 8 is a schematic structural diagram of a capacitive sensing apparatus according to a sixth embodiment of the present invention;

FIG. 9 is a schematic structural diagram of a capacitive sensing apparatus according to a seventh embodiment of the present invention;

FIG. 10 is a schematic structural diagram of a capacitive sensing apparatus according to an eighth embodiment of the present invention;

FIG. 11 is a flow chart of a method of sensing capacitance according to an embodiment of the invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 1 is a schematic general structural diagram of a capacitive sensing device according to an embodiment of the present invention, and fig. 2 is a schematic specific structural diagram of the capacitive sensing device according to the embodiment of the present invention.

As shown in fig. 1, the capacitive sensing device 100 includes a capacitive sensor 101, a switch bank 102, a reference capacitance 103, a comparator 104, a charge balancing circuit 105, and a counter 106.

The capacitive sensing device 100 may be provided in an electronic device to sense a user's operation as part of a user interface.

The capacitive sensor 101 may be arranged at a specific area of the capacitive sensing device 100, which is adapted to sense a conductive object (such as a human finger) in proximity thereto. Whether a conductive object is in proximity may be determined by circuitry within the capacitive sensing apparatus 100 sensing a change in a capacitance value of the capacitive sensor 101, where the capacitance value of the capacitive sensor 101 to be sensed is labeled C in fig. 1-10_X。

In one embodiment, the first terminal of capacitive sensor 101 is grounded.

The switch bank 102 is adapted to alternately couple the capacitive sensor 101 to a first predetermined voltage 107 and a reference capacitance 103 (labeled C in fig. 1 to 10)_R) Wherein the reference capacitance 103 is adapted to share charge with the capacitive sensor 101 when sensing a conductive object.

In one embodiment, the first terminal of the reference capacitor 103 is grounded.

The switch block 102 may have a first terminal, a second terminal, and a third terminal. A first terminal of the switch set 102 may be coupled to the second terminal of the capacitive sensor 101, a second terminal of the switch set 102 may be coupled to a first predetermined voltage 107, and a third terminal of the switch set 102 may be coupled to a second terminal of the reference capacitor 103.

The switch set 102 may perform a first operation, that is, a first terminal of the switch set is coupled to the second terminal of the capacitive sensor 101, a second terminal of the switch set is coupled to a first predetermined voltage 107, and a third terminal of the switch set is decoupled from the second terminal of the reference capacitor 103, so that the capacitive sensor 101 is coupled to the first predetermined voltage 107 and decoupled from the reference capacitor 103; the switch set 102 further performs a second operation, i.e. couples the first terminal thereof to the second terminal of the capacitive sensor 101, decouples the second terminal thereof from the first predetermined voltage 107, and couples the third terminal thereof to the second terminal of the reference capacitor 103, so that the capacitive sensor 101 is coupled to the reference capacitor 103 and decouples from the first predetermined voltage 107. The switch set 102 may alternately perform the first operation and the second operation, thereby alternately coupling the capacitive sensor 101 to the first predetermined voltage 107 and the reference capacitance 103.

In one embodiment, the switch set 102 has a fourth terminal coupled to the clock 123; the switch set 102 receives a control signal from the clock 123 to alternately perform the first operation and the second operation, thereby alternately coupling the capacitive sensor 101 to the first predetermined voltage 107 and the reference capacitance 103.

In another embodiment, the switch set 102 includes a first switch 113 (labeled in fig. 2-10)) And a second switch 114 (labeled in fig. 2-10)) The first switch 113 is coupled between the second terminal of the capacitive sensor 101 and the first predetermined voltage 107, and the second switch 114 is coupled between the second terminal of the capacitive sensor 101 and the second terminal of the reference capacitor 103. The first switch 113 and the second switch 114 may operate in a two-phase non-overlapping phase, which forms a switched capacitor circuit with the capacitive sensor 101.

The first predetermined voltage 107 may be low, such as ground; or may be high, such as an operating voltage (V) of the capacitive sensing device 100_DD)。

The reference capacitance 103 is adapted to share charge with the capacitive sensor 101 when sensing a conductive object. "share charge" means that if the first predetermined voltage 107 is at a low level, the reference capacitance 103 charges the capacitive sensor 101 when the switch group 102 performs the second operation (while the first predetermined voltage 107 discharges the capacitive sensor 101 when the switch group 102 performs the first operation); if the first predetermined voltage 107 is at a high level, the reference capacitance 103 discharges the capacitive sensor 101 when the switch group 102 performs the second operation (while the first predetermined voltage 107 charges the capacitive sensor 101 when the switch group 102 performs the first operation).

In embodiments of the present invention, "charged" means that one element receives charge (positive and/or negative charge) transferred from another element, and "discharged" means that one element releases charge (positive and/or negative charge) to another element; "one element charges another element" means that another element receives charge (positive and/or negative charge) transferred from one element, and "one element discharges another element" means that another element discharges charge (positive and/or negative charge) to one element.

In a specific implementation, if the first predetermined voltage 107 is low, the charge balancing circuit 105 is adapted to charge the reference capacitance 103 when sensing a conductive object; the charge balancing circuit 105 is adapted to discharge the reference capacitance 103 when sensing a conductive object if the first predetermined voltage is high level.

The capacitance value of the reference capacitor 103 may be larger than that of the capacitive sensor 101, so that the voltage of the reference capacitor 103 caused by the coupling between the capacitive sensor 101 and the reference capacitor 103 does not change greatly when the switch group 102 performs the second operation.

The comparator 104 has a first input terminal 108, a second input terminal 109 and an output terminal 110, wherein the first input terminal 108 is coupled to the reference capacitor 103, and the second input terminal 109 is coupled to a reference voltage 111 (labeled as V in fig. 1 to 10)_REF) The output terminal 110 is coupled to the charge balance circuit 105 and the counter 106.

In one embodiment, a first terminal of the reference capacitor 103 is coupled to ground, and a second terminal of the reference capacitor 103 is coupled to the first input terminal 108 of the comparator 104.

Comparator 104 may compare the voltage of reference capacitor 103 to reference voltage 111. For example, when the voltage value of the reference capacitor 103 is lower than the voltage value of the reference voltage 111, the output terminal 110 of the comparator 104 outputs a first logic level; when the voltage value of the reference capacitor 103 is higher than the voltage value of the reference voltage 111, the output terminal 110 of the comparator 104 outputs a second logic level; the first logic level is high and the second logic level is low, or the first logic level is low and the second logic level is high.

The charge balance circuit 105 is coupled to the reference capacitor 103 and adapted to charge or discharge the reference capacitor 103 when sensing a conductive object, wherein "charging the reference capacitor 103 by the charge balance circuit 105" indicates that the reference capacitor 103 receives the charge transferred by the charge balance circuit 105, and "discharging the reference capacitor 103 by the charge balance circuit 105" indicates that the reference capacitor 103 discharges the charge to the charge balance circuit 105.

In one embodiment, a first terminal of the reference capacitor 103 is coupled to ground, and a second terminal of the reference capacitor 103 is coupled to the charge balance circuit 105.

In another embodiment, the charge balancing circuit 105 is adapted to charge or discharge the reference capacitor 103 to maintain the voltage value of the reference capacitor 103 near the voltage value of the reference voltage 111, e.g., to maintain the voltage value of the reference capacitor 103 between 70% and 130% of the voltage value of the reference voltage 111.

In a specific implementation, the charge balancing circuit 105 includes a first power supply 119, a second power supply 120, a first control switch 121 and a second control switch 122, the first power supply 119 and the second power supply 120 are coupled to the reference capacitor 103 (the second end of the reference capacitor 103 as shown in fig. 2) through the first control switch 121 and the second control switch 122, respectively, and the output 110 of the comparator 104 is coupled to the first control switch 121 and the second control switch 122 to be selectively closed and opened, so that the reference capacitor 103 is alternately charged by the first power supply 119 and the second power supply 120, or the reference capacitor 103 is alternately discharged by the first power supply 119 and the second power supply 120.

For example, when the output terminal 110 of the comparator 104 outputs the first logic level, the first control switch 121 is closed and the second control switch 122 is opened, so that only the first power supply 119 charges or discharges the reference capacitor 103; when the output terminal 110 of the comparator 104 outputs the second logic level, the first control switch 121 is opened and the second control switch 122 is closed, so that only the second power supply 119 charges or discharges the reference capacitor 103.

For another example, when the output terminal 110 of the comparator 104 outputs the first logic level, the first control switch 121 is opened and the second control switch 122 is closed, so that only the second power supply 119 charges or discharges the reference capacitor 103; when the output terminal 110 of the comparator 104 outputs the second logic level, the first control switch 121 is closed and the second control switch 122 is opened, so that only the first power supply 119 charges or discharges the reference capacitor 103.

In a specific implementation, the first power source 119 and the second power source 120 are respectively coupled to a second predetermined voltage (labeled as V in fig. 2)₁And (V) and a third predetermined voltage (labeled V in fig. 2)₂). If the first predetermined voltage 107 is low, the second predetermined voltage and the third predetermined voltage are both high to alternately charge the reference capacitor 103; if the first predetermined voltage 107 is high, the second predetermined voltage and the third predetermined voltage are both low (e.g., both coupled to ground) to alternately discharge the reference capacitor 103.

In the embodiment of the present invention, the first power source 119 and the second power source 120 are used to provide a certain current or a certain voltage, and thus, any one of the first power source 119 and the second power source 120 may be a current source or a voltage source; when the above-mentioned "determined current" or "determined voltage" is zero, the first power source 119 or the second power source 120 may be considered as "ground" or the first power source 119 or the second power source 120 may be considered as coupled to "ground".

The counter 106 is coupled to the output terminal 110 of the comparator 104 and is adapted to count based on the logic level output by the comparator 104 to obtain a count value.

For example, when the counter 106 receives the first logic level through its enable terminal, the count value of the counter 106 performs an accumulation count operation (e.g., the first logic level is received once, and the count value is incremented by one); when the counter 106 receives the second logic level through its enable terminal, the count value of the counter 106 is maintained.

For another example, when the counter 106 receives the first logic level through its enable terminal, the count value of the counter 106 is maintained; when the counter 106 receives the second logic level through its enable terminal, the count value of the counter 106 performs an accumulation count operation (e.g., the second logic level is received once, and the count value is incremented by one).

The count value (e.g., the final count value obtained during one sensing cycle) may be output via the output 112 of the counter 106.

The capacitive sensing device 100 may include a filter coupled to the output 112 of the counter 106 to filter the count value output by the counter 106.

The capacitive sensing device 100 may include a timing unit 115, and the output 110 of the comparator 104 is coupled to the charge balancing circuit 105 and the counter 106 through the timing unit 115, respectively. As shown in fig. 2 to 10, an input terminal of the timing unit 115 is coupled to the output terminal 110 of the comparator 104, an output terminal thereof is coupled to the charge balancing circuit 105 and the counter 106, respectively, and the first logic level or the second logic level output by the comparator 104 is synchronized by the timing unit 115 and then provided to the charge balancing circuit 105 and the counter 106, respectively, so that the charge balancing circuit 105 can charge or discharge the reference capacitor 103 in a precise period and the counter 106 can count accurately.

The capacitive sensing device 100 may include a timer 116 coupled to the counter 106 to output a timing signal thereto; the timer 116 is adapted to determine a sensing period during which the counter 106 counts. Specifically, the output 110 of the comparator 104 (which may pass through the timing unit 115) and the output of the timer 116 are respectively coupled to two inputs of the and gate 117, and the output of the and gate 117 is coupled to the enable terminal of the counter 106, so that the counter 106 simultaneously counts within the sensing period based on the first logic level output by the comparator 104 and the timing signal output by the timer 116, and a final count value may be obtained at the end of the sensing period.

The capacitive sensing device 100 may comprise a control unit 118 coupled to the timer 116 to output an enable signal or a disable signal to the latter and to receive a timing signal output by the latter. Specifically, an input terminal of the control unit 118 is coupled to an output terminal of the timer 116 to receive the timing signal outputted by the latter; an output terminal of the control unit 118 is coupled to an enable terminal of the timer 116 to output an enable signal or a disable signal to the latter, wherein the enable signal is a signal for enabling the timer 116, and the disable signal is a signal for disabling the timer 116. The control unit 118 controls the start and end of the sensing process by controlling the enabling or disabling of the timer 116.

The final count value obtained during a sensing period or the final digital value obtained by filtering can be used to measure the capacitance value of the capacitive sensor 101.

The following description is given in conjunction with specific embodiments.

Fig. 3 is a schematic structural diagram of a capacitive sensing apparatus according to a first embodiment of the invention.

As shown in fig. 3, the first predetermined voltage is low (ground); in the charge balance circuit 105, the first power source and the second power source are a current source 201 (labeled as I1 in fig. 3) and a current source 202 (labeled as I2 in fig. 3), respectively, and the current source 201 is coupled to a predetermined voltage (labeled as V in fig. 3)_DD1) The current source 202 is coupled to a predetermined voltage (labeled as V in FIG. 3)_DD2) The first control switch and the second control switch are a switch 203 and a switch 204, respectively.

When the capacitive sensing apparatus 200 senses a capacitance value of the capacitive sensor 101, the switch 113 and the switch 114 constitute a switch group to alternately perform the first operation and the second operation, thereby alternately coupling the capacitive sensor 101 to the first predetermined voltage and the reference capacitance 103. Wherein, when the first operation is performed, the first predetermined voltage discharges the capacitive sensor 101; when the second operation is performed, the reference capacitance 103 charges the capacitive sensor 101.

When the output terminal 110 of the comparator 104 outputs one of the first logic level and the second logic level, the switch 203 is closed and the switch 204 is opened, so that the current source 201 charges the reference capacitor 103; when the output 110 of the comparator 104 outputs the other of the first logic level and the second logic level, the switch 203 is opened and the switch 204 is closed, so that the current source 202 charges the reference capacitor 103.

Fig. 4 is a schematic structural diagram of a capacitive sensing apparatus according to a second embodiment of the present invention.

As shown in FIG. 4, the first predetermined voltage is high (the operating voltage V)_DD) (ii) a In the charge balance circuit 105, the first power supply and the second power supply are a current source 301 and a current source 302, respectively, the current source 301 (labeled as I3 in fig. 4) and the current source 302 (labeled as I4 in fig. 4) are both coupled to ground, and the first control switch and the second control switch are a switch 303 and a switch 304, respectively.

When the capacitive sensing apparatus 300 senses a capacitance value of the capacitive sensor 101, the switch 113 and the switch 114 constitute a switch group to alternately perform the first operation and the second operation, thereby alternately coupling the capacitive sensor 101 to the first predetermined voltage and the reference capacitance 103. Wherein, when the first operation is performed, the first predetermined voltage charges the capacitive sensor 101; when the second operation is performed, the reference capacitance 103 discharges the capacitive sensor 101.

When the output terminal 110 of the comparator 104 outputs one of the first logic level and the second logic level, the switch 303 is closed and the switch 304 is opened, so that the current source 301 discharges the reference capacitance 103; when the output 110 of the comparator 104 outputs the other of the first logic level and the second logic level, the switch 303 is opened and the switch 304 is closed, so that the current source 302 discharges the reference capacitance 103.

The first and second embodiments shown in fig. 3 and 4 involve two current sources. In the first embodiment, the final count value C1 obtained in one sensing period is used to measure the capacitance value of the capacitive sensor 101, which can be calculated by the following formula (1), and the sensitivity of sensing S1 can be calculated by the following formula (2); in the second embodiment, the final count value C2 obtained in one sensing period is used to measure the capacitance value of the capacitive sensor 101, which can be calculated by the following formula (3), and the sensitivity of sensing S2 can be calculated by the following formula (4):

where N is the number of bits of the timer 116, V_REFIs the voltage value of the reference voltage 111, F is the frequency of the switch set 102, C_XCapacitance value to be sensed, I, of capacitive sensor 101₁And I₂First and second power supplies (which are current sources in the first and second embodiments), respectively, and VDD is an operating voltage.

As can be seen from equations (1) and (3), the final count values C1 and C2 are both related to the capacitance value C to be sensed_XIs in direct proportion; as can be seen from equations (2) and (4), the sensitivities S1 and S2 can be adjusted by adjusting I, respectively₁And I₂And the like.

The first and second embodiments have at least four technical advantages compared to the first patent document.

First, a charging circuit in the first patent document selectively charges and discharges a holding capacitor in accordance with an output result of a comparator; in contrast, the first and second embodiments of the present invention facilitate the improvement of the sensing sensitivity by charging or discharging only the reference capacitance 103 through the charge balance circuit 105.

Second, the switch coupled to the capacitive sensor in the first patent document is controlled by the output signal of the comparator, so that the formula for measuring the final count value of the capacitance of the capacitive sensor becomes complicated, in contrast; the switch group coupled with the capacitive sensor in the first and second embodiments of the present invention is not controlled by the output signal of the comparator, so that the formulas for measuring the final count value of the capacitance value of the capacitive sensor are relatively simple, as shown in formulas (1) and (3).

Third, the improvement of sensitivity in the first patent document is based on an increase in the measurement time period, which increases the power consumption of the sensing process; in contrast, in the first and second embodiments of the present invention, as shown in equations (2) and (4), the number of bits of the timer may not be adjusted (i.e., the sensing period is not increased), but the sensitivity may be improved by flexibly adjusting the voltage value of the reference voltage, the frequency of the switching group, and the current value of the current source while avoiding the increased power consumption due to the increase of the sensing period.

Fourth, in comparison with the first patent document, under the condition of the same sensing period, in the first and second embodiments of the present invention, as shown in equations (2) and (4), it is possible to adjust the currents I of the first power supply and the second power supply₁And I₂Etc. to further improve the sensitivity so that a more minute change in the capacitance value of the capacitive sensor can be sensed.

In the first and second embodiments of the present invention, as shown in equations (2) and (4), it is possible to flexibly adjust the current values of two current sources, which is not only higher in sensitivity but also free from overflow, as compared to providing only one current source for adjustment.

Specifically, in the scheme of adjusting one current source, the capacitive sensing device uses only one current source to charge or discharge the reference capacitance, and the other circuit structure is the same as that of the first or second embodiment, so that the first scheme and the second scheme can be formed respectively. In the first scheme, the final count value C3 obtained in one sensing period may be calculated by the following formula (5), and the sensitivity of sensing S3 may be calculated by the following formula (6); in the second scheme, the final count value C4 obtained in one sensing period may be calculated by the following formula (7), and the sensitivity of sensing S4 may be calculated by the following formula (8):

wherein N is the number of bits of the timer, V_REFIs the voltage value of the reference voltage, F is the frequency of the switch group, C_XCapacitance value to be sensed of a capacitive sensor, I₁Is the current of the current source.

The first and second embodiments each have at least two technical advantages over schemes one and two, respectively.

First, for schemes one and two, if the current I is measured₁Adjusted to X, the calculated sensitivity S2 is denoted a; for examples one and two, the current I is measured₁And I₂Adjusted to X and 0.5X, respectively, the calculated sensitivity S1 was 2A. It can be seen that in examples one and two, the sensitivity is improved.

Second, for schemes one and two, if at current I₁When X is obtained, the output value accounts for 70%, and the current I is measured₁When the output value ratio is adjusted to 0.5X, the output value ratio is more than 1 (70% by 2 — 140%), and overflow is generated; for examples one and two, at current I₁Is X and I₂At 0.5X, the output ratio was less than 1 (70% × 2-1 ═ 40%), and no overflow occurred.

Fig. 5 is a schematic structural diagram of a capacitive sensing apparatus according to a third embodiment of the present invention.

As shown in fig. 5, the first predetermined voltage is low (ground); in the charge balance circuit 105, the first power source and the second power source are voltage sources 401 (marked as V in fig. 5)_DD3) And a voltage source 402 (labeled V in FIG. 5)_DD4) The first control switch and the second control switch are a switch 403 and a switch 404, respectively.

In a third embodiment, the charge balancing circuit 105 may include a resistor 405 (labeled as R in FIG. 5)₁) And a resistor 406 (labeled R in FIG. 5)₂) Voltage source 401 is coupled to switch 403 through resistor 405, and voltage source 402 is coupled to switch 404 through resistor 406.

The sensing sensitivity can be adjusted by adjusting the resistance of the resistor 405 and/or the resistor 406.

When the capacitive sensing apparatus 400 senses a capacitance value of the capacitive sensor 101, the switch 113 and the switch 114 constitute a switch group to alternately perform the first operation and the second operation, thereby alternately coupling the capacitive sensor 101 to the first predetermined voltage and the reference capacitance 103. Wherein, when the first operation is performed, the first predetermined voltage discharges the capacitive sensor 101; when the second operation is performed, the reference capacitance 103 charges the capacitive sensor 101.

When the output 110 of the comparator 104 outputs one of the first logic level and the second logic level, the switch 403 is closed and the switch 404 is open, so that the voltage source 401 charges the reference capacitance 103; when the output 110 of the comparator 104 outputs the other of the first logic level and the second logic level, the switch 403 is open and the switch 404 is closed, so that the voltage source 402 charges the reference capacitance 103.

Fig. 6 is a schematic structural diagram of a capacitive sensing apparatus according to a fourth embodiment of the present invention.

As shown in FIG. 6, the first predetermined voltage is high (the operating voltage V)_DD) (ii) a In the charge balance circuit 105, the first power source and the second power source are respectively a voltage source (not shown) coupled to ground, and the first control switch and the second control switch are respectively a switch 503 and a switch 504.

In a fourth embodiment, charge balancing circuit 105 may include a resistor 501 (labeled as R in FIG. 6)₃) And a resistor 502 (labeled R in FIG. 6)₄) The voltage source is coupled to the switch 503 through the resistor 501, and the voltage source is coupled to the switch 504 through the resistor 502.

The sensing sensitivity can be adjusted by adjusting the resistance of the resistor 501 and/or the resistor 502.

When the capacitive sensing apparatus 500 senses a capacitance value of the capacitive sensor 101, the switch 113 and the switch 114 constitute a switch group to alternately perform the first operation and the second operation, thereby alternately coupling the capacitive sensor 101 to the first predetermined voltage and the reference capacitance 103. Wherein, when the first operation is performed, the first predetermined voltage charges the capacitive sensor 101; when the second operation is performed, the reference capacitance 103 discharges the capacitive sensor 101.

When the output 110 of the comparator 104 outputs one of the first logic level and the second logic level, the switch 503 is closed and the switch 504 is open, so that the first power supply discharges the reference capacitance 103; when the output 110 of the comparator 104 outputs the other of the first logic level and the second logic level, the switch 303 is opened and the switch 304 is closed, so that the second power supply discharges the reference capacitance 103.

The third and fourth embodiments shown in fig. 5 and 6 involve two voltage sources. In the third embodiment, I in formulas (1) and (2)₁And I₂Are respectively replaced by (V)_A-V_REF)/R_AAnd (V)_B-V_REF)/R_BTo obtain the formulas (9) and (10), wherein V_AAnd V_BVoltages of two voltage sources, R_AAnd R_BThe final count value C5 and the sensitivity S5 obtained in one sensing period, which are resistances coupled to two voltage sources, respectively, can be calculated based on equations (9) and (10), respectively. In the fourth embodiment, I in formulas (3) and (4)₁And I₂Are respectively replaced by V_REF/R_AAnd V_REF/R_BTo give formulae (11) and (12), wherein R_AAnd R_BThe final count value C6 and the sensitivity S6 obtained in one sensing period, which are resistances coupled to the ground, respectively, can be calculated based on equations (11) and (12), respectively.

Like the first and second embodiments, the third and fourth embodiments have at least four technical advantages as compared with the first patent document.

In the scheme of adjusting one voltage source, the capacitive sensing device only charges or discharges the reference capacitance by using one voltage source, and other circuit structures are the same as the third or fourth embodiment, so that the scheme three and the scheme four can be formed respectively.

Like the first and second embodiments, the third and fourth embodiments have at least two technical advantages over schemes three and four, respectively.

Fig. 7 is a schematic structural diagram of a capacitive sensing apparatus according to a fifth embodiment of the present invention.

As shown in fig. 7, the first predetermined voltage is low (ground); in the charge balance circuit 105, the first power supply and the second power supply are voltage sources 601 (labeled as V in fig. 7)_DD5) And a voltage source 602 (labeled V in FIG. 7)_DD6) The first control switch comprises an and gate 603 and a switch 605, and the second control switch comprises an and gate 604 and a switch 606, wherein the switch 605 and the switch 606 are both a switch group consisting of two sub-switches, and both of the two sub-switches in the switch 605 and both of the two sub-switches in the switch 606 operate in two non-overlapping phases.

A first input of the and gate 603 and a first input of the and gate 604 are both coupled to the output 110 of the comparator 104, a second input of the and gate 603 is coupled to a first clock signal (which is used to control the switching frequency of the switch 605), and a second input of the and gate 604 is coupled to a second clock signal (which is used to control the switching frequency of the switch 606); a switch 605 is coupled between the output of the and gate 603 and the second terminal of the reference capacitor 103, and a switch 606 is coupled between the output of the and gate 604 and the second terminal of the reference capacitor 103.

In the fifth embodiment, the charge balance circuit 105 may include a capacitor 607 (labeled as C in fig. 7)_D1) And a capacitor 608 (labeled C in FIG. 7)_D2) The first terminal of the capacitor 607 is coupled to ground, the second terminal is coupled to the switch 605 so as to be selectively coupled to the reference capacitor 103 by the closing or opening of the switch 605, and the first terminal of the capacitor 608 is coupled to ground, the second terminal is coupled to the switch 606 so as to be selectively coupled to the reference capacitor 103 by the closing or opening of the switch 606.

When the capacitive sensing device 600 senses the capacitance value of the capacitive sensor 101, the capacitor 607 and the switch 605 form an equivalent resistance, and the capacitor 608 and the switch 606 form an equivalent resistance, thereby controllably charging the reference capacitor 103. The sensing sensitivity can be adjusted by adjusting the capacitance values of the capacitor 607 and the capacitor 608 and the switching frequency of the switch 605 and the switch 606.

When the capacitive sensing apparatus 600 senses a capacitance value of the capacitive sensor 101, the switch 113 and the switch 114 alternately provide an output level to perform the first operation and the second operation, respectively, so that the capacitive sensor 101 is alternately coupled to the first predetermined voltage and the reference capacitance 103. Wherein, when the first operation is performed, the first predetermined voltage discharges the capacitive sensor 101; when the second operation is performed, the reference capacitance 103 charges the capacitive sensor 101.

When the output terminal 110 of the comparator 104 outputs one of the first logic level and the second logic level, the and gate 603 has an output and the and gate 604 has no output, so that the voltage source 601 charges the capacitor 607 in the first phase and the capacitor 607 charges the reference capacitor 103 in the second phase, wherein the operations in the first phase and the second phase are performed alternately; when the output 110 of the comparator 104 outputs the other of the first logic level and the second logic level, the and gate 603 has no output and the and gate 604 has an output, such that the voltage source 602 charges the capacitor 608 in the first phase and the capacitor 608 charges the reference capacitor 103 in the second phase, wherein the operations in the first phase and the second phase are performed alternately.

Fig. 8 is a schematic structural diagram of a capacitive sensing apparatus according to a sixth embodiment of the present invention.

As shown in FIG. 8, the first predetermined voltage is high (is the operating voltage V)_DD) (ii) a In the charge balance circuit 105, the first power supply and the second power supply are respectively a voltage source (not shown) both coupled to ground, the first control switch includes an and gate 701 and a switch 703, and the second control switch includes an and gate 702 and a switch 704, wherein the switch 703 and the switch 704 are both a switch group composed of two sub-switches, and both of the two sub-switches in the switch 703 and both of the two sub-switches in the switch 704 operate in two-phase non-overlapping phases.

A first input of the and gate 701 and a first input of the and gate 702 are both coupled to the output 110 of the comparator 104, a second input of the and gate 701 is coupled to the third clock signal (which is used to control the switching frequency of the switch 703), and a second input of the and gate 702 is coupled to the fourth clock signal (which is used to control the switching frequency of the switch 704); switch 703 is coupled between the output of and gate 701 and the second terminal of reference capacitor 103, and switch 704 is coupled between the output of and gate 702 and the second terminal of reference capacitor 103.

In a sixth embodiment, the charge balancing circuit 105 may include a capacitor 705 (labeled as C in fig. 8)_D3) And a capacitor 706 (labeled C in FIG. 8)_D4) The first terminal of the capacitor 705 is coupled to the ground, the second terminal is coupled to the switch 703 so as to be selectively coupled to the reference capacitor 103 by closing or opening the switch 703, and the first terminal of the capacitor 706 is coupled to the ground, the second terminal is coupled to the switch 704 so as to be selectively coupled to the reference capacitor 103 by closing or opening the switch 704.

When the capacitive sensing device 700 senses a capacitance value of the capacitive sensor 101, the capacitance 705 and the switch 703 form an equivalent resistance, and the capacitance 706 and the switch 704 form an equivalent resistance, thereby controllably discharging the reference capacitance 103. The sensing sensitivity can be adjusted by adjusting the capacitance values of the capacitor 705 and the capacitor 706 and the switching frequency of the switch 703 and the switch 704.

When the capacitive sensing apparatus 700 senses a capacitance value of the capacitive sensor 101, the switch 113 and the switch 114 alternately provide an output level to perform the first operation and the second operation, respectively, so that the capacitive sensor 101 is alternately coupled to the first predetermined voltage and the reference capacitance 103. Wherein, when the first operation is performed, the first predetermined voltage charges the capacitive sensor 101; when the second operation is performed, the reference capacitance 103 discharges the capacitive sensor 101.

When the output 110 of the comparator 104 outputs one of the first logic level and the second logic level, the and gate 701 has an output and the and gate 702 has no output, so that ground discharges the capacitor 705 in the first phase and the capacitor 705 discharges the reference capacitor 103 in the second phase, wherein the operations in the first phase and the second phase are performed alternately; when the output 110 of the comparator 104 outputs the other of the first and second logic levels, the and gate 701 has no output and the and gate 702 has an output, such that ground discharges the capacitor 706 in the first phase and the capacitor 706 discharges the reference capacitor 103 in the second phase, wherein the operations in the first and second phases are performed alternately.

The fifth and sixth embodiments shown in fig. 7 and 8 involve two voltage sources. In a fifth embodiment, R in formulae (9) and (10) is_AAnd R_BAre respectively replaced by 1/F_AC_AAnd 1/F_BC_BTo obtain the formulas (13) and (14), wherein F_AAnd F_BFrequency, C, of two switch sets coupled to two voltage sources, respectively_AAnd C_BThe final count value C7 and the sensitivity S7 obtained in one sensing period can be calculated based on equations (13) and (14), respectively, for the capacitance values coupled to the two switch groups. In the sixth embodiment, R in formulae (11) and (12)_AAnd R_BAre respectively replaced by 1/F_AC_AAnd 1/F_BC_BTo obtain the formulas (15) and (16), wherein F_AAnd F_BFrequency, C, of two switch sets coupled to two voltage sources, respectively_AAnd C_BThe final count value C8 and the sensitivity S8 obtained in one sensing period may be calculated based on equations (15) and (16), respectively, for the capacitance values coupled to the two switch groups.

Like the first and second embodiments, the fifth and sixth embodiments have at least four technical advantages as compared with the first patent document.

In the scheme of adjusting one voltage source, the capacitive sensing device charges or discharges the reference capacitance by using only one voltage source, and other circuit structures are the same as the fifth or sixth embodiment, so that the scheme five and the scheme six can be formed respectively.

Like the first and second embodiments, the fifth and sixth embodiments have at least two technical advantages over schemes five and six.

Fig. 9 is a schematic structural diagram of a capacitive sensing apparatus according to a seventh embodiment of the present invention.

As shown in fig. 9, the first predetermined voltage is low (ground); in the charge balance circuit 105, the first power source and the second power source are a current source 801 (labeled as I5 in fig. 9) and a voltage source 802 (labeled as V in fig. 9), respectively_DD8) The current source 801 is coupled to a predetermined voltage (labeled as V in FIG. 9)_DD7) The first control switch and the second control switch are a switch 803 and a switch 804, respectively.

In the seventh embodiment, the charge balance circuit 105 may include a resistor 805 (labeled as R in fig. 9)₅) Voltage source 802 is coupled to switch 804 through resistor 805.

The sensing sensitivity can be adjusted by adjusting the resistance of the resistor 805 and the current of the current source 801.

When the capacitive sensing apparatus 800 senses a capacitance value of the capacitive sensor 101, the switch 113 and the switch 114 constitute a switch group to alternately perform the first operation and the second operation, thereby alternately coupling the capacitive sensor 101 to the first predetermined voltage and the reference capacitance 103. Wherein, when the first operation is performed, the first predetermined voltage discharges the capacitive sensor 101; when the second operation is performed, the reference capacitance 103 charges the capacitive sensor 101.

When the output 110 of the comparator 104 outputs one of the first logic level and the second logic level, the switch 803 is closed and the switch 804 is opened, so that the current source 801 charges the reference capacitance 103; when the output 110 of the comparator 104 outputs the other of the first logic level and the second logic level, the switch 803 is open and the switch 804 is closed, so that the voltage source 802 charges the reference capacitance 103.

Fig. 10 is a schematic structural diagram of a capacitive sensing apparatus according to an eighth embodiment of the present invention.

As shown in FIG. 10, the first predetermined voltage is high (is the operating voltage V)_DD) (ii) a In the charge balance circuit 105, the first power supply and the second power supply are a current source 901 (labeled as I6 in fig. 10) and a voltage source (not shown) which are both coupled to ground, and the first control switch and the second control switch are a switch 903 and a switch 904, respectively.

In the eighth embodiment, the charge balance circuit 105 may include a resistor 902 (labeled as R in fig. 10)₆) The voltage source is coupled to a switch 904 through a resistor 902.

The sensing sensitivity can be adjusted by adjusting the resistance of the resistor 902 and the current of the current source 901.

When the capacitive sensing apparatus 900 senses the capacitance value of the capacitive sensor 101, the switch 113 and the switch 114 constitute a switch group to alternately perform the first operation and the second operation, thereby alternately coupling the capacitive sensor 101 to the first predetermined voltage and the reference capacitance 103. Wherein, when the first operation is performed, the first predetermined voltage charges the capacitive sensor 101; when the second operation is performed, the reference capacitance 103 discharges the capacitive sensor 101.

When the output 110 of the comparator 104 outputs one of the first logic level and the second logic level, the switch 903 is closed and the switch 904 is open, so that the current source discharges the reference capacitance 103; when the output 110 of the comparator 104 outputs the other of the first logic level and the second logic level, the switch 903 is opened and the switch 904 is closed so that the voltage source discharges the reference capacitance 103.

The seventh and eighth embodiments shown in fig. 9 and 10 relate to one current source and one voltage source. In the seventh embodiment, I in formulas (1) and (2)₂Is replaced by (V)_C-V_REF)/R_CTo give formulae (17) and (18), in which V_CIs the voltage of a voltage source, R_CThe final count value C9 and the sensitivity S9 obtained in one sensing period may be calculated based on equations (17) and (18), respectively, for the resistance coupled to the voltage source. In the eighth embodiment, I in formulas (3) and (4)₂Is replaced by V_REF/R_CTo obtain the formulas (19) and (20), wherein R_CThe final count value C10 and the sensitivity S10 obtained in one sensing period may be calculated based on equations (19) and (20), respectively, for the resistance coupled to ground.

Like the first and second embodiments, the seventh and eighth embodiments have at least four technical advantages as compared with the first patent document.

In the scheme of only one voltage source or one current source for adjustment, the capacitive sensing device charges or discharges the reference capacitance using only one voltage source or one current source and the other circuit configuration is the same as that of the seventh or eighth embodiment, so that the scheme seventh and the scheme eighth may be formed, respectively.

Like the first and second embodiments, the seventh and eighth embodiments have at least two technical advantages over schemes seven and eight, respectively.

FIG. 11 is a flow chart of a method of sensing capacitance according to an embodiment of the invention. The method 1000 includes the steps of:

step S1010: alternately coupling a capacitive sensor to a first predetermined voltage and a reference capacitance;

step S1020: comparing the voltage of the reference capacitor with a reference voltage to output a first logic level or a second logic level;

step S1030: the counter is counted based on the first logic level or the second logic level to obtain a count value and to charge or discharge the reference capacitance.

In the execution of step S1010, as previously described, the first operation and the second operation may be alternately executed by the switch group 102 so that the capacitive sensor 101 is alternately coupled to the first predetermined voltage 107 and the reference capacitance 103.

In the execution of step S1020, the voltage of reference capacitor 103 may be compared to reference voltage 111 by comparator 104, as previously described. For example, when the voltage value of the reference capacitor 103 is lower than the voltage value of the reference voltage 111, the output terminal 110 of the comparator 104 outputs a first logic level; when the voltage value of the reference capacitor 103 is higher than the voltage value of the reference voltage 111, the output terminal 110 of the comparator 104 outputs a second logic level; the first logic level is high and the second logic level is low, or the first logic level is low and the second logic level is high.

In the execution of step S1030, as described earlier, the reference capacitor 103 may be charged or discharged by the charge balance circuit 105 to maintain the voltage of the reference capacitor 103 near the reference voltage 111. For example, the voltage value of reference capacitor 103 is maintained between 70% and 130% of the voltage value of reference voltage 111.

In a specific implementation, steps S1010, S1020, and S1030 are executed cyclically within a sensing period determined by a timer, and a final count value is obtained.

In a specific implementation, the first predetermined voltage is low, and step S1010 includes adjusting a voltage of the reference capacitor by charging the capacitive sensor through the reference capacitor.

In a specific implementation, the voltage of the reference capacitor is adjusted by charging the capacitive sensor with the reference capacitor and charging the reference capacitor with the charge balancing circuit.

In a particular implementation, a charge balancing circuit includes first and second power supplies that alternately charge a reference capacitance based on first and second logic levels, respectively.

In a specific implementation, the first predetermined voltage is high, and step S1010 includes adjusting the voltage of the reference capacitor by charging the reference capacitor through the capacitive sensor.

In a specific implementation, the voltage of the reference capacitor is adjusted by charging the reference capacitor with the capacitive sensor and discharging the reference capacitor with the charge balancing circuit.

In a particular implementation, a charge balancing circuit includes first and second power supplies that alternately discharge a reference capacitance based on first and second logic levels, respectively.

For specific principles, embodiments and the like of the method 1000 for sensing capacitance, reference may be made to the description related to the capacitive sensing device in conjunction with fig. 1 to 10, which is not repeated herein.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.