阅读说明：本技术 多比特并行校验方法及装置、存储介质及Turbo译码器 (Multi-bit parallel checking method and device, storage medium and Turbo decoder ) 是由 吴肖亮 于 2021-08-19 设计创作，主要内容包括：本发明公开了一种多比特并行校验方法及装置、存储介质及Turbo译码器,方法包括：在Turbo译码器的半迭代译码过程中,确定Turbo译码器中每个译码单元同时输出的硬判决比特；在每个译码单元同时输出硬判决比特时,根据每个译码单元同时输出的硬判决比特进行循环冗余校验。由此,通过在半迭代译码过程中的每个译码单元输出硬判决比特之后立即开始进行CRC校验,无需等待全部码块的硬判决比特输出之后才开始CRC校验,减少了因CRC校验带来的延迟,提高了Turbo译码器的利用率。(The invention discloses a multi-bit parallel check method and device, a storage medium and a Turbo decoder, wherein the method comprises the following steps: in the semi-iterative decoding process of the Turbo decoder, determining the hard decision bit output by each decoding unit in the Turbo decoder at the same time; and when each decoding unit simultaneously outputs the hard decision bit, performing cyclic redundancy check according to the hard decision bit simultaneously output by each decoding unit. Therefore, the CRC check is started immediately after each decoding unit outputs the hard decision bits in the semi-iterative decoding process, the CRC check is started without waiting for the hard decision bits of all code blocks to be output, the delay caused by the CRC check is reduced, and the utilization rate of the Turbo decoder is improved.)

1. A multi-bit parallel check method is applied to a Turbo decoder, and comprises the following steps:

determining hard decision bits output by each decoding unit in the Turbo decoder at the same time in the semi-iterative decoding process of the Turbo decoder;

and when each decoding unit simultaneously outputs the hard decision bit, performing cyclic redundancy check according to the hard decision bit simultaneously output by each decoding unit.

2. The multi-bit parallel check method according to claim 1, wherein performing a cyclic redundancy check according to the hard decision bits simultaneously output by each decoding unit comprises:

comparing the hard decision bit output by each decoding unit at the same time with the hard decision bit output correspondingly in the last semi-iterative decoding process to obtain an updated hard decision bit corresponding to each decoding unit;

determining a lookup table corresponding to each decoding unit according to the updated hard decision bit corresponding to each decoding unit and the offset address corresponding to each hard decision bit;

and performing operation according to the lookup table corresponding to each decoding unit and a predetermined calculation parameter to obtain a check result.

3. The multi-bit parallel verification method according to claim 2, wherein when the hard decision bits output by each decoding unit at the same time are compared with the corresponding hard decision bits output in the last half-iterative decoding process, the same bits are set to 0 to obtain the updated hard decision bits corresponding to each decoding unit.

4. The multi-bit parallel verification method according to claim 2, wherein determining the lookup table corresponding to each decoding unit according to the updated hard decision bit corresponding to each decoding unit and the offset address corresponding to each hard decision bit comprises:

aiming at each decoding unit, determining a first lookup table according to the offset address corresponding to each hard decision bit;

establishing a relation table between the hard decision bit of each decoding unit and an output lookup table according to the first lookup table;

and determining a lookup table corresponding to each decoding unit according to the updated hard decision bit corresponding to each decoding unit and the relation table.

5. The multi-bit parallel check method of claim 4, wherein determining, for each decoding unit, the first lookup table according to the offset address corresponding to each hard decision bit comprises:

performing modular operation on the offset address corresponding to each decoding unit to obtain a first modular operation result;

dividing the first modulus operation result into a plurality of phases, wherein the number of the phases is the same as the number of offset addresses corresponding to each decoding unit;

and reading out the lookup table of each phase according to the offset address corresponding to each hard decision bit.

6. A multi-bit parallel verification method according to claim 2, wherein said calculation parameters are determined according to the following formula:

F(i)＝f(P-1-i)，

wherein f (i) is the calculation parameter, i is greater than or equal to 0 and less than or equal to P-1, P is the number of decoding units, f (0) is a predetermined base value, and f (1) is x^Mmod g (x), where f (i +1) ═ f (i) + f (1), x is an element on a finite field, M is a ratio between the length of a data block and the number of decoding units in the half-iterative decoding process, mod is a modulo operation, and g (x) is a cyclic redundancy check generator polynomial.

7. The multi-bit parallel verification method according to claim 2, wherein performing an operation according to the lookup table corresponding to each decoding unit and a predetermined calculation parameter to obtain a verification result comprises:

performing convolution operation on the lookup table corresponding to each decoding unit and the calculation parameter corresponding to each decoding unit to obtain a plurality of convolution operation results;

performing accumulation operation on the plurality of convolution operation results to obtain an accumulation operation result;

performing modulo-2 operation on the accumulated operation result to obtain a second modulo operation result;

and repeatedly executing M times, and performing modulo-2 operation on a second modulo operation result obtained by the M times to obtain the check result, wherein M is the ratio of the length of the data block to the number of the decoding units in the semi-iterative decoding process.

8. A computer-readable storage medium, having stored thereon a multi-bit parallel check program, which when executed by a processor implements the multi-bit parallel check method according to any one of claims 1 to 7.

9. A Turbo decoder comprising a memory, a processor and a multi-bit parallel check program stored in the memory and executable on the processor, wherein the processor implements the multi-bit parallel check method according to any one of claims 1 to 7 when executing the multi-bit parallel check program.

10. A multi-bit parallel parity check device, for use in a Turbo decoder, the device comprising:

the determining module is used for determining the hard decision bits output by each decoding unit in the Turbo decoder at the same time in the semi-iterative decoding process of the Turbo decoder;

and the check module is used for performing cyclic redundancy check according to the hard decision bits output by each decoding unit at the same time when each decoding unit outputs the hard decision bits at the same time.

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a multi-bit parallel calibration method and apparatus, a storage medium, and a Turbo decoder.

Background

Generally, after a downlink Turbo decoder in an LTE (Long Term Evolution) system decodes, each transport block performs Cyclic Redundancy Check (CRC) Check to determine whether to terminate the decoding of the Turbo decoder in advance, so as to save power consumption, and determine whether the decoding is correct to complete reporting.

In the related technology, the CRC check is started after each half-iteration decoding is completed, and the next half-iteration decoding is started after the CRC check result is obtained.

Disclosure of Invention

The present invention is directed to solving, at least to some extent, one of the technical problems in the related art. Therefore, a first objective of the present invention is to provide a multi-bit parallel check method, in which CRC check is performed immediately after each decoding unit outputs hard decision bits in a semi-iterative decoding process, and CRC check is performed without waiting for the hard decision bits of all code blocks to be output, so that delay caused by CRC check is reduced, and the utilization rate of a Turbo decoder is improved.

A second object of the invention is to propose a computer-readable storage medium.

The third purpose of the invention is to provide a Turbo decoder.

A fourth object of the present invention is to provide a multi-bit parallel parity checker.

In order to achieve the above object, an embodiment of a first aspect of the present invention provides a multi-bit parallel check method applied in a Turbo decoder, where the method includes: in the semi-iterative decoding process of the Turbo decoder, determining the hard decision bit output by each decoding unit in the Turbo decoder at the same time; and when each decoding unit simultaneously outputs the hard decision bit, performing cyclic redundancy check according to the hard decision bit simultaneously output by each decoding unit.

According to the multi-bit parallel check method provided by the embodiment of the invention, in the semi-iterative decoding process of the Turbo decoder, the hard decision bits output by each decoding unit in the Turbo decoder at the same time are determined, and when the hard decision bits are output by each decoding unit at the same time, cyclic redundancy check is carried out according to the hard decision bits output by each decoding unit at the same time. Therefore, the CRC check is started immediately after each decoding unit outputs the hard decision bits in the semi-iterative decoding process, the CRC check is started without waiting for the hard decision bits of all code blocks to be output, the delay caused by the CRC check is reduced, and the utilization rate of the Turbo decoder is improved.

According to an embodiment of the present invention, performing cyclic redundancy check according to the hard decision bits simultaneously output by each decoding unit includes: comparing the hard decision bit output by each decoding unit at the same time with the hard decision bit output correspondingly in the last semi-iterative decoding process to obtain the updated hard decision bit corresponding to each decoding unit; determining a lookup table corresponding to each decoding unit according to the updated hard decision bit corresponding to each decoding unit and the offset address corresponding to each hard decision bit; and performing operation according to the lookup table corresponding to each decoding unit and the predetermined calculation parameters to obtain a check result.

According to an embodiment of the present invention, when the hard decision bit output by each decoding unit at the same time is compared with the corresponding hard decision bit output in the last half-iterative decoding process, the same bit is set to 0, so as to obtain the updated hard decision bit corresponding to each decoding unit.

According to an embodiment of the present invention, determining a lookup table corresponding to each decoding unit according to the updated hard decision bit corresponding to each decoding unit and the offset address corresponding to each hard decision bit includes: aiming at each decoding unit, determining a first lookup table according to the offset address corresponding to each hard decision bit; establishing a relation table between the hard decision bit of each decoding unit and an output lookup table according to the first lookup table; and determining a lookup table corresponding to each decoding unit according to the updated hard decision bit corresponding to each decoding unit and the relation table.

According to an embodiment of the present invention, for each decoding unit, determining a first lookup table according to an offset address corresponding to each hard decision bit includes: performing modular operation on the offset address corresponding to each decoding unit to obtain a first modular operation result; dividing the first modulus operation result into a plurality of phases, wherein the number of the phases is the same as the number of the offset addresses corresponding to each decoding unit; and reading out the lookup table of each phase according to the offset address corresponding to each hard decision bit.

According to one embodiment of the invention, the calculation parameters are determined according to the following formula:

F(i)＝f(P-1-i)，

wherein f (i) is the calculation parameter, i is greater than or equal to 0 and less than or equal to P-1, P is the number of decoding units, f (0) is a predetermined base value, and f (1) is x^Mmod g (x), where f (i +1) ═ f (i) + f (1), x is an element on a finite field, M is a ratio between the length of a data block and the number of decoding units in a half-iterative decoding process, mod is a modulo operation, and g (x) is a cyclic redundancy check generator polynomial.

According to an embodiment of the present invention, performing an operation according to a lookup table corresponding to each decoding unit and a predetermined calculation parameter to obtain a check result includes: performing convolution operation on the lookup table corresponding to each decoding unit and the calculation parameters corresponding to each decoding unit to obtain a plurality of convolution operation results; performing accumulation operation on the convolution operation results to obtain an accumulation operation result; performing modulo-2 operation on the accumulated operation result to obtain a second modulo operation result; and repeatedly executing M times, and performing modulo-2 operation on a second modulo operation result obtained by the M times to obtain a check result, wherein M is the ratio of the length of the data block to the number of the decoding units in the semi-iterative decoding process.

To achieve the above object, a second embodiment of the present invention provides a computer-readable storage medium, on which a multi-bit parallel check program is stored, and the multi-bit parallel check program, when executed by a processor, implements the multi-bit parallel check method as described above.

According to the computer-readable storage medium of the embodiment of the invention, by the multi-bit parallel check method, the CRC check is started immediately after each decoding unit outputs the hard decision bit in the semi-iterative decoding process, and the CRC check is started without waiting for the hard decision bits of all code blocks to be output, so that the delay caused by the CRC check is reduced, and the utilization rate of the Turbo decoder is improved.

In order to achieve the above object, a third embodiment of the present invention provides a Turbo decoder, which includes a memory, a processor, and a multi-bit parallel check program stored in the memory and executable on the processor, where the multi-bit parallel check program is executed by the processor to implement the multi-bit parallel check method.

According to the Turbo decoder provided by the embodiment of the invention, through the multi-bit parallel check method, the CRC check is started immediately after each decoding unit outputs the hard decision bit in the semi-iterative decoding process, and the CRC check is started without waiting for the hard decision bits of all code blocks to be output, so that the delay caused by the CRC check is reduced, and the utilization rate of the Turbo decoder is improved.

In order to achieve the above object, a fourth aspect of the present invention provides a multi-bit parallel parity check device, which is applied in a Turbo decoder, and includes: the determining module is used for determining the hard decision bits output by each decoding unit in the Turbo decoder at the same time in the semi-iterative decoding process of the Turbo decoder; and the check module is used for performing cyclic redundancy check according to the hard decision bits output by each decoding unit at the same time when each decoding unit outputs the hard decision bits at the same time.

According to the multi-bit parallel check device provided by the embodiment of the invention, the hard decision bits output by each decoding unit in the Turbo decoder at the same time are determined in the semi-iterative decoding process of the Turbo decoder through the determination module, and when the hard decision bits are output by each decoding unit at the same time through the check module, cyclic redundancy check is carried out according to the hard decision bits output by each decoding unit at the same time. Therefore, the CRC check is started immediately after each decoding unit outputs the hard decision bits in the semi-iterative decoding process, the CRC check is started without waiting for the hard decision bits of all code blocks to be output, the delay caused by the CRC check is reduced, and the utilization rate of the Turbo decoder is improved.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

FIG. 1a is a schematic flow chart of a CRC check in the related art;

FIG. 1b is a flowchart illustrating a check process after improving the parallelism of CRC calculation in the related art;

FIG. 2 is a diagram illustrating a structure of CRC check after improving the parallelism of CRC calculation in the related art;

FIG. 3 is a flow chart illustrating a multi-bit parallel checking method according to an embodiment of the present invention;

FIG. 4 is a flow chart of a multi-bit parallel check method according to one embodiment of the invention;

FIG. 5 is a flow chart of a multi-bit parallel check method according to another embodiment of the present invention;

FIG. 6 is a diagram illustrating an internal structure of a lookup table according to an embodiment of the invention;

FIG. 7 is a schematic diagram of the generation of calculation parameters according to one embodiment of the present invention;

FIG. 8 is a block diagram illustrating a multi-bit parallel verification method according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of a multi-bit parallel parity check apparatus according to an embodiment of the present invention.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.

After a downlink Turbo decoder in an LTE system decodes, each transmission block carries out CRC to judge whether to terminate the Turbo decoder decoding in advance so as to save power consumption and judge whether the decoding is correct so as to finish reporting, so that a CRC check result of the semi-iterative decoding needs to be known after each semi-iterative decoding of the Turbo decoder.

In the related art, the CRC check processing flow is shown in fig. 1 a: the Turbo decoder starts CRC check after completing the semi-iterative decoding each time, and starts the next semi-iterative decoding after obtaining the CRC check result, and the Turbo decoder is in a waiting state in the time period of the CRC check, so that the decoding time of the Turbo decoder is prolonged, and the utilization rate of the Turbo decoder is low. In order to reduce the time taken for the CRC check and achieve the result shown in fig. 1b, it is currently mainly achieved by improving the parallelism of the CRC check. Specifically, referring to fig. 2, during CRC check, hard decision bit data obtained by a Turbo decoder is first divided into a plurality of segments, such as P segments, and stored in P transport blocks, and CRC check is performed on each transport block to obtain a CRC check result of each transport block, and then the CRC check results of each transport block are concatenated through dot-product and xor operations by using parameters stored in a memory to obtain a CRC check result of the entire block of data. In order to reduce the time occupied by the CRC check, the parallelism of the CRC check is generally increased by increasing the number of transport blocks or the bit width (e.g., 32 bits or 64 bits) of the CRC parallel check.

Although the two modes can reduce the time occupied by CRC to a certain extent and further reduce the decoding time of the Turbo decoder, the independent CRC time is still needed, and the utilization rate of the Turbo decoder is still not high; meanwhile, the increase of the number of transmission blocks can cause the depth of the hard decision bit memory to be reduced, the increase of the CRC parallel check bit width can cause the width of the hard decision bit memory to be increased, the area of the hard decision bit memory can be increased in both modes, and the realization difficulty is increased; meanwhile, the increase of the parallelism of CRC check requires the increase of computing resources, which results in large CRC area overhead.

In view of the above technical problems, the present application provides a multi-bit parallel check method and apparatus, a storage medium, and a Turbo decoder, where CRC check is set in a semi-iterative decoding process of the Turbo decoder, specifically, when a decoding unit of the Turbo decoder starts to output hard decision bits, as shown in fig. 3, after each semi-iterative decoding is completed, CRC check of a whole code block is also completed simultaneously, and a CRC check result is obtained, and a next semi-iterative decoding is started immediately after hard decision, and the Turbo decoder is always in a working state, so that a utilization rate of the Turbo decoder is greatly improved.

The following describes in detail a multi-bit parallel check method and apparatus, a storage medium, and a Turbo decoder provided in the present application.

Fig. 4 is a flowchart of a multi-bit parallel check method according to an embodiment of the present invention, taking the method as an example for a Turbo decoder, and referring to fig. 4, the multi-bit parallel check method may include the following steps:

step S100, in the semi-iterative decoding process of the Turbo decoder, determining the hard decision bits output by each decoding unit in the Turbo decoder at the same time.

For example, first, the length of a data block to be decoded is defined as K, the maximum value of K in the LTE system is 6144, and assuming that the Turbo decoder has P decoding units, and the data length decoded by each decoding unit is M, then M × P ═ K, and each decoding unit simultaneously outputs at least one hard decision bit. In the semi-iterative decoding process of the Turbo decoder, whether each decoding unit outputs hard decision bits at the same time is judged, and if yes, the hard decision bits output by each decoding unit are obtained.

And step S200, when each decoding unit outputs the hard decision bit at the same time, performing cyclic redundancy check according to the hard decision bit output by each decoding unit at the same time.

Specifically, in the process of semi-iterative decoding, if each decoding unit outputs the hard decision bit at the same time, the CRC check is immediately started according to the hard decision bit output by each decoding unit at the same time, instead of starting the CRC check after waiting for the hard decision bits of all code blocks to be output, so that after each semi-iterative decoding is finished, the CRC check of the whole code block is synchronously finished, and then the next semi-iterative decoding is performed, thereby saving the time occupied by the CRC check alone.

In the embodiment, in the semi-iterative decoding process of the Turbo decoder, the CRC check is immediately performed after each decoding unit of the Turbo decoder simultaneously outputs the hard decision bits, instead of starting the CRC check after the hard decision bits of all code blocks are output, that is, after the semi-iterative decoding is finished, so that the delay caused by the CRC check is eliminated, and the utilization rate of the Turbo decoder is greatly improved.

Further, in some embodiments, referring to fig. 5, performing CRC check according to the hard decision bits output by each decoding unit at the same time includes:

step S201, comparing the hard decision bits output by each decoding unit at the same time with the hard decision bits output correspondingly in the previous half-iterative decoding process, and obtaining an updated hard decision bit corresponding to each decoding unit.

Specifically, during CRC check, the hard decision bits output by each decoding unit at the same time may be compared with the corresponding hard decision bits output in the last semi-iterative decoding process to obtain new hard decision bits, that is, updated hard decision bits. It should be noted that the half-iteration decoding includes multiple half-iteration loops, where the last half-iteration decoding specifically refers to the last half-iteration loop, for example, the odd half-iteration decoding shown in fig. 3 includes multiple half-iteration loops, and when CRC checks are performed, the hard decision bits output by each decoding unit in the current half-iteration loop at the same time are compared with the hard decision bits output by each decoding unit in the last half-iteration loop, so as to obtain new hard decision bits.

Optionally, when the hard decision bit output by each decoding unit at the same time is compared with the hard decision bit output correspondingly in the last half-iterative decoding process, the same bit is set to be 0, so as to obtain the updated hard decision bit corresponding to each decoding unit. For example, assuming that each decoding unit simultaneously outputs 4 hard decision bits, taking one of the decoding units as an example, the 4 hard decision bits output during the current half-iteration decoding are { a1, a2, A3, a4}, the 4 hard decision bits output during the last half-iteration decoding are { a11, a21, a31, a41}, if a1 is the same as a11, the bit is set to 0, otherwise, the bit remains unchanged; if A2 is the same as A21, then set the bit to 0, otherwise remain unchanged; and analogizing in sequence, finally obtaining the updated hard decision bits such as {0, A2, 0, A4 }. Other decoding units and the decoding unit have the same processing mode, and are not described herein again. Therefore, when the hard decision bit output in a certain cycle of the current iteration is the same as the hard decision bit output at the same bit position of the previous iteration, the hard decision bit is set to be 0, the CRC calculation of the corresponding bit in the cycle can be omitted, and the power consumption of the CRC can be effectively reduced when the Turbo decoder is close to convergence.

Step S202, determining a lookup table corresponding to each decoding unit according to the updated hard decision bit corresponding to each decoding unit and the offset address corresponding to each hard decision bit.

It should be noted that each hard decision bit has an offset address, and still taking 4 hard decision bits as an example, the offset addresses corresponding to the 4 hard decision bits can be represented as { oa3, oa2, oa1, oa0}, and the offset addresses corresponding to each hard decision bit are in the range of [0, M-1], where M is the data length decoded by the corresponding decoding unit. Optionally, the offset addresses corresponding to the hard decision bits at the same position of all the decoding units are the same, that is, the offset addresses corresponding to the 4 hard decision bits of each decoding unit in all the decoding units may be { oa3, oa2, oa1, oa0 }.

Assuming that 4 updated hard decision bits corresponding to each decoding unit are { b3, b2, b1, b0}, and the offset addresses corresponding to the 4 hard decision bits are { oa3, oa2, oa1, oa0}, the lookup table corresponding to each decoding unit can be determined according to the 4 updated hard decision bits { b3, b2, b1, b0} corresponding to each decoding unit and the offset addresses { oa3, oa2, oa1, oa0} corresponding to the 4 hard decision bits. It should be noted that the Look-Up Table (LUT) is essentially a RAM, and after data is written into the RAM (random Access Memory) in advance, each time a signal is input, it is equal to inputting an address to perform the Look-Up, and finding out and outputting the content corresponding to the address.

Optionally, in some embodiments, determining the lookup table corresponding to each decoding unit according to the updated hard decision bit corresponding to each decoding unit and the offset address corresponding to each hard decision bit includes: aiming at each decoding unit, determining a first lookup table according to the offset address corresponding to each hard decision bit; establishing a relation table between the hard decision bit of each decoding unit and an output lookup table according to the first lookup table; and determining a lookup table corresponding to each decoding unit according to the updated hard decision bit corresponding to each decoding unit and the relation table.

Specifically, when determining the lookup table corresponding to each decoding unit, taking one of the decoding units as an example, the first lookup table may be determined according to the offset address { oa3, oa2, oa1, oa0} corresponding to 4 hard decision bits to obtain 4 first lookup tables { lut3, lut2, lut1, lut0}, then the relationship table between the hard decision bits { b3, b2, b1, b0} of the decoding unit and the output lookup table l (i) is established according to the 4 first lookup tables { lut3, lut2, lut1, lut0}, that is, the relationship between the two is determined according to the 4 first lookup tables { lut3, lut2, lut1, lut0}, and finally the lookup table l (i) corresponding to the decoding unit is determined according to the updated hard decision bits { b3, b2, b1, b0} and the relationship table.

Optionally, in some embodiments, determining, for each decoding unit, a first lookup table according to the offset address corresponding to each hard decision bit includes: performing modular operation on the offset address corresponding to each decoding unit to obtain a first modular operation result; dividing the first modulus operation result into a plurality of phases, wherein the number of the phases is the same as the number of the offset addresses corresponding to each decoding unit; and reading out the lookup table of each phase according to the offset address corresponding to each hard decision bit.

Specifically, the look-up table has an overall depth of K/P, and when K is 6144, the overall depth is 6144/P, the width can be 24 bits, and x is stored internallyⁱmod g (x), where x is an element in a finite field, i is greater than or equal to 0 and less than or equal to M-1, M is the data length decoded by each decoding unit, and mod represents a modulo operation, where x is takenⁱThe remainder of the division by g (x), g (x) is the generator polynomial for the CRC check. The lookup table may be divided into a plurality of phases according to a first modulo operation result obtained by performing a modulo operation on an offset address corresponding to the decoding unit, for example, performing a modulo 4 operation (for example, modulo 4 addition) on offset addresses { oa3, oa2, oa1, oa0} corresponding to 4 hard decision bits to obtain a first modulo operation result, then dividing the first modulo operation result into 4 phases as { phase3, phase2, phase1, phase0}, which has a specific structure as shown in fig. 6, and finally obtaining an offset address { oa3, oa2, oa1, oa0 corresponding to 4 hard decision bitsRead out the look-up tables for each phase, resulting in 4 first look-up tables lut3, lut2, lut1, lut 0. It should be noted that, since the offset addresses { oa3, oa2, oa1, oa0} corresponding to the 4 hard decision bits output by the decoding unit just satisfy 4 different phase conditions, there is no problem of address collision when reading the lookup table.

Further, after obtaining the 4 first lookup tables, a relationship table between the hard decision bits { b3, b2, b1, b0} of the decoding unit and the output lookup table l (i) may be established according to the 4 first lookup tables { lut3, lut2, lut1, lut0}, as shown in table 1:

TABLE 1

In the context of table 1, the following,representing an exclusive or operation.

And finally, determining the corresponding lookup table L (i) of the decoding unit according to the hard decision bits { b3, b2, b1, b0} of the decoding unit and the relation table. For example, when the hard decision bits { b3, b2, b1, b0} are {0000}, the corresponding lookup table l (i) is 0x 000000; for another example, when the hard decision bits { b3, b2, b1, b0} are {0111}, the corresponding lookup table L (i) is

Step S203, performing an operation according to the lookup table corresponding to each decoding unit and a predetermined calculation parameter to obtain a check result.

Specifically, after the lookup table l (i) corresponding to each decoding unit is obtained in the foregoing manner, an operation is performed according to the lookup table l (i) corresponding to each decoding unit and a predetermined calculation parameter f (i), and finally a CRC check result is obtained. It should be noted that each translation isThe code unit corresponds to a calculation parameter f (i). Optionally, the generation process of the calculation parameter f (i) is as shown in fig. 7, and f (i) ═ f (P-1-i) is satisfied, where i ≦ 0 ≦ P-1, P is the number of decoding units, f (0) ═ predetermined base value, for example, f (0) ≦ 0x800000, f (1) ═ x^Mmod g (x), where f (i +1) ═ f (i) + f (1), x is an element on a finite field, M is a ratio between the length of a data block and the number of decoding units in a semi-iterative decoding process, that is, the length of data decoded by the decoding units, and mod is a modulo operation, where x is taken as the expressionⁱThe remainder of the division by g (x), g (x) is the generator polynomial for the cyclic redundancy check.

In fig. 7, convolution operation means convolves two 24-bit inputs to obtain 47-bit data, and modulo operation means convolves the input 47 bits by mod g (x) to obtain 24-bit data.

Optionally, in some embodiments, performing an operation according to the lookup table corresponding to each decoding unit and a predetermined calculation parameter to obtain a check result includes: performing convolution operation on the lookup table corresponding to each decoding unit and the calculation parameters corresponding to each decoding unit to obtain a plurality of convolution operation results; performing accumulation operation on the convolution operation results to obtain an accumulation operation result; performing modulo-2 operation on the accumulated operation result to obtain a second modulo operation result; and repeatedly executing M times, and performing modulo-2 operation on a second modulo operation result obtained by the M times to obtain a check result, wherein M is the ratio of the length of the data block to the number of the decoding units in the semi-iterative decoding process.

Specifically, after a lookup table l (i) corresponding to each decoding unit is obtained, convolution operation is performed on the lookup table l (i) corresponding to each decoding unit and corresponding calculation parameters f (i) to obtain P convolution operation results, then accumulation calculation (i.e., summation) is performed on the P convolution operation results to obtain an accumulation operation result, modulo-2 operation (e.g., modulo-2 sum) is performed on the accumulation operation result to obtain a second modulo operation result, M times (i.e., K/P) are repeated, and finally modulo-2 operation (e.g., modulo-2 sum) is performed on the M times of obtained second modulo operation results to obtain a CRC check result.

As a specific example, referring to fig. 8, the multi-bit parallel check may include the following processes:

take the length K of the data block 6144 and the number P of decoding units 16 as an example. The 16 calculation parameters f (i), f (i) ═ f (15-i), where i is greater than or equal to 0 and less than or equal to 15, can be generated in advance according to the calculation parameter generation method corresponding to fig. 7, and the calculation result is:

f(0)＝0x800000；

f(1)＝x^Mmod g (x), where M ═ K/P;

f(2)＝f(1)+f(1)mod 2；

f(3)＝f(2)+f(1)mod 2；

f(i+1)＝f(i)+f(1)mod 2；

f(15)＝f(14)+f(1)mod 2。

in the semi-iterative decoding process of the Turbo decoder, when 16 decoding units output hard decision bits simultaneously, CRC check is started immediately. During CRC, each decoding unit outputs 4 hard decision bits to a comparison unit, the comparison unit compares the 4 hard decision bits output by each decoding unit with the hard decision bits at the same position output by the last half iteration, the hard decision bits at the same bits are set to 0, the updated 4 hard decision bits { b3, b2, b1, b0} are obtained, offset addresses { oa3, oa2, oa1, oa0} corresponding to the 4 hard decision bits are output, and the offset addresses corresponding to the 4 hard decision bits are subjected to modulo 4 operation and stored in 4 phases. Then, the lookup table unit searches the corresponding first lookup table according to the offset addresses { oa3, oa2, oa1, oa0} corresponding to the 4 hard decision bits to obtain 4 first lookup tables { lut3, lut2, lut1, lut0}, and selects the corresponding lookup table L (i) according to the 4 hard decision bits { b3, b2, b1, b0} corresponding to each decoding unit, wherein i is greater than or equal to 0 and less than or equal to 15. And then, the convolution operation unit performs convolution calculation on the lookup table L (i) corresponding to each decoding unit and the corresponding calculation parameters F (i) to obtain 16 convolution results, accumulates the 16 convolution results through the accumulation unit to obtain an accumulation operation result, and performs modulo-2 operation on the accumulation operation result through the modulo operation unit to obtain a CRC (cyclic redundancy check) result. Repeating K/P times, and accumulating the result to obtain the CRC result of the whole code block by modulo 2 operation.

Therefore, in the semi-iterative decoding process of the Turbo decoder, after the decoding unit outputs the hard decision bits at the same time, the CRC check is immediately started, instead of starting after all the code block hard decision bits are output, so that the delay caused by the CRC check in the related technology is reduced, the utilization rate of the Turbo decoder is improved, and the hard decision bit memory is easier to manage, namely the lookup table unit in FIG. 8 is easier to manage, the problem of depth and width change caused by parallelism is solved, if the number of the decoding units is not changed, the corresponding depth is not changed, the corresponding bits can be 24, and the width is not changed.

It should be noted that the convolution operation unit and the modulo operation unit in fig. 8 may be shared with the convolution operation unit and the modulo operation unit shown in fig. 7, that is, they may be multiplexed in different calculation processes, so that the calculation resources may be saved and the utilization rate may be improved.

In summary, the CRC check is performed immediately after each decoding unit outputs the hard decision bits in the semi-iterative decoding process, and the CRC check is performed after all the decoding units output the hard decision bits without waiting, so that the delay caused by the CRC check is reduced, and the utilization rate of the Turbo decoder is improved. In addition, the hard decision bit buffer is easier to manage, and the problem that the depth and the width of the buffer are changed due to parallelism is solved.

In some embodiments, embodiments of the present invention also provide a computer-readable storage medium on which a multi-bit parallel check program is stored, the multi-bit parallel check program implementing the multi-bit parallel check method as described above when executed by a processor.

According to the computer-readable storage medium of the embodiment of the invention, by the multi-bit parallel check method, the CRC check is started immediately after each decoding unit outputs the hard decision bit in the semi-iterative decoding process, and the CRC check is started without waiting for the hard decision bits of all code blocks to be output, so that the delay caused by the CRC check is reduced, and the utilization rate of the Turbo decoder is improved.

In some embodiments, an embodiment of the present invention further provides a Turbo decoder, which includes a memory, a processor, and a multi-bit parallel check program stored in the memory and executable on the processor, where the multi-bit parallel check program is executed by the processor to implement the multi-bit parallel check method.

According to the Turbo decoder provided by the embodiment of the invention, through the multi-bit parallel check method, the CRC check is started immediately after each decoding unit outputs the hard decision bit in the semi-iterative decoding process, and the CRC check is started without waiting for the hard decision bits of all code blocks to be output, so that the delay caused by the CRC check is reduced, and the utilization rate of the Turbo decoder is improved.

Fig. 9 is a schematic structural diagram of a multi-bit parallel parity check device according to an embodiment of the present invention, and taking the application of the device to a Turbo decoder as an example, referring to fig. 9, the multi-bit parallel parity check device 90 includes: a determination module 91 and a verification module 92.

The determining module 91 is configured to determine, in a semi-iterative decoding process of the Turbo decoder, a hard decision bit that is output by each decoding unit in the Turbo decoder at the same time. The check module 92 is configured to perform cyclic redundancy check according to the hard decision bits output by each decoding unit at the same time when each decoding unit outputs the hard decision bits at the same time.

In some embodiments, the verification module 92 is specifically configured to: comparing the hard decision bit output by each decoding unit at the same time with the hard decision bit output correspondingly in the last semi-iterative decoding process to obtain the updated hard decision bit corresponding to each decoding unit; determining a lookup table corresponding to each decoding unit according to the updated hard decision bit corresponding to each decoding unit and the offset address corresponding to each hard decision bit; and performing operation according to the lookup table corresponding to each decoding unit and the predetermined calculation parameters to obtain a check result.

In some embodiments, the verification module 92 is specifically configured to: when the hard decision bit output by each decoding unit at the same time is compared with the hard decision bit output correspondingly in the last semi-iterative decoding process, the same bit is set to be 0, so as to obtain the updated hard decision bit corresponding to each decoding unit.

In some embodiments, the verification module 92 is specifically configured to: aiming at each decoding unit, determining a first lookup table according to the offset address corresponding to each hard decision bit; establishing a relation table between the hard decision bit of each decoding unit and an output lookup table according to the first lookup table; and determining a lookup table corresponding to each decoding unit according to the updated hard decision bit corresponding to each decoding unit and the relation table.

In some embodiments, the verification module 92 is specifically configured to: performing modular operation on the offset address corresponding to each decoding unit to obtain a first modular operation result; dividing the first modulus operation result into a plurality of phases, wherein the number of the phases is the same as the number of the offset addresses corresponding to each decoding unit; and reading out the lookup table of each phase according to the offset address corresponding to each hard decision bit.

In some embodiments, the verification module 92 is specifically configured to determine the calculation parameters according to the following formula:

F(i)＝f(P-1-i)，

where f (i) is a calculation parameter, i is 0 ≦ P-1, P is the number of decoding units, f (0) is a predetermined base value, and f (1) is x^Mmod g (x), where f (i +1) ═ f (i) + f (1), x is an element on a finite field, M is a ratio between the length of a data block and the number of decoding units in a half-iterative decoding process, mod is a modulo operation, and g (x) is a cyclic redundancy check generator polynomial.

In some embodiments, the verification module 92 is specifically configured to: performing convolution operation on the lookup table corresponding to each decoding unit and the calculation parameters corresponding to each decoding unit to obtain a plurality of convolution operation results; performing accumulation operation on the convolution operation results to obtain an accumulation operation result; performing modulo-2 operation on the accumulated operation result to obtain a second modulo operation result; and repeatedly executing M times, and performing modulo-2 operation on a second modulo operation result obtained by the M times to obtain a check result, wherein M is the ratio of the length of the data block to the number of the decoding units in the semi-iterative decoding process.

It should be noted that, for the description of the multi-bit parallel verification apparatus in the present application, please refer to the description of the multi-bit parallel verification method in the present application, and details are not repeated here.

According to the multi-bit parallel check device provided by the embodiment of the invention, the hard decision bits output by each decoding unit in the Turbo decoder at the same time are determined in the semi-iterative decoding process of the Turbo decoder through the determination module, and when the hard decision bits are output by each decoding unit at the same time through the check module, cyclic redundancy check is carried out according to the hard decision bits output by each decoding unit at the same time. Therefore, the CRC check is started immediately after each decoding unit outputs the hard decision bits in the semi-iterative decoding process, the CRC check is started without waiting for the hard decision bits of all code blocks to be output, the delay caused by the CRC check is reduced, and the utilization rate of the Turbo decoder is improved.

It should be noted that the logic and/or steps represented in the flowcharts or otherwise described herein, such as an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.

It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.