阅读说明：本技术 一种高精度谐波三相电能表 (High-precision harmonic three-phase electric energy meter ) 是由 钱少波 甄荣国 孟娟 陈高 赵洛阳 于 2021-07-12 设计创作，主要内容包括：本发明公开了一种高精度谐波三相电能表,包括电流采样电路,基于高精度锰铜进行电流采样；电压采样电路,基于高精度电阻分压进行电压采样；电流模数转换芯片,对采样输入的电流信号进行模数转换；电压模数转换芯片,对采样输入的电压信号进行模数转换；硬件触发接收电路,同步接收并传输采转换后的采样信号；多路复用电路,对于多组转换后的电流信号进行整合接收；运算单元,对转换后的采集信号进行接收和实时运算；复位控制电路,对电路芯片进行复位处理。本发明精度高,稳定性良好,抗磁抗干扰能力强,输出信号会随时钟信号的输入同步输出。(The invention discloses a high-precision harmonic three-phase electric energy meter which comprises a current sampling circuit, wherein current sampling is carried out on the basis of high-precision manganin; the voltage sampling circuit is used for sampling voltage based on high-precision resistor voltage division; the current analog-to-digital conversion chip is used for performing analog-to-digital conversion on a sampled and input current signal; the voltage analog-to-digital conversion chip is used for performing analog-to-digital conversion on a voltage signal which is sampled and input; the hardware trigger receiving circuit synchronously receives and transmits the sampling signals after sampling conversion; the multiplexing circuit is used for carrying out integrated receiving on a plurality of groups of converted current signals; the operation unit is used for receiving and performing real-time operation on the converted acquisition signals; and the reset control circuit is used for resetting the circuit chip. The invention has high precision, good stability and strong anti-magnetic and anti-interference capability, and the output signal can be synchronously output along with the input of the clock signal.)

1. A high-precision harmonic three-phase electric energy meter is characterized by comprising

The current sampling circuit is used for sampling current based on high-precision manganin;

the voltage sampling circuit is used for sampling voltage based on high-precision resistor voltage division;

the current analog-to-digital conversion chip is used for performing analog-to-digital conversion on a sampled and input current signal, and the input end of the current analog-to-digital conversion chip is connected with the output end of the current sampling circuit;

the voltage analog-to-digital conversion chip is used for performing analog-to-digital conversion on a voltage signal which is sampled and input, and the input end of the voltage analog-to-digital conversion chip is connected with the output end of the voltage sampling circuit;

the hardware trigger receiving circuit synchronously receives and transmits the sampling signals after sampling conversion, and the input end of the hardware trigger receiving circuit is connected with the output end of the voltage analog-to-digital conversion chip;

the multiplexing circuit integrates and receives a plurality of groups of converted current signals, and the input end of the multiplexing circuit is connected with the output end of the current analog-to-digital conversion chip;

the operation unit is used for receiving and performing real-time operation on the converted acquisition signal, a first input end of the operation unit is connected with an output end of the multiplexing circuit, and a second input end of the operation unit is connected with an output end of the hardware trigger receiving circuit;

and the reset control circuit is used for resetting the circuit chip, the input end of the reset control circuit is connected with the output end of the operation unit, and the output end of the reset control circuit is connected with the input ends of the current digital-to-analog conversion chip and the voltage digital-to-analog conversion chip.

2. The high-precision harmonic three-phase electric energy meter according to claim 1, wherein high-speed digital isolation devices are used between the current sampling circuit and the voltage sampling circuit and between the current sampling circuit and the operation unit, the high-speed digital isolation devices provide isolation power for the current sampling circuit and the voltage sampling circuit, and a low-noise LDO power converter is used at the rear end of the isolation power.

3. A high-precision harmonic three-phase electric energy meter according to claim 1 or 2, wherein the current analog-to-digital conversion chip is an MCP3918 chip, and the voltage analog-to-digital conversion chip is an MCP3919 chip.

4. The high-precision harmonic three-phase electric energy meter according to claim 1, wherein the hardware trigger receiving circuit comprises a power supply VCC, a resistor R80, a resistor R81, a resistor R82, a resistor R83, a flip-flop U11A, a capacitor C35, a capacitor C36, a nand gate U12D and a nand gate U12C, the output terminal of the power supply VCC is respectively connected with the first terminal of a resistor R80, the first terminal of a resistor R81 and the first terminal of a resistor R82, the first terminal of the resistor R83 is connected with the output terminal of a voltage analog-to-digital conversion chip SDO-V, and the flip-flop U11A has a first terminal connected with a second terminal of a resistor R82 and a second terminal of a resistor R83The pin terminal is connected with the second terminal of the resistor R80 and receives the input of the SPI-RST signal of the arithmetic unit, and the second terminal of the resistor R82 is connected with the output of the flip-flop U11AThe second end of the resistor R82 is connected with the D pin end of the flip-flop U11A, the second end of the resistor R83 is connected with the CP pin end of the flip-flop U11A, the Q pin end of the flip-flop U11A is connected with the SC end of the SPI of the arithmetic unit, and the Q pin end of the flip-flop U11A is connected with the SC end of the SPI of the arithmetic unitThe pin end is connected with the second input end of the NAND gate U12D and the second input end of the NAND gate U12C, the VCC pin end of the flip-flop U11A is connected with the first end of the capacitor C35, the output end of the power supply VCC and the first end of the capacitor C36, the GND pin end of the flip-flop U11A, the second end of the capacitor C35 and the second end of the capacitor C36The end of the NAND gate U12D is grounded, the first input end of the NAND gate U12D is connected with the output end of the voltage analog-to-digital conversion chip SDO-V, the second input end of the NAND gate U12C receives the signal input of the clock signal ADC-MCLK of the voltage analog-to-digital conversion chip, the output end of the NAND gate U12D is connected with the MOSI end of the operation unit SPI, and the output end of the NAND gate U12C outputs the SPI-SCK signal.

5. The high-precision harmonic three-phase electric energy meter according to claim 1, wherein the multiplexing circuit comprises a channel power supply VCC, a switching counter U6, a flip-flop U9A, a channel decoder U8, a selection driver U7, a nand gate U5D, a nand gate U5C, a capacitor C16, a capacitor C17, a capacitor C18, a capacitor C19, a resistor R25, a resistor R26, a resistor R27, a resistor R28, a resistor R29, a resistor R30 and a resistor R31, the D0 pin terminal, the D1 pin terminal, the D2 pin terminal and the D3 pin terminal of the switching counter U6 are all grounded, the CP pin terminal of the switching counter U6 receives a CHNL-SW signal input of the arithmetic unit, and the CP pin terminal of the switching counter U6 is connected to the groundThe end receives CHNL-RST signal input of an arithmetic unit, a VCC pin end of the switching counter U6 and a first end of a capacitor C16 are connected with an output end of a power supply VCC, a Q0 pin end, a Q1 pin end, a Q2 pin end and a Q3 pin end of the switching counter U6 are respectively connected with an A0 pin end, an A1 pin end, an A2 pin end and a Q3 pin end of a channel decoder U8The pin terminals are connected, the CEP pin terminal of the switching counter U6 is connected with the first terminal of the resistor R26, the CET pin terminal of the switching counter U6 is connected with the first terminal of the resistor R28, and the switching counter U6The pin terminal is connected with the first end of the resistor R29, the GND pin terminal of the switching counter U6 is grounded, the second terminal of the capacitor C16 is grounded, and the output end of the power supply VCC and the first end of the resistor R29 are connectedThe first end of the resistor R25, the second end of the resistor R26, the first end of the resistor R27, the second end of the resistor R28, the second end of the resistor R29 and the first end of the resistor R30 are connected, the first end of the resistor R31 is connected with the SDO-IA end of the current digital-to-analog conversion chip, and the first end of the flip-flop U9A is connected with the SDO-IA end of the current digital-to-analog conversion chipA pin terminal connected to the second terminal of the resistor R25 and receiving CHNL-RST signal input of the arithmetic unit, the flip-flop U9AThe pin terminal is connected with the second terminal of the resistor R27, the D pin terminal of the flip-flop U9A is connected with the second terminal of the resistor R30, the CP terminal of the flip-flop U9A is connected with the second terminal of the resistor R31, and the flip-flop U9AOf pin-end and channel decoder U8Pin terminals are connected to a CS terminal of the operation unit SPI, a Q pin terminal of the flip-flop U9A is connected to a second input terminal of the nand gate U5D and a second input terminal of the nand gate U5C, a VCC pin terminal of the flip-flop U9A, an E3 pin terminal of the channel decoder U8, a VCC pin terminal of the channel decoder U8, a first terminal of the capacitor C17, and a first terminal of the capacitor C18 are connected to an output terminal of the power VCC, a GND pin terminal of the flip-flop U9A, a GND pin terminal of the channel decoder U8, a second terminal of the capacitor C17, and a second terminal of the capacitor C18 are grounded, and a Y0 pin terminal, a Y1 pin terminal, a Y2 pin terminal, and a Y3 pin terminal of the channel decoder U8 are respectively connected to a CS terminal of the selection driver U71 pin end,2 pin ends,3 pin terminals andthe 4 pin terminals are connected, the Y4 pin terminal of the channel decoder U8 is connected with the TE terminal of the operation unit SPI, the a1 pin terminal, the a2 pin terminal, the A3 pin terminal and the a4 pin terminal of the select driver U7 are connected with the SDO-IA terminal, the SDO-IB terminal, the SDO-IC terminal and the SDO-ID terminal of the current digital-to-analog conversion chip, respectively, the GND pin terminal of the select driver U7 is grounded, the Y1 pin terminal, the Y2 pin terminal, the Y3 pin terminal and the Y4 pin terminal of the select driver U7 are connected with the MOSI2 terminal of the SPI of the operation unit, the VCC pin terminal of the select driver U7 and the first terminal of the capacitor C19 are connected with the output terminal of the power supply VCC, the second terminal of the capacitor C19 is grounded, the first input terminal of the nand gate U5D is connected with the SDO-V terminal of the voltage digital-to-analog conversion chip, and the first input terminal of the nand gate U5 receives the first clock signal conversion chip input terminal of the ADC 5C or the ADC chip, the output end of the NAND gate U5D is connected with the MOSI1 end of the SPI of the arithmetic unit, and the output end of the NAND gate U5C outputs the SPI-SCK signal.

6. A high-precision harmonic three-phase electric energy meter according to claim 1, characterized in that the arithmetic unit is an ataxs 70N20 chip based on Cortex-M7 kernel.

7. The high-precision harmonic three-phase electric energy meter according to claim 1, wherein the reset control circuit comprises a power supply VCC, a resistor R21, a resistor R22, a resistor R23, a resistor R24, a flip-flop U4B, a capacitor C15, a NAND gate U5A and a NAND gate U5B, the output end of the power supply VCC is connected with the first end of the resistor R21, the first end of the resistor R23 and the first end of the resistor R24, and the output end of the flip-flop U4B is connected with the first end of the resistor R24 and the second end of the resistor R21Pin terminal and second of resistor R21Terminal connected to and receiving a clock signal MCLK-EN signal input, of said flip-flop U4BA pin terminal is connected with a second terminal of the resistor R23, a D pin terminal of the flip-flop U4B is connected with a second terminal of the resistor R24, a Q pin terminal of the flip-flop U4B is connected with a first terminal of the resistor R22, a CP pin of the flip-flop U4B is connected with a second input terminal of the nand gate U5A, a second terminal of the resistor R22 is connected with a first input terminal of the nand gate U5A, an upper end of the nand gate U5A and a first terminal of the capacitor C15 are connected with an output terminal of the power supply VCC, a second terminal of the capacitor C15 and a lower terminal of the nand gate U5A are grounded, an output terminal of the nand gate U5A is connected with a first input terminal of the nand gate U5B, a second input terminal of the nand gate U5B receives an ADC-MCLK signal input of the current digital-to analog conversion chip or the voltage digital to analog conversion chip, and an output terminal of the nand gate U5B outputs an ADC-MCLK signal.

Technical Field

The invention relates to the field of electric energy meters, in particular to a high-precision harmonic three-phase electric energy meter.

Background

At present, more and more digital harmonic electric energy meters appear in the market, which shows that the digital harmonic electric energy meters are more and more widely applied, but some digital harmonic electric energy meters have low precision, poor direct current resistance and magnetic field resistance and self-heating. For example, an "embedded electric energy meter with harmonic measurement function" disclosed in chinese patent literature, whose publication number is "CN 201562011U", includes an electric power metering module, which collects and measures external three-phase voltage and current, and transmits the metering data to a microprocessor module; the LED driving module drives the LED display screen; the LED display screen displays the metering data and harmonic components output by the microprocessor module; the storage module is used for storing the system setting parameters, the accumulated electric power value and the standard calibration value of the electric power metering module; and the microprocessor module reads the electric quantity data and calculates the harmonic voltage and the harmonic current through Fourier transform. By adopting the structure and the method, the voltage current acquired by the power metering module is processed by the micro-processing module by adopting fast Fourier transform to obtain 3-31 times of harmonic voltage and harmonic current, and the harmonic voltage and the harmonic current are displayed on the liquid crystal screen. The electric energy meter can improve the harmonic measurement precision of the electric quantity meter to 1%, simplify the hardware design structure and improve the use reliability of the product. However, no isolation processing is performed inside the device, strong electricity may affect weak points, so that the collected data is not accurate enough, and the direct current resistance and the magnetic field resistance are poor.

Disclosure of Invention

The invention provides a high-precision harmonic three-phase electric energy meter, aiming at overcoming the problems of low precision, poor direct-current resistance and magnetic field resistance and spontaneous heating of a harmonic electric energy meter in the prior art, and aiming at improving the precision, enhancing the direct-current resistance and magnetic field resistance and solving the spontaneous heating problem of the electric energy meter.

A high-precision harmonic three-phase electric energy meter comprises a current sampling circuit, a current sampling circuit and a harmonic generation circuit, wherein the current sampling circuit is used for sampling current based on high-precision manganin; the voltage sampling circuit is used for sampling voltage based on high-precision resistor voltage division; the current analog-to-digital conversion chip is used for performing analog-to-digital conversion on a sampled and input current signal, and the input end of the current analog-to-digital conversion chip is connected with the output end of the current sampling circuit; the voltage analog-to-digital conversion chip is used for performing analog-to-digital conversion on a voltage signal which is sampled and input, and the input end of the voltage analog-to-digital conversion chip is connected with the output end of the voltage sampling circuit; the hardware trigger receiving circuit synchronously receives and transmits the sampling signals after sampling conversion, and the input end of the hardware trigger receiving circuit is connected with the output end of the voltage analog-to-digital conversion chip; the multiplexing circuit integrates and receives a plurality of groups of converted current signals, and the input end of the multiplexing circuit is connected with the output end of the current analog-to-digital conversion chip; the operation unit is used for receiving and performing real-time operation on the converted acquisition signal, a first input end of the operation unit is connected with an output end of the multiplexing circuit, and a second input end of the operation unit is connected with an output end of the hardware trigger receiving circuit; and the reset control circuit is used for resetting the circuit chip, the input end of the reset control circuit is connected with the output end of the operation unit, and the output end of the reset control circuit is connected with the input ends of the current digital-to-analog conversion chip and the voltage digital-to-analog conversion chip. The current sampling circuit is based on high-precision manganin sampling because the manganin has the advantages of good stability, direct current resistance, magnetic field resistance, no phase difference, no wireless error, small volume, small heat productivity and the like, and the voltage sampling circuit adopts high-precision resistor voltage division to sample voltage and has the advantages of small error, high precision, good stability and the like.

Preferably, high-speed digital isolation devices are adopted among the current sampling circuit, the voltage sampling circuit and the operation unit, the high-speed digital isolation devices provide isolation power for the current sampling circuit and the voltage sampling circuit, and a low-noise LDO power converter is adopted at the rear end of the isolation power. The high-speed digital isolation device ensures the electrical isolation between strong current and weak current, and the low-noise LDO power converter is adopted at the rear end of the isolation power supply, so that the power supply of the current or voltage digital-to-analog conversion chip is not interfered by the high-speed digital signal, and the sampling precision is improved.

Preferably, the current analog-to-digital conversion chip adopts an MCP3918 chip, and the voltage analog-to-digital conversion chip adopts an MCP3919 chip. The MCP3918 chip and the MCP3919 chip are both 24-bit delta-sigma type ADC chips, the MCP3918 chip is a single-channel chip and is used for sampling current signals, and the MCP3918 chip has the characteristics of high precision, high sampling rate, small temperature influence, simple interface and the like, and the MCP3919 chip is a three-channel chip and is used for sampling voltage signals and also has the characteristics of high precision, high sampling rate, small temperature influence, simple interface and the like.

Preferably, the hardware trigger receiving circuit includes a power supply VCC, a resistor R80, a resistor R81, a resistor R82, a resistor R83, a flip-flop U11A, a capacitor C35, a capacitor C36, a nand gate U12D, and a nand gate U12C, an output terminal of the power supply VCC is respectively connected to a first terminal of a resistor R80, a first terminal of a resistor R81, and a first terminal of a resistor R82, a first terminal of the resistor R83 is connected to an SDO-V output terminal of the voltage analog-to-digital conversion chip, and an output terminal of the flip-flop U11A is connected to an output terminal of the voltage analog-to-digital conversion chip SDO-VThe pin terminal is connected with the second terminal of the resistor R80 and receives the input of the SPI-RST signal of the arithmetic unit, and the second terminal of the resistor R82 is connected with the output of the flip-flop U11AThe second end of the resistor R82 is connected with the D pin end of the flip-flop U11A, the second end of the resistor R83 is connected with the CP pin end of the flip-flop U11A, the Q pin end of the flip-flop U11A is connected with the SC end of the SPI of the arithmetic unit, and the Q pin end of the flip-flop U11A is connected with the SC end of the SPI of the arithmetic unitThe pin end connection is connected with a second input end of the nand gate U12D and a second input end of the nand gate U12C, a VCC pin end of the flip-flop U11A is connected with a first end of the capacitor C35, an output end of the power supply VCC and a first end of the capacitor C36, a GND pin end of the flip-flop U11A, a second end of the capacitor C35 and a second end of the capacitor C36 are grounded, a first input end of the nand gate U12D is connected with an SDO-V output end of the voltage analog-to-digital conversion chip, a second input end of the nand gate U12C receives a signal input of a clock signal ADC-MCLK of the voltage analog-to-digital conversion chip, an output end of the nand gate U12D is connected with an MOSI end of the operation unit SPI, and an output end of the nand gate U12C outputs an SPI-SCK signal. The hardware trigger receiving circuit is used for ensuring that data can be synchronized, and an output signal is synchronously output along with the input of a clock signal.

Preferably, the multiplexing circuit comprises a channel power supply VCC, a switching counter U6, a trigger U9A and a channel decoderThe encoder U8, the selection driver U7, the NAND gate U5D, the NAND gate U5C, the capacitor C16, the capacitor C17, the capacitor C18, the capacitor C19, the resistor R25, the resistor R26, the resistor R27, the resistor R28, the resistor R29, the resistor R30 and the resistor R31 are all grounded, the D0 pin terminal, the D1 pin terminal, the D2 pin terminal and the D3 pin terminal of the switching counter U6 are all grounded, the CP pin terminal of the switching counter U6 receives CHNL-SW signal input of the arithmetic unit, and the switching counter U6 is connected with the CHNL-SW signal input circuitThe end receives CHNL-RST signal input of an arithmetic unit, a VCC pin end of the switching counter U6 and a first end of a capacitor C16 are connected with an output end of a power supply VCC, a Q0 pin end, a Q1 pin end, a Q2 pin end and a Q3 pin end of the switching counter U6 are respectively connected with an A0 pin end, an A1 pin end, an A2 pin end and a Q3 pin end of a channel decoder U8The pin terminals are connected, the CEP pin terminal of the switching counter U6 is connected with the first terminal of the resistor R26, the CET pin terminal of the switching counter U6 is connected with the first terminal of the resistor R28, and the switching counter U6The pin end is connected with the first end of the resistor R29, the GND pin end of the switching counter U6 is grounded, the second end of the capacitor C16 is grounded, the output end of the power supply VCC is connected with the first end of the resistor R25, the second end of the resistor R26, the first end of the resistor R27, the second end of the resistor R28, the second end of the resistor R29 and the first end of the resistor R30, the first end of the resistor R31 is connected with the SDO-IA end of the current digital-to-analog conversion chip, and the trigger U9A is connected with the SDO-IA end of the current digital-to-analog conversion chipA pin terminal connected to the second terminal of the resistor R25 and receiving CHNL-RST signal input of the arithmetic unit, the flip-flop U9APin terminal and resistorThe second end of the R27 is connected, the D pin end of the trigger U9A is connected with the second end of the resistor R30, the CP end of the trigger U9A is connected with the second end of the resistor R31, and the trigger U9AOf pin-end and channel decoder U8Pin terminals are connected to a CS terminal of the operation unit SPI, a Q pin terminal of the flip-flop U9A is connected to a second input terminal of the nand gate U5D and a second input terminal of the nand gate U5C, a VCC pin terminal of the flip-flop U9A, an E3 pin terminal of the channel decoder U8, a VCC pin terminal of the channel decoder U8, a first terminal of the capacitor C17, and a first terminal of the capacitor C18 are connected to an output terminal of the power VCC, a GND pin terminal of the flip-flop U9A, a GND pin terminal of the channel decoder U8, a second terminal of the capacitor C17, and a second terminal of the capacitor C18 are grounded, and a Y0 pin terminal, a Y1 pin terminal, a Y2 pin terminal, and a Y3 pin terminal of the channel decoder U8 are respectively connected to a CS terminal of the selection driver U7A pin end,A pin end,Pin terminal andpin terminals are connected, a Y4 pin terminal of the channel decoder U8 is connected with a TE terminal of an SPI of the operation unit, an a1 pin terminal, an a2 pin terminal, an A3 pin terminal and an a4 pin terminal of the selection driver U7 are connected with an SDO-IA terminal, an SDO-IB terminal, an SDO-IC terminal and an SDO-ID terminal of the current digital-to-analog conversion chip, respectively, a GND pin terminal of the selection driver U7 is grounded, a Y1 pin terminal, a Y2 pin terminal, a Y3 pin terminal and a Y4 pin terminal of the selection driver U7 are connected with an MOSI2 terminal of the SPI of the operation unit, and a VCC pin terminal of the selection driver U7 is connected with a MOSI2 terminal of the SPI of the operation unitThe pin end and the first end of the capacitor C19 are connected with the output end of a power supply VCC, the second end of the capacitor C19 is grounded, the first input end of the NAND gate U5D is connected with the SDO-V end of the voltage digital-to-analog conversion chip, the first input end of the NAND gate U5C receives the clock signal ADC-MCLK signal input of the current digital-to-analog conversion chip or the voltage digital-to-analog conversion chip, the output end of the NAND gate U5D is connected with the MOSI1 end of the SPI of the arithmetic unit, and the output end of the NAND gate U5C outputs the SPI-SCK signal. A total four current sampling circuits use a piece of MCP3918 chip to process data, and the operation unit only has two SPI interfaces, so the multiplexing circuit is used to switch data source, and the multiplexing of SPI interfaces of the operation unit is realized.

Preferably, the arithmetic unit is an ATSAMS70N20 chip based on a Cortex-M7 kernel. The external interface is rich, and the device is mainly used for completing data acquisition and real-time operation of a current or voltage digital-to-analog conversion chip.

Preferably, the reset control circuit comprises a power supply VCC, a resistor R21, a resistor R22, a resistor R23, a resistor R24, a flip-flop U4B, a capacitor C15, a nand gate U5A and a nand gate U5B, the output end of the power supply VCC is connected with the first end of the resistor R21, the first end of the resistor R23 and the first end of the resistor R24, and the output end of the flip-flop U4B is connected with the first end of the resistor R21, the first end of the resistor R23 and the first end of the resistor R24The pin terminal is connected with the second terminal of the resistor R21 and receives the clock signal MCLK-EN signal input, of the trigger U4BThe pin terminal is connected with the second end of the resistor R23, the D pin terminal of the flip-flop U4B is connected with the second end of the resistor R24, the Q pin terminal of the flip-flop U4B is connected with the first end of the resistor R22, the CP pin of the flip-flop U4B is connected with the second input end of the NAND gate U5A, the second end of the resistor R22 is connected with the first input end of the NAND gate U5A, the upper end of the NAND gate U5A and the first end of the capacitor C15 are connected with the output end of a power supply VCC, the second end of the capacitor C15 and the lower end of the NAND gate U5A are grounded, and the NAND gate U5A is connected with the lower end of the power supply VCCThe output end of the gate U5A is connected to a first input end of the nand gate U5B, a second input end of the nand gate U5B receives an ADC-RST signal input of the current digital-to-analog conversion chip or the voltage digital-to-analog conversion chip, and an output end of the nand gate U5B outputs an ADC-MCLK signal. The reset circuit can be used as an internal watchdog reset function to monitor clock signals, thereby realizing the reset of a current or voltage digital-to-analog conversion chip.

Therefore, the invention has the following beneficial effects: (1) the precision is high; (2) the stability is excellent; (3) the anti-magnetic and anti-interference capability is strong; (4) the output signal is output synchronously with the input of the clock signal.

Drawings

FIG. 1 is a block diagram of the present invention;

FIG. 2 is a schematic diagram of a hardware triggered receive circuit of the present invention;

FIG. 3 is a schematic diagram of the multiplexing circuit of the present invention;

fig. 4 is a schematic diagram of the reset control circuit of the present invention.

In the figure, the circuit comprises a current sampling circuit 1, a voltage sampling circuit 2, a current digital-to-analog conversion chip 3, a voltage digital-to-analog conversion chip 4, a voltage digital-to-analog conversion chip 5, a hardware trigger receiving circuit 6, a multiplexing circuit 7, an arithmetic unit 8 and a reset control circuit.

Detailed Description

The invention is further described with reference to the following detailed description and accompanying drawings.

In the embodiment shown in fig. 1, the current sampling circuit is divided into 4 current sampling circuits, which respectively sample A, B, C and N four current signals, and then transmit the current signals obtained by sampling to the current digital-to-analog conversion chip, because the current digital-to-analog conversion chip is an MCP3918 chip, the MCP3918 chip is a single-channel chip and can only transmit signals one by one, the current digital-to-analog conversion chip is also divided into four blocks, receives current signals transmitted by A, B, C and N four current sampling circuits respectively, then converts the received sampled current signals, amplifies the signals by matching with a gain amplifier, transmits the processed current signals to a multiplexing circuit for integration and circuit multiplexing, and transmits the signals to an operation unit for data acquisition and timely operation. The voltage sampling circuit is divided into 3 voltage sampling circuits, voltage signals of A, B paths and C paths are respectively collected, then the sampled voltage signals are transmitted to a voltage digital-to-analog conversion chip, the voltage digital-to-analog conversion chip selects an MCP3919 chip, the MCP3919 chip is a three-channel chip, and one-to-three signal transmission can be carried out, so that only one voltage digital-to-analog conversion chip is adopted to receive the voltage signals transmitted by the A, B and C paths of voltage sampling circuits, then the received sampled voltage signals are converted, and the processed voltage signals are transmitted to a hardware trigger receiving circuit, so that synchronous output of input of data to a clock signal can be ensured, and then the output signals are transmitted to an operation unit for data integration collection and timely operation. The arithmetic unit can control the resetting of the current and voltage digital-to-analog conversion chip through the reset control circuit, the reset control circuit has a watchdog reset function, and the arithmetic unit can reset the current or voltage digital-to-analog conversion chip by closing the input of the clock signal. The MCP3918 chip and the MCP3919 chip are both 24-bit delta-sigma type ADC chips, the MCP3918 chip is a single-channel chip and is used for sampling current signals, and the MCP3918 chip has the characteristics of high precision, high sampling rate, small temperature influence, simple interface and the like, and the MCP3919 chip is a three-channel chip and is used for sampling voltage signals and also has the characteristics of high precision, high sampling rate, small temperature influence, simple interface and the like. The specific 2-Wire communication interfaces of the MCP3918 chip and the MCP3919 chip integrate chip resetting, clock input, data output and multiplexing functions, so that synchronous sampling of multiple signals can be realized, conversion results are output in a centralized mode, and interconnection with an operation unit interface is facilitated. The operation unit adopts an ATSAMS70N20 chip based on a Cortex-M7 kernel, the main frequency reaches 300MHz, 16KB I-Cache and 16KB D-Cache are integrated, a single-precision hardware floating point operation unit and a double-precision hardware floating point operation unit are provided, DSP instructions are supported, 384KB SRAM and 1MB program FLASH are embedded, and abundant peripheral interfaces are configured.

In the embodiment shown in fig. 2, the hardware trigger receiving circuit includes a power supply VCC, a resistor R80, a resistor R81, a resistor R82, a resistor R83, a flip-flop U11A, a capacitor C35, a capacitor C36, a nand gate U12D and a nand gate U12C, an output terminal of the power supply VCC is respectively connected to a first terminal of a resistor R80, a first terminal of the resistor R81 and a first terminal of a resistor R82, a first terminal of the resistor R83 is connected to an SDO-V output terminal of the voltage analog-to-digital conversion chip, and an output terminal of the flip-flop U11AThe pin terminal is connected to the second terminal of the resistor R80 and receives the input of the SPI-RST signal of the arithmetic unit, the second terminal of the resistor R82 is connected to the output of the flip-flop U11AThe pin terminal is connected, the second terminal of the resistor R82 is connected with the D pin terminal of the flip-flop U11A, the second terminal of the resistor R83 is connected with the CP pin terminal of the flip-flop U11A, the Q pin terminal of the flip-flop U11A is connected with the SC terminal of the operation unit SPI, and the flip-flop U11A is connected with the D pin terminal of the flip-flop U11AThe pin terminal is connected with the second input terminal of the nand gate U12D and the second input terminal of the nand gate U12C, the VCC pin terminal of the flip-flop U11A is connected with the first terminal of the capacitor C35, the output terminal of the power supply VCC and the first terminal of the capacitor C36, the GND pin terminal of the flip-flop U11A, the second terminal of the capacitor C35 and the second terminal of the capacitor C36 are grounded, the first input terminal of the nand gate U12D is connected with the SDO-V output terminal of the voltage analog-to-digital conversion chip, the second input terminal of the nand gate U12C receives the signal input of the clock signal ADC-MCLK of the voltage analog-to-digital conversion chip, the output terminal of the nand gate U12D is connected with the MOSI terminal of the operation unit SPI, and the output terminal of the nand gate U12C outputs the SPI-SCK signal. The hardware trigger receiving circuit is used for ensuring that data can be synchronized, and an output signal is synchronously output along with the input of a clock signal. The conversion result of the current and voltage digital-to-analog conversion chip is along with the inputThe signal output mode is compatible with the SPI interface of the operation unit, but the clock signal MCLK provided for the current and voltage D/A conversion chip is continuous, and the SPI interface of the operation unit can not obtain data from the starting point of the data, so the SPI interface of the operation unit is processed synchronously when receiving the data. Can trigger the clock signal and the chip select signal of arithmetic unit SPI interface after the count overflows at every turn, start the SPI interface and receive data, close the SPI interface after the data of fixed length is received to the SPI interface, wait for next signal transmission. When the SPI-RST signal goes low, flip-flop U11A is in a clear state, wherein the output Q pin is also clear,the pin terminal is set to high level, so the chip select signal SPI-CS is high level, and the SPI-SCLK and SPI-MOSI signals are kept low level; when the SPI-RST signal goes high, flip-flop U11A is in an active state, and when there is a rising signal at the CP pin, the D pin of flip-flop U11A is in the same state as Q, set high,the pin end is cleared, the SPI-CS signal is pulled down, simultaneously along with the ADC-RST signal of the current or voltage digital-analog conversion chip and the SDO-V signal of the voltage digital-analog conversion chip are both output to the SPI-SCK and the SPI-MOSI, the SPI interface can receive the output signal from the current or voltage digital-analog conversion chip, when the data reception is finished, the SPI-RST signal is pulled down, the signals of the SPI-CS end and the SPI-SCK end are restored to the initial state, and the trigger signal generated by the next data rising is waited.

In the embodiment shown in fig. 3, the multiplexing circuit includes a channel power VCC, a switching counter U6, a flip-flop U9A, a channel decoder U8, a select driver U7, a nand gate U5D, a nand gate U5C, a capacitor C16, a capacitor C17, a capacitor C18, a capacitor C19, a resistor R25, a resistor R26, a resistor R27, a resistor R28, a resistor R29, a resistor R30 and a resistor R31, a D0 pin terminal, a D1 pin terminal, a D2 pin terminal and a D3 pin terminal of the switching counter U6 are all grounded,the CP pin terminal of the switching counter U6 receives the CHNL-SW signal input of the operation unit, and switches the counter U6The end receives CHNL-RST signal input of the arithmetic unit, a VCC pin end of the switching counter U6 and a first end of the capacitor C16 are connected with an output end of a power supply VCC, a Q0 pin end, a Q1 pin end, a Q2 pin end and a Q3 pin end of the switching counter U6 are respectively connected with an A0 pin end, an A1 pin end, an A2 pin end and a Q3 pin end of the channel decoder U8The pin terminal is connected, the CEP pin terminal of the switching counter U6 is connected with the first terminal of the resistor R26, the CET pin terminal of the switching counter U6 is connected with the first terminal of the resistor R28, and the switching counter U6 is connectedThe pin terminal is connected with the first end of a resistor R29, the GND pin terminal of a switching counter U6 is grounded, the second end of a capacitor C16 is grounded, the output end of a power supply VCC is connected with the first end of a resistor R25, the second end of a resistor R26, the first end of a resistor R27, the second end of a resistor R28, the second end of a resistor R29 and the first end of a resistor R30, the first end of a resistor R31 is connected with the SDO-IA end of a current digital-to-analog conversion chip, and the trigger U9A is connected with the power supply voltage regulatorThe pin terminal is connected to the second terminal of the resistor R25 and receives the CHNL-RST signal input of the arithmetic unit, of the flip-flop U9AThe pin terminal is connected with the second terminal of the resistor R27, the D pin terminal of the trigger U9A is connected with the second terminal of the resistor R30, the CP terminal of the trigger U9A is connected with the second terminal of the resistor R31, and the trigger U9AOf pin-end and channel decoder U8The pin terminal is connected with the CS terminal of the operation unit SPI, the Q pin terminal of the flip-flop U9A is connected with the second input terminal of the nand gate U5D and the second input terminal of the nand gate U5C, the VCC pin terminal of the flip-flop U9A, the E3 pin terminal of the channel decoder U8, the VCC pin terminal of the channel decoder U8, the first terminal of the capacitor C17 and the first terminal of the capacitor C18 are connected with the output terminal of the power supply VCC, the GND pin terminal of the flip-flop U9A, the GND pin terminal of the channel decoder U8, the second terminal of the capacitor C17 and the second terminal of the capacitor C18 are grounded, and the Y0 pin terminal, the Y1 pin terminal, the Y2 pin terminal and the Y3 pin terminal of the channel decoder U8 are respectively connected with the CS terminal of the select driver U7A pin end,A pin end,Pin terminal andpin terminals are connected, a pin terminal Y4 of a channel decoder U8 is connected to a terminal TE of an operation unit SPI, a pin terminal a1, a pin terminal a2, a pin terminal a3 and a pin terminal a4 of a select driver U7 are connected to an SDO-IA terminal, an SDO-IB terminal, an SDO-IC terminal and an SDO-ID terminal of a current digital-to-analog conversion chip, respectively, a GND pin terminal of a select driver U7 is grounded, a pin terminal Y1, a pin terminal Y2, a pin terminal Y3 and a pin terminal Y4 of a select driver U7 are connected to an MOSI2 terminal of the SPI of the operation unit, a VCC pin terminal of a select driver U7 and a first terminal of a capacitor C19 are connected to an output terminal of a power supply VCC, a second terminal of a capacitor C19 is grounded, a first input terminal of a nand gate U5D is connected to an SDO-V terminal of the voltage digital-to-analog conversion chip, a first input terminal of a nand gate U5C receives a clock signal or an ADC-lk signal converted from the current digital-to-analog conversion chip, the output end of the NAND gate U5D is connected with the MOSI1 end of the SPI of the arithmetic unit, and the output end of the NAND gate U5C outputs the SPI-SCK signal. One total of four current samplesThe circuits use one MCP3918 chip to process data, and the operation unit only has two SPI interfaces, so the multiplexing circuit is used to switch the data source, and the multiplexing of the SPI interfaces of the operation unit is realized. . Because the current sampling circuits need to be isolated from each other, one MCP3918 chip is used for collecting current signals, A, B, C and D are shared, and an arithmetic unit only comprises 2 SPI interfaces, so that reception of sampling currents adopts a duplex mode, and multiplexing of the SPI interfaces can be realized through switching of signal sources. The multiplexing circuit internally comprises a hardware trigger receiving circuit, so the multiplexing circuit can also ensure the synchronization of data, and output signals are synchronously output along with the input of clock signals. The multiplexing circuit is based on the hardware trigger receiving circuit, a channel switching counter U6 is added, channel switching signals CHNL-SW of the operation unit are counted, the counted value is output to Q0-Q3, then a decoder U8 converts channel values into channel selection signals and outputs the channel selection signals to Y0-Y4, Y0-Y3 respectively correspond to A, B, C and output signals of an N four-way current digital-to-analog conversion chip, then a driver U7 is used for selecting signal input, one of the signals is output to an SPI-MOSI2 end, when the channel signals are switched to Y5, data signals of 4 sampling channels are transmitted, at the moment, the operation mode that the CHNL-RST signals are pulled down first and pulled up then can be pulled up through the operation unit, U9A and the switching counter U6 of the hardware trigger receiving circuit are reset to an initial state simultaneously, waiting for the next data transmission.

In the embodiment shown in fig. 4, the reset control circuit includes a power supply VCC, a resistor R21, a resistor R22, a resistor R23, a resistor R24, a flip-flop U4B, a capacitor C15, a nand gate U5A, and a nand gate U5B, wherein an output terminal of the power supply VCC is connected to a first terminal of the resistor R21, a first terminal of the resistor R23, and a first terminal of the resistor R24

The RD pin of the flip-flop U4B is connected to the second terminal of the resistor R21 and receives the clock signal MCLK-EN

A signal input, the SD pin terminal of the flip-flop U4B is connected with the second terminal of the resistor R23, the D pin terminal of the flip-flop U4B is connected with the second terminal of the resistor R24,the Q pin end of the flip-flop U4B is connected with the first end of the resistor R22, the CP pin of the flip-flop U4B is connected with the second input end of the NAND gate U5A, the second end of the resistor R22 is connected with the first input end of the NAND gate U5A, the upper end of the NAND gate U5A and the first end of the capacitor C15 are connected with the output end of the power supply VCC, the second end of the capacitor C15 and the lower end of the NAND gate U5A are grounded, the output end of the NAND gate U5A is connected with the first input end of the NAND gate U5B, the second input end of the NAND gate U5B receives the ADC-RST signal input of the current digital-to-analog conversion chip or the voltage digital to-analog conversion chip, and the output end of the NAND gate U5B outputs the ADC-MCLK signal. The reset circuit can be used as an internal watchdog reset function to monitor clock signals, thereby realizing the reset of a current or voltage digital-to-analog conversion chip. When the clock signal MCLK pin of the current and voltage digital-to-analog conversion chip detects the rising edge of the signal, the watchdog timing function is started, and the time t set by the watchdog is_watchIf the clock signal MCLK pin of the current and voltage digital-to-analog conversion chip does not detect the falling edge, the sufficient reset function of the watchdog is generated, the whole chip is restored to the reset state, and if the watchdog sets time t_watchWhen the clock signal MCLK pin of the internal current and voltage digital-to-analog conversion chip detects a falling edge, the watchdog is cleared and waits for the next rising edge. When the current or voltage digital-to-analog conversion chip needs to be reset, the input of the clock signal MCLK is firstly closed, the Q pin of U4B becomes low by pulling MCLK-EN low, and U5A outputs high level, so that the output signal of U5B is determined by the ADC-RST signal of the current or voltage digital-to-analog conversion chip, when the ADC-RST signal is high level, the output is low level, and when the ADC-RST signal is low level, the output is high level, so that the reset of the current or voltage digital-to-analog conversion chip is realized.

A flip-flop U4B in the reset control circuit, a flip-flop U11A in the hardware trigger receiving circuit and a flip-flop U9A in the multiplexing circuit all adopt a two-channel D-Q flip-flop with a 74HC74 model, and when the RD pin end is at a low level and the SD pin end is at a high level, the output of the Q pin end is cleared, namely the output is 0; when the RD pin terminal is at a high level and the SD pin terminal is at a low level, the RD pin terminal is set as the output of the Q pin terminal, that is, the output is 1; when the RD pin terminal and the SD pin terminal are both at a high level, the output of the D pin is the same as the Q pin at the rising edge of the CP signal.

A channel switching counter U6 of the multiplexing circuit adopts a preset type 4-bit binary counter of 74HC161 model, and an MR pin is a reset signal end and can clear the count; the CP pin end is the input of the counting signal, and the counting is added with 1 on each rising edge; Q0-Q3 are binary count values; D0-D3 are preset values.

A channel decoder U8 in the multiplexing circuit adopts A3-8 line decoder of a 74HC138 model, E1-E3 are enabling control signals, A0-A2 are decoding input signals, Y0-Y7 are decoding output signals, and the channel decoder U8 is effective in low level.

The driver U7 in the multiplexing circuit is a 4-channel 3-state line driver of type 74HC125, which has a channel output signal Y equal to the channel input signal a when the output enable signal OE is low and a high impedance state if the output enable signal OE is high.

The current sampling circuit is based on high-precision manganin sampling, and has the advantages of good stability, direct current resistance, magnetic field resistance, no phase difference, no wireless error, small volume, small heat productivity and the like because the manganin precision is 1 percent, and the temperature coefficient is less than 20 ppm. Because the rear end of the current sampling circuit adopts a 24-bit high-precision current digital-to-analog conversion chip which can be matched with a gain amplifier, when the maximum input quantity is 10A current, 1M omega of manganin is adopted, the maximum power consumption is 0.1W, and almost no self-heating exists. The voltage sampling circuit adopts a high-precision resistor for voltage division sampling, the precision of the resistor is higher than 1%, and the voltage sampling circuit has the same advantages as the current sampling circuit.

A high-speed digital isolation device is adopted between a current sampling circuit and an operation unit at the rear end, the device provides an isolation power supply required by the current sampling circuit while providing a digital isolation channel, the isolation voltage reaches 7KV, the electrical isolation between strong current and weak current is ensured, the communication speed is up to 150MHz, the real-time transmission of sampling data is ensured, a low-noise LDO power converter is adopted at the rear end of the isolation power supply, the power supply of a current and voltage digital-to-analog conversion chip is ensured not to be interfered by high-speed digital signals, and the sampling precision is improved.

The above-described embodiments are only preferred embodiments of the present invention, and are not intended to limit the present invention in any way, and other variations and modifications may be made without departing from the spirit of the invention as set forth in the claims.