阅读说明：本技术 负载检测电路及放大电路 (Load detection circuit and amplification circuit ) 是由 德田郁实 于 2021-04-21 设计创作，主要内容包括：本发明提供负载检测电路及放大电路,高精度地检测负载阻抗。负载检测电路(10)具备第一检测部和第二检测部。第一检测部具备电容器(113)及电容器(114),与将RF放大器(20)的输出端与负载(ZLD)之间连接的信号传输线路(101)进行容性耦合而输出第一信号。第二检测部具备电感器(111)及电感器(112),与信号传输线路(101)进行感性耦合而输出第二信号。(The invention provides a load detection circuit and an amplification circuit, which can detect load impedance with high precision. The load detection circuit (10) is provided with a first detection unit and a second detection unit. The first detection unit is provided with a capacitor (113) and a capacitor (114), and outputs a first signal by capacitively coupling with a signal transmission line (101) connecting between the output terminal of the RF amplifier (20) and the load (ZLD). The second detection unit is provided with an inductor (111) and an inductor (112), and inductively couples with the signal transmission line (101) to output a second signal.)

1. A load detection circuit, wherein,

the load detection circuit includes:

a first detection unit which outputs a first signal by capacitively coupling to a signal transmission line connecting an output terminal of the RF amplifier and a load; and

and a second detection unit which outputs a second signal by inductively coupling the signal transmission line.

2. The load detection circuit of claim 1,

the load detection circuit includes an arithmetic unit that generates a load impedance detection signal by subtracting the first signal and the second signal.

3. The load detection circuit of claim 2,

the arithmetic unit adds the first signal and the second signal to generate a power detection signal.

4. The load detection circuit of claim 2 or 3,

the arithmetic unit includes a logarithmic converter that logarithmically converts the first signal and the second signal.

5. The load detection circuit of any of claims 2 to 4,

the load detection circuit includes a detector circuit that detects the first signal and the second signal before being input to the arithmetic unit.

6. A load detection circuit, wherein,

the load detection circuit includes:

a first detection unit capacitively coupled to a signal transmission line connecting an output terminal of the RF amplifier and a load; and

a second detection section inductively coupled to the signal transmission line,

the first detection part is connected with the second detection part,

outputting a first signal from the load side of the second detection portion,

a second signal is output from an output end side of the RF amplifier of the second detection section.

7. An amplifying circuit, wherein,

the amplification circuit includes:

the load detection circuit of any of claims 2 to 4;

the RF amplifier;

an output matching circuit; and

a control circuit to which the load impedance detection signal is input,

the control circuit controls the impedance of the output matching circuit using the load impedance detection signal.

8. The amplification circuit of claim 7,

the amplifying circuit is provided with an input matching circuit connected to an input of the RF amplifier,

the control circuit controls the impedance of the input matching circuit using the load impedance detection signal.

9. The amplification circuit of claim 8,

the amplification circuit is provided with a sub-RF amplifier connected in parallel with the RF amplifier,

the input matching circuit is also connected to the input of the secondary RF amplifier,

the control circuit controls the impedance of the input matching circuit using the load impedance detection signal.

10. An amplifying circuit, wherein,

the amplification circuit includes:

the load detection circuit of any of claims 2 to 4;

the RF amplifier;

an output matching circuit; and

a control circuit to which the load impedance detection signal is input,

the control circuit controls a driving condition of the RF amplifier using the load impedance detection signal.

11. The amplification circuit of claim 10,

the control circuit controls a bias voltage of the RF amplifier as the driving condition.

12. The amplification circuit of claim 10 or 11,

the control circuit controls a drive voltage of the RF amplifier as the drive condition.

13. The amplification circuit of any one of claims 10 to 12,

the amplification circuit is provided with a sub-RF amplifier connected in parallel with the RF amplifier,

the control circuit controls a driving condition of the sub RF amplifier using the load impedance detection signal.

Technical Field

The present invention relates to a load detection circuit for detecting a load impedance of an amplifier, and an amplifier circuit including the load detection circuit.

Background

Patent document 1 describes a matching circuit connected between a power amplifier circuit and an output load. The matching circuit adjusts the load impedance on the output load side as viewed from the power amplifying circuit.

Prior art documents

Patent document

Patent document 1: japanese patent laid-open publication No. 2004-112810

Disclosure of Invention

Problems to be solved by the invention

However, if the load impedance on the output load side as viewed from the power amplifier circuit cannot be detected with high accuracy, the matching circuit cannot be adjusted appropriately. In particular, when the output load varies, the matching circuit must be appropriately adjusted according to the load impedance to the output load.

Therefore, an object of the present invention is to detect load impedance of a load as viewed from a power amplifier (amplifier) with high accuracy.

Means for solving the problems

The load detection circuit of the present invention includes a first detection unit and a second detection unit. The first detection unit outputs a first signal by capacitively coupling a signal transmission line connecting an output terminal of the RF amplifier and a load. The second detection unit inductively couples with the signal transmission line to output a second signal.

In this structure, the first signal and the second signal reflect the characteristics of the RF signal output from the RF amplifier. More specifically, the first and second signals reflect the voltage and current amplitudes, respectively, in the RF signal. Therefore, the impedance (load impedance) on the load side viewed from the RF amplifier can be calculated by using the first signal and the second signal.

Effects of the invention

According to the present invention, the load impedance of the load as viewed from the power amplifier (amplifier) can be detected with high accuracy.

Drawings

Fig. 1 is an equivalent circuit diagram of a load detection circuit of the first embodiment.

Fig. 2 is an equivalent circuit diagram of the amplifier circuit of the first embodiment.

Fig. 3 is an equivalent circuit diagram of an amplifier circuit of the second embodiment.

Fig. 4 is an equivalent circuit diagram of the amplifying circuit of the third embodiment.

Fig. 5 is an equivalent circuit diagram of an amplifier circuit of the fourth embodiment.

Fig. 6 is an equivalent circuit diagram of an amplifier circuit of the fifth embodiment.

Fig. 7 is an equivalent circuit diagram of an amplifier circuit according to the sixth embodiment.

Fig. 8 is an equivalent circuit diagram of an amplifier circuit of the seventh embodiment.

Fig. 9 is an equivalent circuit diagram of an amplifier circuit according to the eighth embodiment.

Fig. 10 is an equivalent circuit diagram of a load detection circuit of the ninth embodiment.

Description of the reference numerals

1. 1A, 1B, 1C, 1D, 1E, 1F, 1G: an amplifying circuit;

10. 10H: a load detection circuit;

11. 11H: a detection unit;

12: a wave detection unit;

13: a calculation unit;

20. 21, 22, 23: an RF amplifier;

20S: a secondary RF amplifier;

30. 31, 32, 33: an output matching circuit;

40: a control circuit;

51. 51S: a bias circuit;

52: a drive voltage circuit;

60. 61, 62, 63: an input matching circuit;

71. 72: a switching circuit;

101: a signal transmission line;

111. 112, 112: an inductor;

113. 114, 116: a capacitor;

115: a resistance;

121. 122: a detection circuit;

131. 132: a logarithmic converter;

133: an adder-subtractor;

134. 135, and (3) adding: an amplifier;

201：FET；

202: an input capacitance;

203: a bias resistor;

204: a coil;

ZLD: and (4) loading.

Detailed Description

(first embodiment)

A load detection circuit and an amplifier circuit according to a first embodiment of the present invention will be described with reference to the drawings.

(load detection circuit)

Fig. 1 is an equivalent circuit diagram of a load detection circuit of the first embodiment. As shown in fig. 1, the load detection circuit 10 is connected between the RF amplifier 20 and the output matching circuit 30. That is, the output terminal of the RF amplifier 20 is connected to the load detection circuit 10, and the load detection circuit 10 is connected to the output matching circuit 30. The output matching circuit 30 is connected to the load ZLD. Hereinafter, the impedance of the load ZLD side as viewed from the RF amplifier 20 is referred to as a load impedance.

The load ZLD is for example an antenna for RF signals. Note that the load ZLD is not limited to an antenna. The RF amplifier 20, the load detection circuit 10, and the output matching circuit 30 are realized by, for example, an insulating substrate on which a conductor pattern is formed, a semiconductor element mounted on the insulating substrate, a chip-type electronic component, a passive element formed on the insulating substrate, and the like.

The load detection circuit 10 includes a detection unit 11, a detection unit 12, and an arithmetic unit 13. The detection unit 11 includes an inductor 111, an inductor 112, a capacitor 113, a capacitor 114, and a resistor 115.

Inductor 111 is inductively coupled with inductor 112 such that a mutual inductance M is generated. The inductors 111 and 112 are realized by, for example, a transformer formed on a conductor pattern of an insulating substrate. The inductor 111 and the inductor 112 realize a "second detection unit" according to the present invention. Note that the formation structure of the inductor 111 and the inductor 112 is not limited to this. For example, when the substrate is formed of a semiconductor substrate, the inductor 111 and the inductor 112 can be implemented by a chip-type transformer.

The inductor 111 is connected between the output of the RF amplifier 20 and the output matching circuit 30. In other words, one end of the inductor 111 is connected to the output end of the RF amplifier 20 via the RF amplifier 20 side portion of the RF signal transmission line 101. The other end of the inductor 111 is connected to the output matching circuit 30 via a portion of the RF signal transmission line 101 on the output matching circuit 30 side.

One end of the inductor 112 is connected to the detector 12. The other end of the inductor 112 is connected to a reference potential.

With such a configuration, the portion (second detection unit) including the inductor 111 and the inductor 112 outputs the second detection signal from the signal transmission line 101 to the detection unit 12 by inductive coupling. The second detection signal reflects the current amplitude of the RF signal output from the RF amplifier 20.

One end of the capacitor 113 is connected to a portion of the signal transmission line 101 that connects the output end of the RF amplifier 20 and the inductor 111. One end of the capacitor 114 is connected to a portion of the signal transmission line 101 that connects the inductor 111 and the output matching circuit 30. The other end of the capacitor 113 is connected to the other end of the capacitor 114, and the other ends thereof are connected to the detector 12 and to the reference potential via the resistor 115.

The capacitor 113 and the capacitor 114 are each realized by, for example, a conductor pattern formed on an insulating substrate. Note that the formation structure of the capacitor 113 and the capacitor 114 is not limited to this. For example, when the substrate is formed of a semiconductor substrate, the capacitor 113 and the capacitor 114 can be realized by a chip-type capacitor, and more specifically, can be realized by an MIM capacitor. The capacitor 113 and the capacitor 114 realize a "first detection unit" according to the present invention.

With such a configuration, the portion (first detection section) including the capacitor 113 and the capacitor 114 outputs the first detection signal from the signal transmission line 101 to the detection section 12 by capacitive coupling. The first detection signal reflects the voltage amplitude of the RF signal output from the RF amplifier 20.

The length of the line connecting the capacitor 113 and the capacitor 114 is preferably sufficiently shorter than the wavelength of the RF signal (the wavelength of the first detection signal). Thereby, the phase difference between the first detection signal output from the capacitor 113 and the first detection signal output from the capacitor 114 can be reduced. Therefore, the characteristics of the first detection signal input to the detector 12 can reflect the characteristics of the RF signal with higher accuracy. The detection unit (first detection unit) may be only one of the capacitor 113 and the capacitor 114, or may be configured by 3 or more capacitors. This may be set as appropriate according to the desired size of the capacitive coupling. For example, the capacitance and the number of capacitors may be set so that the magnitude of the inductive coupling in the second detection unit with respect to the RF signal is equal to the magnitude of the capacitive coupling in the first detection unit.

The resistor 115 functions as a terminating element for capacitive coupling. The resistor 115 can be replaced with another impedance terminating element.

The detector unit 12 includes a detector circuit 121 and a detector circuit 122. The detector circuit 122 is connected to the inductor 112. The detector circuit 121 is connected to the capacitor 113 and the capacitor 114. Thereby, the first detection signal is input to the detector circuit 121. The second detection signal is input to the detector circuit 122.

The detector circuits 121 and 122 are, for example, circuits for performing envelope detection. The detector circuit 121 detects the first detection signal and outputs a first detection signal. The detector circuit 122 detects the second detection signal and outputs a second detection signal.

The arithmetic unit 13 includes a logarithmic converter 131, a logarithmic converter 132, an adder-subtractor 133, an amplifier 134, and an amplifier 135. The logarithmic converters 131 and 132 are connected to the input terminals of the adder-subtractor 133, and the output terminals of the adder-subtractor 133 are connected to the amplifiers 134 and 135.

The logarithmic converter 131 is connected to the detector circuit 121. The logarithmic converter 131 logarithmically converts the amplitude of the first detection signal to generate a first logarithmic signal. The logarithmic converter 131 outputs the first logarithmic signal to the adder-subtractor 133. The logarithmic converter 132 is connected to the detector circuit 122. The logarithmic converter 132 logarithmically converts the amplitude of the second detection signal to generate a second logarithmic signal. The logarithmic converter 132 outputs the second logarithmic signal to the adder-subtractor 133.

The adder-subtractor 133 subtracts the second logarithmic signal and the first logarithmic signal. In the present embodiment, more specifically, the adder-subtractor 133 subtracts the first logarithmic signal from the second logarithmic signal. The adder-subtractor 133 may subtract the second logarithmic signal from the first logarithmic signal. As described above, the first detection signal serving as the first logarithmic signal source reflects the voltage amplitude of the RF signal, and the second detection signal serving as the second logarithmic signal source reflects the current amplitude of the RF signal. Therefore, the signal obtained by subtracting the first logarithmic signal from the second logarithmic signal reflects the load impedance for the RF signal. That is, a signal obtained by subtracting the first logarithmic signal from the second logarithmic signal is the load impedance detection signal Sz.

The adder-subtractor 133 outputs a load impedance detection signal Sz to the amplifier 134. The amplifier 134 amplifies and outputs the load impedance detection signal Sz at a predetermined amplification factor. The amplifier 134 can be omitted.

The adder-subtractor 133 adds the first logarithmic signal and the second logarithmic signal. As described above, the first detection signal serving as the first logarithmic signal source reflects the voltage amplitude of the RF signal, and the second detection signal serving as the second logarithmic signal source reflects the current amplitude of the RF signal. Therefore, a signal obtained by adding the second logarithmic signal and the first logarithmic signal reflects the power of the RF signal. That is, a signal obtained by adding the second logarithmic signal and the first logarithmic signal is the power detection signal Sp.

The adder-subtractor 133 outputs a power detection signal Sp to the amplifier 135. The amplifier 135 amplifies and outputs the power detection signal Sp at a predetermined amplification factor. The amplifier 135 can be omitted.

In this way, the load impedance detection signal Sz is generated using the voltage amplitude and the current amplitude of the detected RF signal, and therefore, the load impedance is reflected with high accuracy. Therefore, the load detection circuit 10 can detect the load impedance with high accuracy. Similarly, the power detection signal Sp is generated using the voltage amplitude and the current amplitude of the detected RF signal, and therefore, the power of the RF signal is reflected with high accuracy. Therefore, the load detection circuit 10 can detect the output power of the RF signal with high accuracy.

In addition, for example, in the case where the directional coupler is used for detecting the load impedance without using the configuration of the present invention, the load impedance detection signal cannot be directly detected. Therefore, when the directional coupler is used, it is only possible to indirectly detect the load impedance by detecting whether or not the overload state is achieved based on the power detection signal output from the directional coupler.

On the other hand, according to the load detection circuit of the present invention, the load impedance detection signal can be directly detected separately from the power detection signal. Therefore, the load impedance can be detected with higher accuracy than the case of detecting the load impedance using the directional coupler.

The load detection circuit 10 includes a logarithmic converter 131 and a logarithmic converter 132. Thus, the load detection circuit 10 can generate the load impedance detection signal Sz by a simple subtraction method using a circuit configuration such as division and a programmatically complicated configuration without using a circuit configuration such as division. Further, by using the logarithmic converter 131 and the logarithmic converter 132, the load detection circuit 10 can determine a more quantitative amount and generate the load impedance detection signal Sz with higher accuracy.

Further, the load detection circuit 10 can convert the signal for generating the load impedance detection signal Sz into a signal closer to direct current by using the detector circuit 121 and the detector circuit 122. In addition, noise of a signal for generating the load impedance detection signal Sz can be suppressed. Thus, the load detection circuit 10 can generate the load impedance detection signal Sz more stably and with higher accuracy.

The load detection circuit 10 generates the power detection signal Sp together with the load impedance detection signal Sz. However, if only the load impedance detection signal Sz is generated, the load detection circuit 10 may include a subtractor instead of the adder-subtractor 133. However, by generating the power detection signal Sp, the control unit described later can more appropriately execute various controls.

The load detection circuit 10 having such a configuration is used for an amplifier circuit as shown below, for example.

(amplifying Circuit)

Fig. 2 is an equivalent circuit diagram of the amplifier circuit of the first embodiment. As shown in fig. 2, the amplifier circuit 1 includes a load detection circuit 10, an RF amplifier 20, an output matching circuit 30, and a control circuit 40. As described above, the load detection circuit 10, the RF amplifier 20, and the output matching circuit 30 are not specifically described.

The control circuit 40 is realized by an IC, a microcomputer, or the like. The control circuit 40 is connected to the load detection circuit 10 and the output matching circuit 30. The load impedance detection signal Sz and the power detection signal Sp are input from the load detection circuit 10 to the control circuit 40. At least the load impedance detection signal Sz may be input to the control circuit 40.

The control circuit 40 controls the impedance of the output matching circuit 30 using the load impedance detection signal Sz. For example, the control circuit 40 acquires the load impedance detection signal Sz at predetermined sampling intervals, and detects a variation in load impedance. The control circuit 40 adjusts the impedance of the output matching circuit 30 in accordance with the variation of the load impedance. This enables the amplifier circuit 1 to compensate for the variation in load impedance with high accuracy.

This stabilizes the impedance matching between RF amplifier 20 and load ZLD, and suppresses, for example, the characteristic degradation of the amplifier. Here, the amplifier characteristics include, for example, distortion characteristics, EVM (Error Vector Magnitude), efficiency, saturation power, and the like.

In this configuration, since the impedance is adjusted by the output matching circuit 30, the amplifier circuit 1 can directly compensate for the load impedance.

(second embodiment)

Fig. 3 is an equivalent circuit diagram of an amplifier circuit of the second embodiment. As shown in fig. 3, the amplifier circuit 1A according to the second embodiment is different from the amplifier circuit 1 according to the first embodiment in the control target controlled by the control circuit 40. The other configurations of the amplifier circuit 1A are the same as those of the amplifier circuit 1, and descriptions of the same parts are omitted.

The amplifier circuit 1A includes a bias circuit 51 and a drive voltage circuit 52. As shown in fig. 3, the RF amplifier 20 includes, for example, an FET201, an input capacitor 202, a bias resistor 203, and a coil 204. The source of the FET201 is grounded. The gate of the FET201 is connected to an input terminal of an RF signal via an input capacitor 202. The gate of the FET201 is connected to the bias circuit 51 via a bias resistor 203. The drain of the FET201 is connected to the drive voltage circuit 52 via the coil 204. Further, the drain of the FET201 is connected to the load detection circuit 10 through the output terminal of the RF amplifier 20.

The bias circuit 51 generates a bias voltage. The bias circuit 51 supplies a bias voltage to the gate of the FET201 via the bias resistor 203. The drive voltage circuit 52 generates a drive voltage. The driving voltage circuit 52 supplies a driving voltage to the drain of the FET201 via the coil 204.

The control circuit 40 controls the bias circuit 51 using the load impedance detection signal Sz. In other words, the control circuit 40 adjusts the bias voltage for the RF amplifier 20 using the load impedance detection signal Sz. The amplifier circuit 1A can adjust the characteristics of the RF amplifier 20 by adjusting the bias voltage, and can indirectly adjust the load impedance. That is, the amplifier circuit 1A can indirectly compensate for the load impedance.

(third embodiment)

Fig. 4 is an equivalent circuit diagram of the amplifying circuit of the third embodiment. As shown in fig. 4, the amplifier circuit 1B according to the third embodiment is different from the amplifier circuit 1A according to the second embodiment in the control target of the control circuit 40. The other configurations of the amplifier circuit 1B are the same as those of the amplifier circuit 1A, and descriptions of the same parts are omitted.

The control circuit 40 controls the drive voltage circuit 52 using the load impedance detection signal Sz. In other words, the control circuit 40 adjusts the drive voltage for the RF amplifier 20 using the load impedance detection signal Sz. The amplifier circuit 1B can adjust the characteristics of the RF amplifier 20 by adjusting the driving voltage, and can indirectly adjust the load impedance. That is, the amplifier circuit 1B can indirectly compensate for the load impedance.

(fourth embodiment)

Fig. 5 is an equivalent circuit diagram of an amplifier circuit of the fourth embodiment. As shown in fig. 5, the amplifier circuit 1C of the fourth embodiment is different from the amplifier circuit 1 of the first embodiment in that it includes the sub RF amplifier 20S, in that it is a circuit change point caused by the sub RF amplifier 20S, and in that it is an object to be controlled by the control circuit 40. The other configurations of the amplifier circuit 1C are the same as those of the amplifier circuit 1, and the description of the same parts is omitted.

The amplifier circuit 1C includes a sub RF amplifier 20S, a bias circuit 51S, and an input matching circuit 60.

The input matching circuit 60 is connected between the input terminal of the RF amplifier 20 and the input terminal of the RF signal of the amplifying circuit 1C.

The input terminal of the sub RF amplifier 20S is connected to the input matching circuit 60, and the output terminal of the sub RF amplifier 20S is connected to the output matching circuit 30. In other words, the sub RF amplifier 20S is connected in parallel with the RF amplifier 20.

The bias circuit 51S supplies a bias voltage to the sub RF amplifier 20S.

The control circuit 40 controls the bias circuit 51S using the load impedance detection signal Sz. In other words, the control circuit 40 adjusts the bias voltage for the sub RF amplifier 20S using the load impedance detection signal Sz. Amplifier circuit 1C can adjust the characteristics of sub RF amplifier 20S by adjusting the bias voltage of sub RF amplifier 20S. In the amplifying circuit 1C, the load impedance depends on the characteristics of the RF amplifier 20 and the characteristics of the sub-RF amplifier 20S. Therefore, the amplifier circuit 1C can indirectly adjust the load impedance. That is, the amplifier circuit 1C can indirectly compensate for the load impedance.

In this configuration, the bias voltage and the driving voltage of the RF amplifier 20, which is a main amplifier, may not be changed.

In the present embodiment, although the bias voltage of the sub RF amplifier 20S is adjusted, the driving voltage can be adjusted.

(fifth embodiment)

Fig. 6 is an equivalent circuit diagram of an amplifier circuit of the fifth embodiment. As shown in fig. 6, an amplifier circuit 1D according to the fifth embodiment is different from the amplifier circuit 1C according to the fourth embodiment in the control target of the control circuit 40. The other configurations of the amplifier circuit 1D are the same as those of the amplifier circuit 1C, and descriptions of the same parts are omitted.

The control circuit 40 controls at least one of the impedance of the output matching circuit 30 and the impedance of the input matching circuit 60 using the load impedance detection signal Sz. In such a configuration and process, the amplifier circuit 1D can adjust and compensate the load impedance. The amplifier circuit 1D may not necessarily include the input matching circuit 60 together with the sub RF amplifier 20S, and may include only the input matching circuit 60.

(sixth embodiment)

Fig. 7 is an equivalent circuit diagram of an amplifier circuit according to the sixth embodiment. As shown in fig. 7, an amplifier circuit 1E according to the sixth embodiment is different from the amplifier circuit 1 according to the first embodiment in that the order of connection between the output matching circuit 30 and the load detection circuit 10 is reversed. The other configurations of the amplifier circuit 1E are the same as those of the amplifier circuit 1, and the description of the same parts is omitted.

In the amplifier circuit 1E, an output matching circuit 30 is connected to an output terminal of the RF amplifier 20, and the output matching circuit 30 is connected to a load ZLD via the load detection circuit 10.

Even with such a configuration, the amplifier circuit 1E can adjust and compensate the load impedance. In this configuration, the impedance of the portion to which the load detection circuit 10 is connected is higher than the impedance of the output terminal of the RF amplifier 20. This makes it easy to reduce the loss in the load detection circuit 10.

(seventh embodiment)

Fig. 8 is an equivalent circuit diagram of an amplifier circuit of the seventh embodiment. As shown in fig. 8, the amplifier circuit 1F according to the seventh embodiment is different from the amplifier circuit 1E according to the sixth embodiment in the control target of the control circuit 40. The other configurations of the amplifier circuit 1F are the same as those of the amplifier circuit 1E, and descriptions of the same parts are omitted.

In the amplifier circuit 1F, the control circuit 40 controls the bias circuit 51 for the RF amplifier 20 using the load impedance detection signal Sz. Even with such a configuration, the amplifier circuit 1F can adjust and compensate the load impedance.

(eighth embodiment)

Fig. 9 is an equivalent circuit diagram of an amplifier circuit according to the eighth embodiment. As shown in fig. 9, an amplifier circuit 1G according to the eighth embodiment is different from the amplifier circuit 1E according to the sixth embodiment in that it has an amplification system for a plurality of RF signals. The other configurations of the amplifier circuit 1G are the same as those of the amplifier circuit 1E, and the description of the same parts is omitted.

The amplifier circuit 1G includes a load detection circuit 10, a control circuit 40, a plurality of RF amplifiers (RF amplifier 21, RF amplifier 22, and RF amplifier 23), a plurality of output matching circuits (output matching circuit 31, output matching circuit 32, and output matching circuit 33), a plurality of input matching circuits (input matching circuit 61, input matching circuit 62, and input matching circuit 63), a switch circuit 71, and a switch circuit 72.

The input terminal of the RF signal of the amplifier circuit 1G is connected to the switch circuit 71. The switch circuit 71 is connected to the input matching circuit 61, the input matching circuit 62, and the input matching circuit 63. The switch circuit 71 selects one of the input matching circuit 61, the input matching circuit 62, and the input matching circuit 63 and is connected to an input terminal of an RF signal.

The input matching circuit 61 is connected to an input terminal of the RF amplifier 21. The output of the RF amplifier 21 is connected to an output matching circuit 31. The input matching circuit 62 is connected to the input of the RF amplifier 22. The output of the RF amplifier 22 is connected to an output matching circuit 32. The input matching circuit 63 is connected to the input of the RF amplifier 23. The output of the RF amplifier 23 is connected to an output matching circuit 33.

The output matching circuit 31, the output matching circuit 32, and the output matching circuit 33 are connected to the switch circuit 72. The switch circuit 72 is connected to the load detection circuit 10. The switch circuit 72 selects one of the output matching circuit 31, the output matching circuit 32, and the output matching circuit 33 and is connected to the load detection circuit 10.

The connection switching of the switch circuit 71 is performed in synchronization with the connection switching of the switch circuit 72. That is, when the switch circuit 71 selects the input matching circuit 61, the switch circuit 72 selects the output matching circuit 31. Similarly, when the switch circuit 71 selects the input matching circuit 62, the switch circuit 72 selects the output matching circuit 32, and when the switch circuit 71 selects the input matching circuit 63, the switch circuit 72 selects the output matching circuit 33.

The control circuit 40 controls the impedances of the output matching circuit 31, the output matching circuit 32, and the output matching circuit 33. More specifically, when the input matching circuit 61, the RF amplifier 21, and the output matching circuit 31 are selected to amplify the first RF signal, the control circuit 40 controls the impedance of the output matching circuit 31. Similarly, when the input matching circuit 62, the RF amplifier 22, and the output matching circuit 32 are selected to amplify the second RF signal, the control circuit 40 controls the impedance of the output matching circuit 32. When the input matching circuit 63, the RF amplifier 23, and the output matching circuit 33 are selected to amplify the third RF signal, the control circuit 40 controls the impedance of the output matching circuit 33.

With this configuration, the amplifier circuit 1G can amplify a plurality of kinds of RF signals and can compensate load impedance for each RF signal. For example, even if a plurality of RF signals are provided in a frequency band that cannot be handled by one RF amplifier, the amplifier circuit 1G can switch the RF amplifiers for each RF signal and compensate for the load impedance of each RF amplifier. In this configuration, the load detection circuit 10 does not have to be provided for each RF amplifier, and the circuit configuration of the amplifier circuit 1G can be simplified.

In addition, the control targets of the control circuit 40 in the above embodiments can be combined. For example, the control circuit 40 can also control the bias circuit and the drive voltage circuit. In addition, for example, the control circuit 40 can also control the bias circuit and the output matching circuit 30.

(ninth embodiment)

Fig. 10 is an equivalent circuit diagram of a load detection circuit of the ninth embodiment. As shown in fig. 10, the load detection circuit 10H of the ninth embodiment is different from the load detection circuit 10 of the first embodiment in the configuration of the detection unit 11H and the signal output therefrom. The other configurations of the load detection circuit 10H are the same as those of the load detection circuit 10, and descriptions of the same parts are omitted.

The load detection circuit 10H includes a detection unit 11H. The detection unit 11H includes an inductor 111, an inductor 112, a capacitor 113, a capacitor 114, and a capacitor 116.

Inductor 111 is inductively coupled with inductor 112 such that a mutual inductance M is generated. The inductor 111 is connected between the output of the RF amplifier 20 and the output matching circuit 30.

One end of the capacitor 113 and one end of the capacitor 114 are connected to the signal transmission line 101, respectively. The other end of the capacitor 113 is connected to the other end of the capacitor 114, and a node at the other ends thereof is connected to the reference potential via a capacitor 116.

A node between the other end of the capacitor 113 and the other end of the capacitor 114 is connected to the inductor 112.

The end E1 of the inductor 112 on the load ZLD side is connected to the detector circuit 121 of the detector 12. The first signal is output from the end E1 of the inductor 112. The end E1 on the load ZLD side of the inductor 112 is an end of a portion of the inductor 111 on the side connected to the load ZLD (on the side connected to the output matching circuit 30) where the inductor 112 is inductively coupled to the load ZLD.

The end E2 of the inductor 112 on the RF amplifier 20 side is connected to the detector circuit 122 of the detector unit 12. The second signal is output from end E2 of inductor 112. The end E2 of the inductor 112 on the RF amplifier 20 side is an end of a portion of the inductor 111 on the side connected to the RF amplifier 20, which is inductively coupled to the inductor 112.

In this configuration, a connection portion (node) between the inductor 112 and the capacitors 113 and 114 is connected to a reference potential via the capacitor 116. Therefore, in the signal transmission line 101, the phase difference between the voltage and the current is 90 degrees, but the phase difference between the voltage of the first signal and the voltage of the second signal is 180 degrees.

The first signal and the second signal are signals obtained by superimposing the signal detected by the inductor 112 and the signals detected by the capacitors 113 and 114. Thus, the first signal and the second signal depend on the magnitude and sign of the reactive component of the load impedance.

Therefore, a signal obtained by subtracting the first signal and the second signal output from the adder-subtractor 133 becomes the reactance detection signal Szr of the load impedance. Thus, the load detection circuit 10H can detect the reactance component of the load impedance with higher accuracy.

The configurations of the above embodiments can be combined as appropriate, and the respective combinations can provide operational effects.