阅读说明：本技术 信息隐藏方法、装置及计算机存储介质 (Information hiding method and device and computer storage medium ) 是由 杨磊 张何钫 于 2021-08-27 设计创作，主要内容包括：本发明公开了一种信息隐藏方法、装置及计算机存储介质,涉及图像处理技术领域,解决了图像的抗隐藏分析能力较差的技术问题。该信息隐藏方法包括：获取第一图像和第二图像；确定第一图像的M个第一位平面,并对M个第一位平面进行亚仿射变换置乱,得到M个第二位平面,第一图像的同一图像通道中的第一位平面的噪声低于同一图像通道中的其它位平面的噪声；确定第二图像的N个位平面,并将N个位平面嵌入M个第二位平面中,得到M个第三位平面,一个N个位平面中的位平面对应嵌入一个第二位平面中；对M个第三位平面进行亚仿射周期还原,得到隐藏了N个位平面的第三图像；其中,M、N为正整数,且M大于或等于N。(The invention discloses an information hiding method and device and a computer storage medium, relates to the technical field of image processing, and solves the technical problem of poor anti-hiding analysis capability of an image. The information hiding method comprises the following steps: acquiring a first image and a second image; determining M first bit planes of a first image, and performing sub-affine transformation scrambling on the M first bit planes to obtain M second bit planes, wherein the noise of the first bit planes in the same image channel of the first image is lower than the noise of other bit planes in the same image channel; determining N bit planes of a second image, embedding the N bit planes into M second bit planes to obtain M third bit planes, and correspondingly embedding a bit plane in the N bit planes into one second bit plane; carrying out sub-affine periodic reduction on the M third bitplanes to obtain a third image hiding the N bitplanes; wherein M, N is a positive integer, and M is greater than or equal to N.)

1. An information hiding method, comprising:

acquiring a first image and a second image;

determining M first bit planes of the first image, and performing sub-affine transformation scrambling on the M first bit planes to obtain M second bit planes, wherein the noise of the first bit planes in the same image channel of the first image is lower than the noise of other bit planes in the same image channel;

determining N bit planes of the second image, and embedding the N bit planes into the M second bit planes to obtain M third bit planes, wherein one bit plane in the N bit planes is correspondingly embedded into one second bit plane;

performing sub-affine periodic reduction on the M third bitplanes to obtain a third image hiding the N bitplanes;

wherein M, N is a positive integer, and M is greater than or equal to N.

2. The information hiding method of claim 1, wherein the first image comprises 4 image channels, each image channel comprising 8 bit planes; the determining M first bit planes of the first image and performing sub-affine transformation scrambling on the M first bit planes to obtain M second bit planes includes:

sequentially carrying out first operation on 4 image channels of the first image to obtain 8 first bit planes;

carrying out sub-affine transformation scrambling on the 8 first bitplanes to obtain 8 second bitplanes;

the first operation includes: sequencing 8 bit planes in a target image channel according to the sequence of bit plane noise from small to large; determining the first two bit planes as a first bit plane of the target image channel, the target image channel being any one of 4 image channels of the first image.

3. The information hiding method according to claim 2, wherein the second image includes 1 image channel; said embedding said N bit-planes into said M second bit-planes comprising: embedding 8 bit planes of the second image into the 8 second bit planes in a one-to-one correspondence.

4. The information hiding method as claimed in claim 1, wherein the method further comprises:

acquiring the third image;

determining a bit plane containing embedded information in the bit plane of the third image, and performing sub-affine transformation scrambling on the bit plane containing the embedded information;

and extracting data of the N bit planes from the bit planes subjected to the sub-affine transformation scrambling by comparing the M second bit planes.

5. The information hiding method according to any one of claims 1 to 4, wherein the method further comprises:

determining the anti-steganalysis capability of the third image according to a preset analysis method, wherein the preset analysis method comprises at least one of a histogram intersection distance formula analysis method, a cosine function formula analysis method, a regular and singular group RS analysis method and a frequency histogram analysis method.

6. An information hiding apparatus, comprising: an acquisition unit and a processing unit;

the acquisition unit is used for acquiring a first image and a second image;

the processing unit is configured to determine M first bit planes of the first image, perform sub-affine transformation scrambling on the M first bit planes, and obtain M second bit planes, where noise of the first bit planes in the same image channel of the first image is lower than noise of other bit planes in the same image channel; determining N bit planes of the second image, and embedding the N bit planes into the M second bit planes to obtain M third bit planes, wherein one bit plane in the N bit planes is correspondingly embedded into one second bit plane; performing sub-affine periodic reduction on the M third bitplanes to obtain a third image hiding the N bitplanes;

wherein M, N is a positive integer, and M is greater than or equal to N.

7. The hidden-information hiding apparatus as claimed in claim 6, wherein the first image comprises 4 image channels, each image channel comprising 8 bit planes; the processing unit is configured to:

sequentially carrying out first operation on 4 image channels of the first image to obtain 8 first bit planes; carrying out sub-affine transformation scrambling on the 8 first bitplanes to obtain 8 second bitplanes; the first operation includes: sequencing 8 bit planes in a target image channel according to the sequence of bit plane noise from small to large; determining the first two bit planes as a first bit plane of the target image channel, the target image channel being any one of 4 image channels of the first image.

8. The information hiding apparatus as claimed in claim 7, wherein the second image includes 1 image channel; the processing unit is specifically configured to: embedding 8 bit planes of the second image into the 8 second bit planes in a one-to-one correspondence.

9. An information hiding apparatus, comprising a memory and a processor; the memory is used for storing computer execution instructions, and the processor is connected with the memory through a bus;

when the information hiding device is operated, the processor executes the computer-executable instructions stored in the memory to cause the information hiding device to perform the information hiding method according to any one of claims 1 to 5.

10. A computer-readable storage medium, comprising computer-executable instructions that, when executed on a computer, cause the computer to perform the information hiding method of any one of claims 1-5.

Technical Field

The present invention relates to the field of image processing technologies, and in particular, to an information hiding method and apparatus, and a computer storage medium.

Background

The information hiding means that secret information is embedded into a carrier by utilizing human perception and the self redundancy of the digital media so as to track the use of the carrier, thereby achieving the purposes of copyright protection, integrity authentication and the like.

The information hiding algorithms in the prior art mainly include a spatial domain replacement method, that is, a redundant part in a carrier is directly replaced by secret information, for example, a bit plane algorithm. Although such an algorithm has the advantages of easy implementation, low computational complexity, etc., it is easy to identify because of its simple implementation.

Accordingly, those skilled in the art have made efforts to develop an information hiding method, apparatus, and computer storage medium that can improve the anti-hiding analysis capability of an image.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, the technical problems to be solved by the present invention are: how to improve the anti-hiding analysis capability of the image.

In order to achieve the purpose, the invention adopts the following technical scheme:

in a first aspect, the present invention provides an information hiding method, including: acquiring a first image and a second image; determining M first bit planes of a first image, and performing sub-affine transformation scrambling on the M first bit planes to obtain M second bit planes, wherein the noise of the first bit planes in the same image channel of the first image is lower than the noise of other bit planes in the same image channel; determining N bit planes of a second image, embedding the N bit planes into M second bit planes to obtain M third bit planes, and correspondingly embedding a bit plane in the N bit planes into one second bit plane; carrying out sub-affine periodic reduction on the M third bitplanes to obtain a third image hiding the N bitplanes; wherein M, N is a positive integer, and M is greater than or equal to N.

In the embodiment of the invention, a first image and a second image can be acquired; determining M first bit planes of a first image, and performing sub-affine transformation scrambling on the M first bit planes to obtain M second bit planes, wherein the noise of the first bit planes in the same image channel of the first image is lower than the noise of other bit planes in the same image channel; determining N bit planes of a second image, embedding the N bit planes into M second bit planes to obtain M third bit planes, and correspondingly embedding a bit plane in the N bit planes into one second bit plane; carrying out sub-affine periodic reduction on the M third bitplanes to obtain a third image hiding the N bitplanes; wherein M, N is a positive integer, and M is greater than or equal to N. By the scheme, because sub-affine transformation and bit plane information hiding can be combined, and N bit planes of the second image are hidden into M first bit planes of the first image, the difference between the first image and the third image is extremely small visually, and the anti-hiding analysis capability of the third image can be improved.

In a preferred embodiment of the present invention, the first image comprises 4 image channels, each image channel comprising 8 bit planes; the determining M first bit planes of the first image and performing sub-affine transformation scrambling on the M first bit planes to obtain M second bit planes includes: sequentially carrying out first operation on 4 image channels of the first image to obtain 8 first bit planes; performing sub-affine transformation scrambling on the 8 first bitplanes for preset times to obtain 8 second bitplanes; the first operation includes: sequencing 8 bit planes in a target image channel according to the sequence of bit plane noise from small to large; determining the first two bit planes as a first bit plane of the target image channel, the target image channel being any one of 4 image channels of the first image.

In a preferred embodiment of the present invention, the second image comprises 1 image channel; said embedding said N bit-planes into said M second bit-planes comprising: embedding 8 bit planes of the second image into the 8 second bit planes in a one-to-one correspondence.

In the embodiment of the present invention, the second image includes 1 image channel, and 8 second bit planes can be obtained from the first image, so that the 8 bit planes of the second image can be embedded into the 8 second bit planes in a one-to-one correspondence manner, that is, the second image is hidden in the first image, thereby not only ensuring the anti-hiding analysis capability of the image, but also hiding the complete image in another image, thereby improving the information hiding capacity of the first image.

In a preferred embodiment of the present invention, the method further comprises: acquiring the third image; determining a bit plane containing embedded information in the bit plane of the third image, and performing sub-affine transformation scrambling on the bit plane containing the embedded information; and extracting data of the N bit planes from the bit planes subjected to the sub-affine transformation scrambling by comparing the M second bit planes.

In the embodiment of the invention, because the data of the hidden N bit planes can be restored from the third image, the information hidden in the image can be restored, thereby realizing the secret protection of the hidden information.

In a preferred embodiment of the present invention, the method further comprises: determining the anti-steganalysis capability of the third image according to a preset analysis method, wherein the preset analysis method comprises at least one of a histogram intersection distance formula analysis method, a cosine function formula analysis method, a regular and singular group RS analysis method and a frequency histogram analysis method.

In the embodiment of the invention, because the anti-steganalysis capability of the third image can be determined by the preset analysis method, the use effect of the information hiding method provided by the application can be evaluated, and theoretical guarantee is provided for the practical application of the information hiding method.

In a second aspect, the present invention provides an information hiding apparatus, including: an acquisition unit and a processing unit; the acquisition unit is used for acquiring a first image and a second image; the processing unit is configured to determine M first bit planes of the first image, perform sub-affine transformation scrambling on the M first bit planes, and obtain M second bit planes, where noise of the first bit planes in the same image channel of the first image is lower than noise of other bit planes in the same image channel; determining N bit planes of the second image, and embedding the N bit planes into the M second bit planes to obtain M third bit planes, wherein one bit plane in the N bit planes is correspondingly embedded into one second bit plane; performing sub-affine periodic reduction on the M third bitplanes to obtain a third image hiding the N bitplanes; wherein M, N is a positive integer, and M is greater than or equal to N.

In a preferred embodiment of the invention, the first image comprises 4 image channels, each image channel comprising 8 bit planes; the processing unit is specifically configured to: sequentially carrying out first operation on 4 image channels of the first image to obtain 8 first bit planes; carrying out sub-affine transformation scrambling on the 8 first bitplanes to obtain 8 second bitplanes; the first operation includes: sequencing 8 bit planes in a target image channel according to the sequence of bit plane noise from small to large; determining the first two bit planes as a first bit plane of the target image channel, the target image channel being any one of 4 image channels of the first image.

In a preferred embodiment of the invention, the second image comprises 1 image channel; the processing unit is specifically configured to: embedding 8 bit planes of the second image into the 8 second bit planes in a one-to-one correspondence.

In a preferred embodiment of the present invention, the acquiring unit is further configured to acquire the third image; the processing unit is further configured to determine a bit plane containing embedded information in a bit plane of the third image, and perform sub-affine transform scrambling on the bit plane containing embedded information; and extracting data of the N bit planes from the bit planes subjected to the sub-affine transformation scrambling by comparing the M second bit planes.

In a preferred embodiment of the present invention, the processing unit is further configured to determine the anti-steganalysis capability of the third image according to a predetermined analysis method, where the predetermined analysis method includes at least one of a histogram intersection distance formula analysis method, a cosine function formula analysis method, a regular and singular group RS analysis method, and a frequency histogram analysis method.

In a third aspect, the present invention provides an information hiding apparatus, comprising a memory and a processor. The memory is used for storing computer execution instructions, and the processor is connected with the memory through a bus. When the information hiding device is running, the processor executes computer-executable instructions stored in the memory to make the information hiding device execute the information hiding method provided by the first aspect and various possible embodiments thereof.

In a fourth aspect, a computer-readable storage medium is provided, where the computer-readable storage medium includes computer-executable instructions, which, when executed on a computer, cause an information hiding apparatus to perform the information hiding method provided in the first aspect and various possible implementations thereof.

In a fifth aspect, a computer program product is provided, which comprises computer instructions that, when run on a computer, cause an information hiding apparatus to perform the information hiding method provided in the first aspect and its various possible implementations.

It should be noted that all or part of the computer instructions may be stored on the computer readable storage medium. The computer-readable storage medium may be packaged together with a processor executing the information hiding apparatus, or may be packaged separately from the processor executing the information hiding apparatus, which is not limited in this embodiment of the present invention.

For the description of the second, third, fourth and fifth aspects of the present invention, reference may be made to the detailed description of the first aspect; in addition, for the beneficial effects described in the second aspect, the third aspect, the fourth aspect and the fifth aspect, reference may be made to the beneficial effect analysis of the first aspect, and details are not repeated here.

The conception, the specific structure and the technical effects of the present invention will be further described with reference to the accompanying drawings to fully understand the objects, the features and the effects of the present invention.

Drawings

Fig. 1 is a flowchart illustrating an information hiding method according to a preferred embodiment of the present invention;

FIG. 2 is a schematic view of a Lena black-and-white image A image channel bit-plane according to an embodiment of the present invention;

FIG. 3 is a frequency histogram of a first image according to an embodiment of the present invention;

FIG. 4 is a frequency histogram of a third image according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of an information hiding apparatus according to an embodiment of the present invention;

fig. 6 is a second schematic structural diagram of an information hiding device according to an embodiment of the present invention.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.

It should be noted that, in the embodiments of the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary" or "e.g.," an embodiment of the present invention is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Further, it should be noted that the scope of the methods and apparatus of embodiments of the present invention is not limited to performing functions in the order illustrated or discussed, but may include performing functions in a substantially simultaneous manner or in a reverse order based on the functions involved, e.g., the methods described may be performed in an order different than that described, and various steps may be added, omitted, or combined. In addition, features described with reference to certain examples may be combined in other examples.

For the convenience of clearly describing the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, the words "first", "second", and the like are used for distinguishing the same items or similar items with basically the same functions and actions, and those skilled in the art can understand that the words "first", "second", and the like are not limited in number or execution order.

Some exemplary embodiments of the invention have been described for illustrative purposes, and it is to be understood that the invention may be practiced otherwise than as specifically described.

The above-described implementations are described in detail below with reference to specific embodiments and the accompanying drawings.

As shown in fig. 1, an embodiment of the present invention provides an information hiding method, which can be applied to an information hiding apparatus. The information hiding device can be a component, an integrated circuit or a chip in the terminal, can be a mobile electronic device such as a notebook computer, and can also be a non-mobile electronic device such as a server. The information hiding method may include: S101-S104:

s101, the information hiding device acquires a first image and a second image.

The first image may be a color image, and the second image may be a black-and-white image. The first image comprises 4 image channels, which are respectively an a (alph) image channel, an r (red) image channel, a g (green) image channel and a b (blue) image channel. The second image includes one image channel, the a image channel. Each image channel may include 8 bit planes.

The bit plane is a plane formed by bits having the same pixel position in a stereo histogram formed with an image as a bottom surface and an 8-bit binary number indicating the pixel brightness as a height.

Optionally, the information hiding device may obtain the first image first and then obtain the second image; the first image and the second image may also be obtained simultaneously, which may be determined according to actual use conditions, and this is not limited in the embodiment of the present application.

S102, the information hiding device determines M first bit planes of the first image, and sub-affine transformation scrambling is carried out on the M first bit planes to obtain M second bit planes.

The noise of the first bit plane in the same image channel of the first image is lower than the noise of other bit planes in the same image channel. M is a positive integer.

Optionally, the M first bit planes may include at least one bit plane of the same image channel, and may also include bit planes of different image channels. And the number of first bit-planes in an image channel may be the same or different.

For example, taking M as 8 and the number of first bit planes in one image channel is the same, the information hiding apparatus may perform a first operation on 4 image channels of the first image in sequence to obtain 8 first bit planes; and performing sub-affine transformation scrambling on the 8 first bitplanes to obtain 8 second bitplanes. The first operation includes: sequencing 8 bit planes in a target image channel according to the sequence of bit plane noise from small to large; the first two bit planes are determined as the first bit plane of the target image channel, which is any one of the 4 image channels of the first image.

As shown in fig. 2, the a image channel of the first image is a Lena black-and-white image as an example. Bit-planes 1-8 are included in the image, and it can be seen that of the 8 bit-planes, the later bit-planes have less visual impact on the Lena image, and thus bit-plane 7 and bit-plane 8 can be considered as the first bit-plane of the a-image channel. And then, scrambling all the first bit planes by sub-affine transformation to obtain second bit planes.

Optionally, the information hiding device may perform sub-affine transformation scrambling on the first bit plane for a preset number of times to obtain the second bit plane. The preset number may be greater than or equal to 20.

It should be noted that sub-affine transformation scrambling refers to the following formula:alternatively, equation 2:and transforming the coordinates of the pixel points of the image. And sub-affine transformation scrambling satisfies: the condition 1 is that the change is a single mapping from the discrete point domain { (x, y):1 ≦ x ≦ N, 1 ≦ y ≦ N } to itself; condition 2, change is a full mapping of the discrete point domain { (x, y):1 ≦ x ≦ N, 1 ≦ y ≦ N } to itself. Wherein x, y represent coordinate values before transformation, x ', y' represent coordinate values after transformation, and N represents orders a, b, c, d, e, f of the digital image. The method is a property of geometric change, after the given N-order digital image is subjected to the transformation for multiple times, each pixel point is scrambled and uniformly distributed in the image, and the original image can be restored after the times reach a certain period. In the embodiment of the present application, the solution of sub-affine transform scrambling may be determined as a-0, b-1, c-1, d-1, e-N +1, and f-1.

S103, the information hiding device determines N bit planes of the second image and embeds the N bit planes into M second bit planes to obtain M third bit planes.

And the bit plane of one of the N bit planes is correspondingly embedded into one second bit plane, namely, each bit plane of the N bit planes respectively corresponds to one second bit plane. N is a positive integer, and M is greater than or equal to N.

Optionally, the N bit planes may be bit planes of the second image, where noise is greater than that of the other bit planes. I.e. the noise of the N bit-planes is larger than the noise of the other bit-planes of the second image.

Optionally, N may be a preset number, or may be a value input by a user. In the case that N is the preset number, the information hiding apparatus may first determine noise of each bit plane of the second image, and then select the preset number of bit planes from the bit planes of the second image in an order of noise from large to small. In the case where N is a value input by the user, the information hiding means may first determine noise of each bit plane of the second image, then receive the value of N input by the user, and select N bit planes from among the bit planes of the second image in order of noise from large to small in response to the input.

In the case that M is equal to N, the information hiding means may embed N bit planes into M second bit planes in a one-to-one correspondence; when M is greater than N, the information hiding device may select N second bit planes from the M second bit planes, and then embed the N second bit planes in a one-to-one correspondence.

Illustratively, taking M and N as 8 as an example, the second image includes 8 bit planes, and the information hiding device may obtain 8 second bit planes through S102, so that the information hiding device may embed the 8 bit planes of the second image into the 8 second bit planes in a one-to-one correspondence manner as 0 and 1. Therefore, the anti-hiding analysis capability of the image can be ensured, and the complete image can be hidden in another image, so that the information hiding capacity of the first image is improved.

S104, performing sub-affine periodic reduction on the M third bit planes by the information hiding device to obtain a third image with the N hidden bit planes.

Specifically, by respectively restoring 8 third bit planes by sub-affine periods, a third image in which N bit planes of the second image are hidden can be synthesized, and the third image is hardly visually distinguished from the first image by human eyes.

Optionally, the information hiding method may further include: the information hiding device acquires a third image; determining a bit plane containing embedded information in the bit plane of the third image and the times of sub-affine transformation scrambling, namely the preset times, according to the user input, and then performing sub-affine transformation scrambling on the bit plane containing the embedded information for the preset times; and finally, extracting data of N bit planes from the bit planes subjected to sub-affine transformation scrambling by comparing the M second bit planes.

It should be noted that, when M, N are all 8 bits, the information hiding device may combine each 8 bits into one pixel point, and finally arrange all the combined pixels in order to obtain the second image. Since the data of the hidden N bit planes can be restored from the third image, the information hidden in the image can be restored, thereby achieving the secrecy protection of the hidden information.

Optionally, the information hiding method may further include: determining the anti-steganalysis capability of the third image according to a preset analysis method, wherein the preset analysis method comprises at least one of a histogram intersection distance formula analysis method, a cosine function formula analysis method, a regular and singular group RS analysis method and a frequency histogram analysis method. The anti-steganalysis capability of the third image can be determined through a preset analysis method, so that the using effect of the information hiding method provided by the application can be evaluated, and theoretical guarantee is provided for the practical application of the information hiding method.

(1) Formula analysis method for square-crossing distance

As shown in table 1, the results of the calculation of the histogram intersection distance formula of the Lena RGB image at different embedding rates are obtained by using the common bit plane algorithm; as shown in table 2, the calculated results of the histogram intersection distance formula of the Lena RGB image at different embedding rates are obtained by using the bit plane algorithm provided in the embodiment of the present application. It can be seen that, under the same embedding rate, the calculation result of the square intersection distance formula obtained by using the bit plane algorithm after sub-affine transformation scrambling is closer to 1 than the calculation result of the square intersection distance formula obtained by using the common bit plane algorithm, so that the bit plane algorithm provided by the embodiment of the application has stronger anti-hiding analysis capability.

TABLE 1

TABLE 2

(2) Cosine function formula analysis method

As shown in table 3, the calculation result is the cosine function formula of Lena RGB image calculated by using the common bit plane algorithm at different embedding rates; as shown in table 4, the calculated result of the cosine function formula of the Lena RGB image at different embedding rates is obtained by using the bit plane algorithm provided in the embodiment of the present application. It can be seen that, under the same embedding rate, the cosine function formula calculation result obtained by using the bit plane algorithm scrambled based on the sub-affine transformation is closer to 1 than the cosine function formula calculation result obtained by using the ordinary bit plane algorithm, so that the bit plane algorithm provided by the embodiment of the present application has stronger anti-hiding analysis capability.

TABLE 3

TABLE 4

(3) RS assay

As shown in table 5, the RS analysis results of Lena RGB images calculated by using the common bit plane algorithm at different embedding rates are shown; as shown in table 6, the results of RS analysis of Lena RGB images calculated by using the bit-plane algorithm provided in the embodiment of the present application at different embedding rates are shown. It can be seen that, under the same embedding rate, the RS analysis result obtained by using the bit plane algorithm scrambled based on the sub-affine transformation has a lower value than the RS analysis result obtained by using the ordinary bit plane algorithm, and therefore, the bit plane algorithm provided by the embodiment of the present application has a stronger anti-hiding analysis capability.

TABLE 5

TABLE 6

(4) Frequency histogram analysis method

As shown in fig. 3, the frequency histogram of the first image is shown, and as shown in fig. 4, the frequency histogram of the third image is shown. It can be seen that the three graphs are basically indistinguishable from each other, so the information hiding method provided by the embodiment of the application can resist the analysis of frequency histograms.

In the embodiment of the invention, because the sub-affine transformation and the bit plane information hiding can be combined, and the N bit planes of the second image are hidden into the M first bit planes of the first image, the difference between the first image and the third image is extremely small visually, and the anti-hiding analysis capability of the third image can be improved.

The scheme provided by the embodiment of the application is mainly introduced from the perspective of a method. To implement the above functions, it includes hardware structures and/or software modules for performing the respective functions. Those of skill in the art will readily appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. Whether a function is performed as hardware or computer software drives hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the information hiding method provided by the embodiment of the application, the execution main body may be an information hiding device, or a control module for hiding information in the information hiding device. In the embodiment of the present application, an information hiding method executed by an information hiding device is taken as an example to describe the information hiding device provided in the embodiment of the present application.

In addition, in the embodiment of the present application, the information hiding device may be divided into the functional modules according to the method example, for example, each functional module may be divided according to each function, or two or more functions may be integrated into one processing module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. Optionally, the division of the modules in the embodiment of the present application is schematic, and is only a logic function division, and there may be another division manner in actual implementation.

As shown in fig. 5, an information hiding apparatus 500 is provided in an embodiment of the present application. The information hiding apparatus 500 includes: an acquisition unit 501 and a processing unit 502. The acquiring unit 501 may be configured to acquire a first image and a second image; the processing unit 502 may be configured to determine M first bit planes of the first image, and perform sub-affine transformation scrambling on the M first bit planes to obtain M second bit planes, where noise of the first bit planes in a same image channel of the first image is lower than noise of other bit planes in the same image channel; determining N bit planes of the second image, and embedding the N bit planes into the M second bit planes to obtain M third bit planes, wherein one bit plane in the N bit planes is correspondingly embedded into one second bit plane; performing sub-affine periodic reduction on the M third bitplanes to obtain a third image hiding the N bitplanes; wherein M, N is a positive integer, and M is greater than or equal to N.

Optionally, the first image comprises 4 image channels, each image channel comprising 8 bit planes; the processing unit 502 may specifically be configured to: sequentially carrying out first operation on 4 image channels of the first image to obtain 8 first bit planes; carrying out sub-affine transformation scrambling on the 8 first bitplanes to obtain 8 second bitplanes; the first operation includes: sequencing 8 bit planes in a target image channel according to the sequence of bit plane noise from small to large; determining the first two bit planes as a first bit plane of the target image channel, the target image channel being any one of 4 image channels of the first image.

Optionally, the second image includes 1 image channel; the processing unit 502 may specifically be configured to: embedding 8 bit planes of the second image into the 8 second bit planes in a one-to-one correspondence.

Optionally, the obtaining unit 501 may be further configured to obtain the third image; the processing unit 502 may be further configured to determine a bit plane containing embedded information in a bit plane of the third image, and perform sub-affine transform scrambling on the bit plane containing embedded information; and extracting data of N bit planes from the bit planes subjected to the sub-affine transformation scrambling by comparing the M second bit planes.

Optionally, the processing unit 502 may be further configured to determine the anti-steganalysis capability of the third image according to a preset analysis method, where the preset analysis method includes at least one of a histogram intersection distance formula analysis method, a cosine function formula analysis method, a regular and singular group RS analysis method, and a frequency histogram analysis method.

Of course, the information hiding device 500 provided in the embodiment of the present application includes, but is not limited to, the above units.

According to the information hiding device provided by the embodiment of the invention, because sub-affine transformation and bit plane information hiding can be combined, and N bit planes of the second image are hidden into M first bit planes of the first image, the difference between the first image and the third image is extremely small visually, and the anti-hiding analysis capability of the third image can be improved.

The embodiment of the present application further provides an information hiding apparatus as shown in fig. 6, where the information hiding apparatus includes a processor 11, a memory 12, a communication interface 13, and a bus 14. The processor 11, the memory 12 and the communication interface 13 may be connected by a bus 14.

The processor 11 is a control center of the information hiding apparatus, and may be a single processor or a collective term for a plurality of processing elements. For example, the processor 11 may be a general-purpose Central Processing Unit (CPU), or may be another general-purpose processor. Wherein a general purpose processor may be a microprocessor or any conventional processor or the like.

For one embodiment, processor 11 may include one or more CPUs, such as CPU 0 and CPU 1 shown in FIG. 6.

The memory 12 may be, but is not limited to, a read-only memory (ROM) or other type of static storage device that may store static information and instructions, a Random Access Memory (RAM) or other type of dynamic storage device that may store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.

In a possible implementation, the memory 12 may be present separately from the processor 11, and the memory 12 may be connected to the processor 11 via a bus 14 for storing instructions or program code. The deployment method of the service function chain provided by the embodiment of the present application can be implemented when the processor 11 calls and executes the instructions or program codes stored in the memory 12.

In another possible implementation, the memory 12 may also be integrated with the processor 11.

And a communication interface 13 for connecting with other devices through a communication network. The communication network may be an ethernet network, a radio access network, a Wireless Local Area Network (WLAN), or the like. The communication interface 13 may comprise a receiving unit for receiving data and a transmitting unit for transmitting data.

The bus 14 may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended ISA (EISA) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown in FIG. 6, but this is not intended to represent only one bus or type of bus.

It should be noted that the structure shown in fig. 6 does not constitute a limitation of the information hiding apparatus. The information hiding means may comprise more or less components than those shown in fig. 6, or a combination of some components, or a different arrangement of components than those shown in the figure.

Embodiments of the present invention also provide a computer-readable storage medium, which includes computer-executable instructions. When the computer executes the instructions to run on the computer, the computer executes the steps executed by the information hiding device in the information hiding method provided by the embodiment.

The embodiment of the present invention further provides a computer program product, which can be directly loaded into the memory and contains software codes, and after the computer program product is loaded and executed by the computer, the information hiding method provided by the above embodiment can be implemented, and each step executed by the information hiding device is executed.

Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) and includes instructions for causing a terminal to execute the methods according to the embodiments of the present invention.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.