阅读说明：本技术 晶圆对准曝光方法及半导体器件 (Wafer alignment exposure method and semiconductor device ) 是由 陈帮 黄宇恒 盛备备 于 2021-08-24 设计创作，主要内容包括：本发明提供一种晶圆对准曝光方法及半导体器件,包括：提供第一晶圆,其具有相对的第一表面和第二表面；提供光罩,其上设置有光罩图形,光罩图形与第一标记层的图形对应；光刻机台通过光罩对第一光阻层曝光,在对应透光区的位置形成第一开孔；刻蚀第一晶圆形成沟槽。本发明的光罩图形与第一标记层的图形对应,通过曝光后刻蚀形成沟槽,沟槽在第二表面的投影至少覆盖一个子标记在第二表面的投影；使光刻机台识别第一标记层需穿透的厚度(识别厚度)变小,实现较厚晶圆加工时,光刻机台可以从晶圆厚度方向上的一侧识别另一侧的对准标识图形,满足后续工艺对准要求,提高工艺精度。(The invention provides a wafer alignment exposure method and a semiconductor device, comprising the following steps: providing a first wafer, wherein the first wafer is provided with a first surface and a second surface which are opposite; providing a photomask, wherein a photomask graph is arranged on the photomask, and the photomask graph corresponds to the graph of the first marking layer; exposing the first photoresist layer through a photomask by using a photoetching machine, and forming a first opening at a position corresponding to the light-transmitting area; and etching the first wafer to form a groove. The mask pattern corresponds to the pattern of the first mark layer, a groove is formed by etching after exposure, and the projection of the groove on the second surface at least covers the projection of one sub mark on the second surface; the thickness (identification thickness) of the first mark layer to be penetrated is reduced, so that the photoetching machine can identify the alignment mark pattern on the other side from one side in the thickness direction of the wafer when a thicker wafer is processed, the alignment requirement of the subsequent process is met, and the process precision is improved.)

1. A wafer alignment exposure method is characterized by comprising the following steps:

providing a first wafer, wherein the first wafer is provided with a first surface and a second surface which are opposite; a first photoresist layer is formed on the first surface; a first marking layer is formed on one side close to the second surface; the first mark layer comprises at least one sub-mark;

providing a photomask, wherein a photomask graph is arranged on the photomask, the photomask graph corresponds to the graph of the first marking layer, and the photomask graph comprises a light-transmitting area;

exposing the first photoresist layer through the photomask by using a photoetching machine, and forming a first opening at a position corresponding to the light-transmitting area;

and etching the first wafer by taking the exposed first photoresist layer as a mask to form a groove, wherein the projection of the groove on the second surface at least covers the projection of one sub-mark on the second surface.

2. The wafer alignment exposure method as claimed in claim 1, wherein the projection of the transparent region on the second surface covers the projection of the first mark layer on the second surface.

3. The wafer alignment exposure method as claimed in claim 1, wherein in a cross section parallel to the first wafer, the X direction and the Y direction perpendicular to each other form four quadrants, the first mark layer includes four sub-marks spaced in a rectangular ring, and one sub-mark is disposed in one quadrant.

4. The wafer alignment exposure method of claim 3, wherein, in a cross section parallel to the first wafer, the light-transmitting areas comprise four sub-light-transmitting areas spaced in a rectangular ring, one of the sub-light-transmitting areas being disposed in one of the quadrants; the projection of the sub-transmissive region in each quadrant onto the second surface covers the projection of the corresponding sub-mark onto the second surface.

5. The wafer alignment exposure method according to claim 4,

the lower left corner of the sub-mark located in a first quadrant is aligned with the lower left corner of the sub-transmitting region located in the first quadrant;

a lower right corner of the sub-mark located in a second quadrant is aligned with a lower right corner of the sub-transmissive region located in the second quadrant;

the upper right corner of the sub-mark located in the third quadrant is aligned with the upper right corner of the sub-transmitting area located in the third quadrant;

the upper left corner of the sub-mark located in the fourth quadrant is aligned with the upper left corner of the sub-transmitting region located in the fourth quadrant.

6. The wafer alignment exposure method according to claim 4, wherein the sub-transmissive regions are square, the four sub-transmissive regions are arranged in a square ring at intervals, and when the first mark layer is not recognized by the lithography machine on the first surface side through exposure, the position deviation range of the exposure light is within ± a; the maximum width of the sub-mark in the X direction and the maximum width of the sub-mark in the Y direction are both b; the side length of the sub light-transmitting area is a + b.

7. The wafer alignment exposure method of claim 1, wherein the thickness of the first wafer is greater than the maximum recognition thickness of a photolithography tool, and the thickness from the bottom of the trench to the first mark layer is less than or equal to the maximum recognition thickness of the photolithography tool.

8. The wafer alignment exposure method according to any one of claims 1 to 7, wherein the trench comprises four sub-trenches spaced apart in a square ring or a rectangular ring in a cross section parallel to the first wafer, and the sub-trenches have one of a square shape, a rectangular shape, or a circular shape.

9. The wafer alignment exposure method according to any one of claims 1 to 7,

when the manufacturing process is less than 50nm, at least 12 grooves are formed, and the grooves are distributed in the peripheral edge area of the first wafer at intervals;

when the manufacturing process is 50nm to 1 μm, at least 6 grooves are formed, and the grooves are distributed at intervals in the peripheral edge area of the first wafer;

and when the manufacturing process is larger than 1 micrometer, forming two grooves which are distributed at two ends of one diameter of the first wafer.

10. The wafer alignment exposure method according to any one of claims 1 to 7, wherein the manufacturing method further comprises:

forming a second photoresist layer on the first surface and exposing the second photoresist layer, wherein the photoetching machine station identifies the first marking layer through the groove to realize the alignment of the exposure process of the second photoresist layer;

etching the first wafer to form a second opening by taking the exposed second photoresist layer as a mask;

and forming a filling layer, wherein the filling layer is filled in the groove and the second opening.

11. The wafer alignment exposure method of claim 10,

the fill layer includes a second marker layer that is aligned with the first marker layer.

12. A semiconductor device, comprising:

a first wafer having opposing first and second surfaces; a first marking layer is formed on one side close to the second surface; the first mark layer comprises at least one sub-mark; a trench extending through a portion of a thickness of the first wafer from the first surface; the projection of the groove on the second surface at least covers the projection of one sub-mark on the second surface.

13. The semiconductor device according to claim 12, further comprising:

a second opening through a portion of the thickness of the first wafer from the first surface;

a filling layer filled in the trench and the second opening.

14. The semiconductor device according to claim 13,

the fill layer includes a second marker layer that is aligned with the first marker layer.

15. The semiconductor device according to claim 12, wherein in a cross section parallel to the first wafer, X and Y directions perpendicular to each other constitute four quadrants, the first mark layer includes four sub-marks arranged at intervals in a rectangular ring, and one of the sub-marks is arranged in one of the quadrants.

16. The semiconductor device of claim 15, wherein, in a cross-section parallel to the first wafer, the trench comprises four sub-trenches spaced apart in a rectangular ring; in each quadrant, the sub-grooves and the sub-marks are distributed in a one-to-one correspondence mode; the projection of the sub-grooves in at least one quadrant on the second surface covers the projection of the corresponding sub-marks on the second surface.

17. The semiconductor device according to claim 16, wherein the sub-trenches are square, the four sub-trenches are arranged at intervals in a square ring, and when the first mark layer is not recognized by a photolithography tool in exposure on the first surface side, a positional deviation range of an exposure light is within ± a; the maximum width of the sub-mark in the X direction and the maximum width of the sub-mark in the Y direction are both b; the side length of the sub-groove is a + b.

18. The semiconductor device of claim 12, wherein a thickness of the first wafer is greater than a maximum identified thickness of a photolithography tool, and a thickness of the trench bottom to the first marker layer is less than or equal to the maximum identified thickness of the photolithography tool.

19. The semiconductor device according to any one of claims 12 to 18,

when the manufacturing process is less than 50nm, at least 12 grooves are formed, and the grooves are distributed in the peripheral edge area of the first wafer at intervals;

when the manufacturing process is 50nm to 1 μm, at least 6 grooves are formed, and the grooves are distributed at intervals in the peripheral edge area of the first wafer;

and when the manufacturing process is larger than 1 micrometer, forming two grooves which are distributed at two ends of one diameter of the first wafer.

Technical Field

The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a wafer alignment exposure method and a semiconductor device.

Background

In the three-dimensional stacking technology, two or more wafers are bonded and stacked together, a pattern is made on the back surface of a top wafer, at this time, a mark pattern on the front surface of the top wafer needs to be aligned, and if the thickness of the top wafer exceeds the maximum recognition thickness of a photoetching machine, the photoetching machine cannot recognize the alignment mark pattern on the front surface of the top wafer, so that the photoetching process on the back surface of the top wafer cannot be carried out. If the photolithographic process on the back side of the top wafer is not aligned with the front side or front layer wafer of the top wafer, the process results are not satisfactory for the design requirements. This limits the thickness of the top wafer and thus the application of this process in certain areas.

Disclosure of Invention

The invention aims to provide a wafer alignment exposure method and a semiconductor device, which can realize that a photoetching machine can identify an alignment identification pattern on the other side (such as the side bonded with other wafers) from one side (such as the non-bonded side) in the thickness direction of the wafer when a thicker wafer is processed, meet the alignment requirement of subsequent processes (such as photoetching) and improve the process precision.

The invention provides a wafer alignment exposure method, which comprises the following steps:

providing a first wafer, wherein the first wafer is provided with a first surface and a second surface which are opposite; a first photoresist layer is formed on the first surface; a first marking layer is formed on one side close to the second surface; the first mark layer comprises at least one sub-mark;

providing a photomask, wherein a photomask graph is arranged on the photomask, the photomask graph corresponds to the graph of the first marking layer, and the photomask graph comprises a light-transmitting area;

exposing the first photoresist layer through the photomask by using a photoetching machine, and forming a first opening at a position corresponding to the light-transmitting area;

and etching the first wafer by taking the exposed first photoresist layer as a mask to form a groove, wherein the projection of the groove on the second surface at least covers the projection of one sub-mark on the second surface.

Further, the projection of the light-transmitting area on the second surface covers the projection of the first mark layer on the second surface.

Furthermore, on a cross section parallel to the first wafer, four quadrants are formed in the X direction and the Y direction which are perpendicular to each other, the first mark layer includes four sub-marks which are distributed at intervals in a rectangular ring, and one sub-mark is distributed in one quadrant.

Furthermore, on a section parallel to the first wafer, the light-transmitting area comprises four sub light-transmitting areas which are distributed at intervals in a rectangular ring shape, and one sub light-transmitting area is distributed in one quadrant; the projection of the sub-transmissive region in each quadrant onto the second surface covers the projection of the corresponding sub-mark onto the second surface.

Further, the lower left corner of the sub-mark located in the first quadrant is aligned with the lower left corner of the sub-transmissive region located in the first quadrant;

a lower right corner of the sub-mark located in a second quadrant is aligned with a lower right corner of the sub-transmissive region located in the second quadrant;

the upper right corner of the sub-mark located in the third quadrant is aligned with the upper right corner of the sub-transmitting area located in the third quadrant;

the upper left corner of the sub-mark located in the fourth quadrant is aligned with the upper left corner of the sub-transmitting region located in the fourth quadrant.

Furthermore, the sub light transmission areas are square, the four sub light transmission areas are distributed at intervals in a square ring shape, and when the first mark layer cannot be identified by exposure of the photoetching machine on one side of the first surface, the position deviation range of the exposure light is within +/-a; the maximum width of the sub-mark in the X direction and the maximum width of the sub-mark in the Y direction are both b; the side length of the sub light-transmitting area is a + b.

Further, the thickness of the first wafer is larger than the maximum recognition thickness of a photoetching machine, and the thickness from the bottom of the groove to the first mark layer is smaller than or equal to the maximum recognition thickness of the photoetching machine.

Further, on a cross section parallel to the first wafer, the trench includes four sub-trenches distributed at intervals in a square ring or a rectangular ring, and the sub-trenches are one of square, rectangular or circular.

Further, when the manufacturing process is less than 50nm, at least 12 grooves are formed, and the grooves are distributed in the peripheral edge area of the first wafer at intervals;

when the manufacturing process is 50nm to 1 μm, at least 6 grooves are formed, and the grooves are distributed at intervals in the peripheral edge area of the first wafer;

and when the manufacturing process is larger than 1 micrometer, forming two grooves which are distributed at two ends of one diameter of the first wafer.

Further, the manufacturing method further comprises:

forming a second photoresist layer on the first surface and exposing the second photoresist layer, wherein the photoetching machine station identifies the first marking layer through the groove to realize the alignment of the exposure process of the second photoresist layer;

etching the first wafer to form a second opening by taking the exposed second photoresist layer as a mask;

forming a filling layer, wherein the filling layer is filled in the groove and the second opening;

further, the fill layer includes a second marker layer that is aligned with the first marker layer.

The present invention also provides a semiconductor device comprising:

a first wafer having opposing first and second surfaces; a first marking layer is formed on one side close to the second surface; the first mark layer comprises at least one sub-mark; a trench extending through a portion of a thickness of the first wafer from the first surface; the projection of the groove on the second surface at least covers the projection of one sub-mark on the second surface.

Further, the semiconductor device further includes:

a second opening through a portion of the thickness of the first wafer from the first surface;

a filling layer filled in the trench and the second opening.

Further, the fill layer includes a second marker layer that is aligned with the first marker layer.

Furthermore, on a cross section parallel to the first wafer, four quadrants are formed in the X direction and the Y direction which are perpendicular to each other, the first mark layer includes four sub-marks which are distributed at intervals in a rectangular ring, and one sub-mark is distributed in one quadrant.

Further, on a section parallel to the first wafer, the groove comprises four sub-grooves distributed at intervals in a rectangular ring shape; in each quadrant, the sub-grooves and the sub-marks are distributed in a one-to-one correspondence mode; the projection of the sub-grooves in at least one quadrant on the second surface covers the projection of the corresponding sub-marks on the second surface.

Furthermore, the sub-grooves are square, the four sub-grooves are distributed at intervals in a square ring shape, and when the first mark layer cannot be identified by exposure of a photoetching machine on one side of the first surface, the position deviation range of the exposure is within +/-a; the maximum width of the sub-mark in the X direction and the maximum width of the sub-mark in the Y direction are both b; the side length of the sub-groove is a + b.

Further, the thickness of the first wafer is larger than the maximum recognition thickness of a photoetching machine, and the thickness from the bottom of the groove to the first mark layer is smaller than or equal to the maximum recognition thickness of the photoetching machine.

Further, when the manufacturing process is less than 50nm, at least 12 grooves are formed, and the grooves are distributed in the peripheral edge area of the first wafer at intervals;

when the manufacturing process is 50nm to 1 μm, at least 6 grooves are formed, and the grooves are distributed at intervals in the peripheral edge area of the first wafer;

and when the manufacturing process is larger than 1 micrometer, forming two grooves which are distributed at two ends of one diameter of the first wafer.

Compared with the prior art, the invention has the following beneficial effects:

the invention provides a wafer alignment exposure method and a semiconductor device, comprising the following steps: providing a first wafer, wherein the first wafer is provided with a first surface and a second surface which are opposite; a first photoresist layer is formed on the first surface; a first marking layer is formed on one side close to the second surface; the first mark layer comprises at least one sub-mark; providing a photomask, wherein a photomask graph is arranged on the photomask, and the photomask graph corresponds to the graph of the first marking layer; exposing the first photoresist layer through the photomask by using a photoetching machine, and forming a first opening at a position corresponding to the light-transmitting area; and etching the first wafer to form a groove by taking the exposed first photoresist layer as a mask. The invention sets the pattern of a light shield corresponding to the pattern of a first mark layer, and a groove is formed by etching after exposure, and the projection of the groove on the second surface at least covers the projection of one sub-mark on the second surface; the thickness (identification thickness) which needs to be penetrated by the photoetching machine for identifying the first mark layer is reduced, so that when a thicker wafer is processed, the photoetching machine can identify the alignment mark pattern on the other side (for example, the side bonded with other wafers) from one side (for example, the non-bonded side) in the thickness direction of the wafer, the alignment requirement of the subsequent process (for example, photoetching) is met, the process precision is improved, and the method can be applied to more fields.

The invention is not limited to solve the problem that the maximum recognition thickness of the photoetching machine is not enough, and the thickness which needs to be penetrated after the groove is formed is reduced, so that even if the maximum recognition thickness of the photoetching machine is enough, the recognition precision of the photoetching machine can be improved and the recognition difficulty can be reduced by the invention.

Drawings

Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the invention.

Fig. 2 is a schematic view of a first wafer according to an embodiment of the invention.

FIG. 3 is a schematic diagram illustrating the distribution of the mask pattern and the first mark layer according to the embodiment of the present invention.

FIG. 4 is a diagram illustrating a trench formed according to an embodiment of the present invention.

Fig. 5a is a schematic diagram of a right deviation of a trench actually formed in accordance with an embodiment of the present invention.

Fig. 5b is a schematic left-side view of a trench actually formed according to an embodiment of the present invention.

FIG. 5c is a schematic diagram of an upper offset of a trench actually formed according to an embodiment of the present invention.

FIG. 5d is a schematic diagram of a trench being formed in practice according to an embodiment of the present invention.

FIG. 5e is a schematic diagram illustrating the trench actually formed according to the embodiment of the present invention shifted to the upper right.

Fig. 6 is a schematic view illustrating distribution positions of trenches on a first wafer according to an embodiment of the invention.

FIG. 7 is a diagram illustrating a second photoresist layer formed according to an embodiment of the present invention.

Fig. 8 is a schematic diagram illustrating the second opening formed according to the embodiment of the invention.

FIG. 9 is a diagram illustrating a second mark layer formed according to an embodiment of the present invention.

Wherein the reference numbers are as follows:

m-mask; k-a light-transmitting region; k1, K2, K3, K4-sub light-transmitting region; l-a first opening; 10-a first wafer; 11-a first substrate; 11 a-a first surface; 11 b-a second surface; 12-a second dielectric layer; 13-a first indicia layer; 13a, 13b, 13c, 13 d-subtag; 20-a second wafer; 31-a first photoresist layer; a V-groove; v1, V2, V3, V4-sub-trenches; 32-a second photoresist layer; o-second opening; 14-a filling layer.

Detailed Description

Based on the above research, the embodiment of the invention provides a wafer alignment exposure method and a semiconductor device. The invention is described in further detail below with reference to the figures and specific examples. The advantages and features of the present invention will become more apparent from the following description. It is to be noted, however, that the drawings are designed in a simplified form and are not to scale, but rather are to be construed in an illustrative and descriptive sense only and not for purposes of limitation.

An embodiment of the present invention provides a wafer alignment exposure method, as shown in fig. 1, including:

step S1, providing a first wafer having a first surface and a second surface opposite to each other; a first photoresist layer is formed on the first surface; a first marking layer is formed on one side close to the second surface; the first mark layer comprises at least one sub-mark;

step S2, providing a photomask, wherein a photomask graph is arranged on the photomask, the photomask graph corresponds to the graph of the first mark layer, and the photomask graph comprises a light-transmitting area;

step S3, exposing the first photoresist layer through the mask by a photolithography tool, and forming a first opening at a position corresponding to the light-transmitting area;

step S4, etching the first wafer to form a groove by taking the exposed first photoresist layer as a mask, wherein the projection of the groove on the second surface at least covers the projection of one sub-mark on the second surface.

The steps of the wafer alignment exposure method according to the embodiment of the invention will be described in detail with reference to fig. 2 to 9.

As shown in fig. 2, a first wafer 10 is provided, where the first wafer 10 has a first surface 11a and a second surface 11b opposite to each other, and a first photoresist layer 31 is formed on the first surface 11 a; a first mark layer 13 is formed on a side of the first wafer 10 close to the second surface 11b, and in some embodiments, the first mark layer 13 includes at least one sub-mark. Specifically, the first wafer 10 includes a substrate 11 and a dielectric layer 12 formed on the substrate 11, and the first mark layer 13 is formed in the dielectric layer 12. The first mark layer 13 may be a metal alignment mark layer, and may also be an alignment mark layer formed of silicon oxide and/or silicon nitride. The second surface 11b side of the first wafer 10 may be bonded with a second wafer 20 or more. The first wafer 10 has a relatively thick thickness, for example, the thickness of the first wafer 10 is greater than or equal to 50 μm. According to different models of the blasting machines, the thickness of the penetrable wafer is different, and the current mainstream machine cannot penetrate the wafer with the thickness larger than 50 μm.

As shown in fig. 2 and 3, a mask M is provided, on which a mask pattern is disposed, the mask pattern including a light-transmitting region K, and the mask pattern corresponds to the pattern of the first mark layer 13. Illustratively, in a cross section parallel to the first wafer 10, the X direction and the Y direction perpendicular to each other constitute four quadrants, and the first mark layer 13 includes four sub-marks (e.g., 13a, 13b, 13c, and 13d) spaced apart in square or rectangular rings, one of the quadrants being allocated to one of the sub-marks, and the maximum cross-sectional widths of the sub-marks in both XY directions are b. Illustratively, the sub-indicia may be in the form of a cross, a cross-hair, or a plurality of parallel spaced apart patterns.

The mask M is provided with a light-transmitting region K, and the light-transmitting region K includes four sub-light-transmitting regions (e.g., K1, K2, K3, and K4) spaced in a square or rectangular ring shape in a cross section parallel to the first wafer 10. The light-transmitting region K of the mask M is required to be light-transmitting and chromium-plating-free region, and the non-light-transmitting region (light-opaque region) of the mask M is chromium-plating-free region.

In another embodiment, the light-transmitting region K may be configured in other shapes, such as a rectangle, but may also be configured in an oval shape and the like. For example, when the known machine is offset more toward a certain direction (for example, Y direction), the transparent region K may be set to be rectangular. For the same reason, the arrangement of the four sub-transmission regions can be set to other shapes, such as a rectangle.

The projection of the transparent area K on the second surface 11b covers the projection of the first mark layer on the second surface 11b, and specifically, the projection of the sub-transparent area in each quadrant on the second surface 11b covers the projection of the corresponding sub-mark on the second surface 11 b.

The lower left corner of the sub mark 13a located in the first quadrant is aligned with the lower left corner of the sub transmitting area K1 located in the first quadrant; the lower right corner of the sub mark 13b located in the second quadrant is aligned with the lower right corner of the sub transmitting area K2 located in the second quadrant; the upper right corner of the sub-mark 13c located in the third quadrant is aligned with the upper right corner of the sub-transmitting area K3 located in the third quadrant; the upper left corner of the sub-mark 13d located in the fourth quadrant is aligned with the upper left corner of the sub-transmitting area K4 located in the fourth quadrant.

Exposing and developing the first photoresist layer 31 through the photomask M by a photoetching machine to form a first opening L, wherein the first opening L corresponds to the pattern of the first mark layer 13; the thickness of the first wafer 10 is greater than the maximum identified thickness of the photolithography tool.

When the photolithography tool forms various patterns on the first surface 11a of the first wafer 10, the photolithography tool needs to align with the first mark layer 13 on the side of the first wafer 10 close to the second surface 11b to align the patterns on the two sides of the first wafer 10 in the thickness direction. Such as transistor element patterns, metal leads, pads, etc. of an integrated circuit. When the patterned first photoresist layer 31 is formed on the first surface 11a, the patterned first photoresist layer 31 has a first opening L, and since the first wafer 10 is thicker than the maximum recognition thickness of the photolithography tool, the photolithography tool does not blindly expose the first mark layer 13 (which is too thick to be recognized), and the photolithography tool can ensure that the variation range of the exposure position is within ± a (e.g., ± 500 μm), i.e., the deviation between the actual exposure position and the theoretical exposure position is within ± a.

As shown in fig. 2 and 4, in order to identify the first mark layer 13 by the subsequent photolithography tool, the first exposed photoresist layer 31 is used as a mask to etch the first wafer 10 to form a trench V, such that the thickness h from the bottom of the trench V to the first mark layer 13 is less than or equal to the maximum identification thickness of the photolithography tool; in this way, the photolithography tool can identify the first mark layer 13 from the trench V. The projection of the groove V on the second surface 11b covers at least one projection of the sub-mark on the second surface 11 b. The groove V is located above the first mark layer 13; the grooves V extend through a part of the thickness of the first wafer 10 from the first surface 11 a.

After forming the trench V, the area of the first wafer 10 is occupied, so that the trench needs to be reasonably arranged, and the occupied area of the trench V is reduced as much as possible on the premise of meeting the thickness identification requirement.

The trench V is formed by etching using the patterned first photoresist layer 31 as a mask. The actual position of the trench V depends on the actual exposure position of the first opening L of the first photoresist layer 31. The photolithography tool exposes the first photoresist layer 31 through the mask M. When the first opening L is formed, the photolithography tool performs blind exposure, the first mark layer 13 is not recognized (too thick) by exposure on the first surface 11a side, and the photolithography tool can ensure that the variation range of the exposure position is within ± a (e.g., ± 500 μm).

Because the first mark layer 13 cannot be identified by blind exposure, the actual exposure position may be shifted to the right, left, up, or down or in other directions (for example, right upper, left lower, etc.) compared with the theoretical exposure position, and the shift to which direction is random, the gist of the embodiment of the present invention is that no matter which direction the trench V is shifted, after the trench V is opened (formed), the photolithography tool can identify at least one sub-mark from the actually formed trench V to the lower side, that is, the projection of the actually formed trench V on the second surface 11b can at least cover the projection of one sub-mark on the second surface; that is, regardless of the offset direction, the requirement of forming various patterns on the first surface 11a side of the first wafer 10 to align with the previous layer (the second surface 11b side of the first wafer 10) is satisfied.

Blind exposure is carried out on a photoetching machine, namely the first mark layer 13 is not identified as being too thick, the photoetching machine can ensure that the variation range of the exposure position is +/-a, so that at least one sub mark can be ensured to be still in the groove V slotting range in a plane parallel to the first wafer 10 if the maximum deviation a of the upper part, the lower part, the left part and the right part is a, namely the photoetching machine can identify at least one sub mark from the groove V slotting range; then alignment is satisfied throughout the range of flare position variation.

Illustratively, as shown in fig. 5a, if the flare pattern is shifted to the right by a, i.e. the position of the actually formed groove V (solid line box) is shifted to the right by a from the theoretical position (dashed line box), the sub-mark 13b of the second quadrant and the sub-mark 13c of the third quadrant (front layer alignment mark pattern) are still within the groove V slotting range, specifically within the sub-groove V2 and the sub-groove V3, i.e. the projection of the groove V on the second surface can cover at least one sub-mark (e.g. 13b and 13c) projected on the second surface. Similarly, as shown in fig. 5b, if the flare pattern is shifted to the left by a, the sub-mark 13a of the first quadrant and the sub-mark 13d of the fourth quadrant (the front layer alignment mark pattern) are still within the groove V grooving range, specifically, the sub-groove V1 and the sub-groove V4. As shown in fig. 5c, if the flare pattern is shifted upward by a, the sub-mark 13c of the third quadrant and the sub-mark 13d of the fourth quadrant (front layer alignment mark pattern) remain within the groove V grooving range, particularly within the sub-groove V3 and the sub-groove V4. As shown in fig. 5d, if the flare pattern is shifted downward by a, the sub-mark 13a of the first quadrant and the sub-mark 13b of the second quadrant (the front layer alignment mark pattern) remain within the groove V grooving range, particularly within the sub-groove V1 and the sub-groove V2. As shown in fig. 5e, if the flare pattern is shifted to the upper right (e.g., by a to the right and by a upward), the sub-mark 13c (front layer alignment mark pattern) of the third quadrant is still within the groove V grooving range, specifically within the sub-groove V3. The present embodiment can fully ensure that the alignment mark pattern (e.g., the first mark layer 13) under the first wafer (thick silicon) can be recognized.

In a cross section parallel to the first wafer, the trench V includes four sub-trenches (e.g., V1, V2, V3, and V4) spaced in square or rectangular rings, and illustratively, the sub-trenches have a side length of a + b, and one sub-trench is distributed in one quadrant.

In another embodiment, the grooves V may be provided in other shapes, such as rectangular. For example, when the known machine is offset more toward a certain direction (for example, the Y direction), the groove V may be configured to be rectangular, or may be configured to be circular, elliptical, or the like. For the same reason, the arrangement of four grooves V can also be provided in other shapes, such as rectangular rings.

As shown in fig. 6, the number and positions of the grooves V need to be set properly according to the manufacturing process requirements. When the manufacturing process requirement is higher, for example, less than 50nm, at least 12 grooves are formed, and the grooves are distributed at intervals in the peripheral edge area of the first wafer; the manufacturing process is less than 50nm, which means that the distance between circuits in an Integrated Circuit (IC) is less than 50 nm. The manufacturing process requires that at least 6 grooves are formed when the thickness is 50nm to 1 μm, and the grooves are distributed at intervals in the peripheral edge area of the first wafer, such as the area B in the figure; when the manufacturing process is larger than 1 μm, two grooves are formed, and the two grooves are distributed at two ends of a diameter of the first wafer, such as an area A in the figure.

The photolithography tool can recognize the first mark layer 13 after the groove V is formed on the first wafer 10, and the alignment between the pattern formed on the first surface 11a side of the first wafer 10 and the pattern formed on the second surface 11b side is realized.

The wafer alignment exposure method of the embodiment further includes:

as shown in fig. 7, a second photoresist layer 32 is formed on the first surface and exposed, and the photolithography tool recognizes the first mark layer 13 through the trench V, so as to achieve alignment of the exposure process of the second photoresist layer 32; in the exposure process, the yellow light process can be aligned to a thicker wafer, so that the wafer can meet more application fields.

As shown in fig. 8, the exposed second photoresist layer 32 is used as a mask to etch the first wafer to form a second opening O; then, the patterned second photoresist layer 32 is removed.

As shown in fig. 9, a filling layer 14 is formed, and the filling layer 14 is filled in the trench V and the second opening O. The fill layer includes a second marker layer that is aligned with the first marker layer. So far, the first surface 11a side of the first wafer 10 has an alignment mark layer, and when a wafer is subsequently stacked or a next layer is manufactured, the second mark layer can be used as an alignment mark reference. The second marker layer is, for example, a silicon oxide layer or a metal layer (e.g., one of copper, aluminum, or tungsten). The filling layer can also comprise other dielectric layers or functional layers, and the required pattern is designed according to actual requirements.

The present embodiment also provides a semiconductor device including:

as shown in fig. 4, a first wafer 10 having opposing first and second surfaces; a first mark layer 13 is formed on one side close to the second surface; the first label layer 13 comprises at least one sub-label; the thickness of the first wafer 10 is greater than the maximum recognition thickness of the lithography machine;

a groove V, wherein the groove V penetrates through the first wafer 10 with partial thickness from the first surface, and the thickness h from the bottom of the groove V to the first mark layer 13 is smaller than or equal to the maximum identification thickness of the photoetching machine; the projection of the groove V on the second surface at least covers the projection of one sub-mark on the second surface.

Specifically, as shown in fig. 4, 8, and 9, the semiconductor device further includes:

a second opening O extending through a portion of the thickness of the first wafer 10 from the first surface;

and a filling layer 14, wherein the filling layer 14 is filled in the groove V and the second opening O. The fill layer includes a second marker layer that is aligned with the first marker layer. The filling layer can also comprise other dielectric layers or functional layers, and the required pattern is designed according to actual requirements.

The first wafer 10 also has an alignment mark layer (second mark layer) on the first surface 11a side, and the second mark layer can be used as an alignment mark reference when a wafer is subsequently stacked or a next layer is manufactured.

As shown in fig. 5a to 5e, in a cross section parallel to the first wafer, the X direction and the Y direction perpendicular to each other form four quadrants, and the first mark layer 13 includes four sub-marks (e.g., 13a, 13b, 13c, and 13d) uniformly spaced in a square ring, one sub-mark is distributed in one quadrant, and the four sub-marks are located in the same layer. It should be noted that four quadrants are not necessarily required to divide the wafer into four equal sized portions, and are merely illustrative definitions made for convenience in describing the orientation of the plurality of marks.

On a section parallel to the first wafer, the trench V comprises four sub-trenches (such as V1, V2, V3 and V4) distributed at equal intervals in a square ring, and the sub-trenches are square; in each quadrant, the sub-grooves and the sub-marks are distributed in a one-to-one correspondence mode; the projection of the sub-grooves in at least one quadrant on the second surface covers the projection of the corresponding sub-marks on the second surface. When the photoetching machine station cannot identify the first mark layer by exposure on one side of the first surface, the position deviation range of the exposure is within +/-a; the maximum width of the sub-mark in the X direction and the maximum width of the sub-mark in the Y direction are both b; the side length of the sub-groove is a + b. As shown in fig. 6, the number and positions of the grooves V need to be set properly according to the manufacturing process requirements. When the manufacturing process requirement is higher, for example, less than 50nm, at least 12 grooves are formed, and the grooves are distributed at intervals in the peripheral edge area of the first wafer; the manufacturing process is less than 50nm, which means that the distance between circuits in an Integrated Circuit (IC) is less than 50 nm. The manufacturing process requires that at least 6 grooves are formed when the thickness is 50nm to 1 μm, and the grooves are distributed at intervals in the peripheral edge area of the first wafer, such as the area B in the figure; when the manufacturing process is larger than 1 μm, two grooves are formed, and the two grooves are distributed at two ends of a diameter of the first wafer, such as an area A in the figure.

In summary, the present invention provides a wafer alignment exposure method and a semiconductor device, including: providing a first wafer, wherein the first wafer is provided with a first surface and a second surface which are opposite; the first mark layer includes at least one sub-mark; providing a photomask, wherein a photomask graph is arranged on the photomask, the photomask graph corresponds to the graph of the first marking layer, and the photomask graph comprises a light-transmitting area; exposing the first photoresist layer through the photomask by using a photoetching machine, and forming a first opening at a position corresponding to the light-transmitting area; and etching the first wafer to form a groove. The photomask graph of the photomask corresponds to the graph of the first mark layer, a groove is formed by etching after exposure, and the projection of the groove on the second surface at least covers the projection of one sub-mark on the second surface; the thickness (identification thickness) which needs to be penetrated by the photoetching machine for identifying the first mark layer is reduced, so that when a thicker wafer is processed, the photoetching machine can identify the alignment mark pattern on the other side (for example, the side bonded with other wafers) from one side (for example, the non-bonded side) in the thickness direction of the wafer, the alignment requirement of the subsequent process (for example, photoetching) is met, the process precision is improved, and the method can be applied to more fields.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the method disclosed by the embodiment, the description is relatively simple because the method corresponds to the device disclosed by the embodiment, and the relevant points can be referred to the description of the method part.

The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.