阅读说明：本技术 硬件加速器配置信息的配置方法、装置及存储介质 (Configuration method and device of hardware accelerator configuration information and storage medium ) 是由 刘君 于 2020-05-25 设计创作，主要内容包括：本申请实施例公开了一种硬件加速器配置信息的配置方法、装置及存储介质,所述方法包括：通过确定多个链表项中每一链表项的待更新配置信息,得到多组待更新配置信息,每一组待更新配置信息包括对应的链表项中的配置信息的部分配置信息；将多组待更新配置信息中每一组待更新配置信息写入对应的链表项,得到写入后的多个链表项；通过硬件加速器根据多个链表项中的配置信息中每一配置信息是否写入多个链表项中每一链表项,生成与该配置信息对应的标志位,得到多个标志位；将写入后的多个链表项和多个标志位打包成链表数据包,并写入共享存储器,从而减小了链表的内存大小,降低了存储空间需求；还降低了多个链表项的配置时间和对链表管理消耗的时间。(The embodiment of the application discloses a configuration method, a device and a storage medium of hardware accelerator configuration information, wherein the method comprises the following steps: obtaining a plurality of groups of configuration information to be updated by determining the configuration information to be updated of each link table item in a plurality of link table items, wherein each group of configuration information to be updated comprises part of configuration information of the configuration information in the corresponding link table item; writing each group of configuration information to be updated in the plurality of groups of configuration information to be updated into a corresponding link table item to obtain a plurality of written link table items; generating a flag bit corresponding to the configuration information according to whether each piece of configuration information in the plurality of linked list items is written into each linked list item in the plurality of linked list items or not by a hardware accelerator to obtain a plurality of flag bits; the written multiple linked list items and multiple flag bits are packaged into a linked list data packet and written into a shared memory, so that the memory size of the linked list is reduced, and the storage space requirement is reduced; configuration time for multiple link entries and time consumed for link management is also reduced.)

1. A method for configuring configuration information of a hardware accelerator, wherein the accelerator is configured by using configuration information in a plurality of linked list items, the method comprising:

determining the configuration information to be updated of each link table item in the plurality of link table items to obtain a plurality of groups of configuration information to be updated, wherein the configuration information to be updated comprises part of configuration information of the hardware accelerator;

writing each group of configuration information to be updated in the multiple groups of configuration information to be updated into the corresponding link table item to obtain multiple written link table items;

generating a flag bit corresponding to the configuration information according to whether each piece of configuration information in the plurality of linked list items is written into each linked list item in the plurality of linked list items or not by the hardware accelerator to obtain a plurality of flag bits;

and packaging the written multiple link table items and the multiple flag bits into a link table data packet, and writing the link table data packet into a shared memory, wherein the multiple flag bits form a link table head of the link table data packet, and the multiple groups of configuration information to be updated form a data part of the link table data packet.

2. The method of claim 1, wherein the configuration information of the hardware accelerator corresponding to each link entry includes multiple items of configuration information, and the determining the configuration information to be updated, which needs to be configured for each link entry in the multiple link entries in the configuration information of the hardware accelerator, to obtain multiple sets of configuration information to be updated includes:

and aiming at the ith link table item in the plurality of link table items, comparing the plurality of items of configuration information corresponding to the ith link table item with the plurality of items of configuration information corresponding to the (i-1) th link table item to obtain at least one different item of configuration information to be updated, wherein i is an integer greater than 1.

3. The method according to claim 2, wherein each configuration information corresponding to a first one of the plurality of linked list items belongs to the configuration information to be updated; and the last configuration information corresponding to each link table item in the plurality of link table items belongs to the configuration information to be updated.

4. The method according to any one of claims 1-3, further comprising:

creating a virtual address space through the hardware accelerator, and storing configuration information in a plurality of linked list items which are required to be configured by the accelerator to the virtual address space;

and accessing the virtual address space in the hardware accelerator to obtain the configuration information in a plurality of link items which need to be configured by the hardware accelerator.

5. The method according to claim 4, wherein the writing each of the plurality of sets of configuration information to be updated into the corresponding link table entry to obtain a plurality of written link table entries includes:

executing write operation on each configuration information corresponding to the first link table item in the plurality of link table items according to the address sequence of the virtual address space;

if the xth configuration information CFM corresponding to the ith link table item in the plurality of link table items_xXth configuration information CFM corresponding to (i-1) th link table entry_(i-1)xThe same, the xth configuration information CFM corresponding to the ith link table item is skipped_xWherein the CFM_ixConfiguring information for any one of the ith link table items, wherein x is a positive integer;

if the xth configuration information CFM_ixBelonging to the configuration information to be updated, and CFM (computational fluid dynamics) the configuration information_ixAnd writing the data into the ith link table entry.

6. The method according to any one of claims 1 to 5, wherein generating, by the hardware accelerator, a flag bit corresponding to the configuration information according to whether each piece of configuration information in the plurality of linked list items is written into each of the plurality of linked list items, and obtaining a plurality of flag bits comprises:

if the configuration information CFM corresponding to each of the plurality of link entries is aimed at_jExecuted write operations, generating with the hardware accelerator the configuration information CFM_jCorresponding flag bit 1, the configuration information CFM_jIs any configuration information, and j is a positive integer;

if not aiming at the configuration information CFM_jPerforming a write operation, generating with the configuration information CFM by the hardware accelerator_jThe corresponding flag bit is 0.

7. The method of claim 6, wherein each row in the netlist header includes m flag bits, m being a positive integer greater than 1, the method further comprising:

if the total number n of the flag bits corresponding to each chain table entry is not an integral multiple of m, filling reserved bits with residual vacant bits behind the last flag bit in the n flag bits in the last row of the n flag bits corresponding to each chain table entry in the chain table header.

8. The method of any one of claims 1-7, further comprising:

when the hardware accelerator uses any link table item in the plurality of link table items, determining the configuration information to be updated corresponding to the link table item according to the flag bit information corresponding to the link table item in the link table head;

and updating the configuration information to be updated corresponding to any link table entry in the data part into the hardware accelerator through the hardware accelerator.

9. An apparatus for configuring configuration information of a hardware accelerator, the hardware accelerator being configured with the configuration information in a plurality of linked list items, the apparatus comprising:

a determining unit, configured to determine configuration information to be updated of each of the plurality of linked list items, to obtain a plurality of sets of configuration information to be updated, where the configuration information to be updated includes partial configuration information of the hardware accelerator;

the writing unit is used for writing each group of configuration information to be updated in the plurality of groups of configuration information to be updated into the corresponding link table item to obtain a plurality of written link table items;

a generating unit, configured to generate a flag bit corresponding to configuration information according to whether each piece of configuration information in the configuration information is written into each of the plurality of linked list items through the hardware accelerator, so as to obtain a plurality of flag bits;

the write-in unit is further configured to pack the written multiple linked list items and the multiple flag bits into a linked list data packet, and write the linked list data packet into a shared memory, where the multiple flag bits form a linked list header of the linked list data packet, and the multiple sets of configuration information to be updated form a data portion of the linked list data packet.

10. An electronic device comprising a processor, a memory for storing one or more programs and configured for execution by the processor, the programs comprising instructions for performing the steps in the method of any of claims 1-8.

11. A computer-readable storage medium, characterized in that a computer program for electronic data exchange is stored, wherein the computer program causes a computer to perform the method according to any one of claims 1-8.

Technical Field

The present application relates to the field of electronic technologies, and in particular, to a method and an apparatus for configuring configuration information of a hardware accelerator, and a storage medium.

Background

After the communication technology enters the 5G era, as the amount of data transmitted by a chip of an electronic device is increased and the transmission time is shortened, a method of configuring a hardware accelerator (HWA) by using a linked list gradually replaces a conventional method of configuring a hardware accelerator by using a register, and becomes a mainstream technical scheme for configuring a hardware accelerator in a current chip. However, the configuration information (CFM) with a large data volume may cause that hardware configuration of the link table is a memory overhead of software and hardware interaction, and may also occupy a large memory space. When the hardware accelerator is configured by using the linked list currently, the same configuration information is repeatedly configured in the configuration information corresponding to different linked list items, which causes waste of configuration time and memory space. Managing the chain table consumes much time and hardware resources.

Disclosure of Invention

The embodiment of the application provides a configuration method, a configuration device and a storage medium of configuration information of a hardware accelerator, which can reduce configuration time of a plurality of linked lists and storage space of the configuration information, and reduce time and hardware resources consumed by linked list management.

In a first aspect, an embodiment of the present application provides a method for configuring configuration information of a hardware accelerator, where the method configures the hardware accelerator with the configuration information in multiple link entries, and includes the following steps:

determining the configuration information to be updated of each link table item in the plurality of link table items to obtain a plurality of groups of configuration information to be updated, wherein the configuration information to be updated comprises part of configuration information of the configuration information in the corresponding link table item;

writing each group of configuration information to be updated in the multiple groups of configuration information to be updated into the corresponding link table item to obtain multiple written link table items;

generating a flag bit corresponding to the configuration information according to whether each piece of configuration information in the plurality of linked list items is written into each linked list item in the plurality of linked list items or not by the hardware accelerator to obtain a plurality of flag bits;

and packaging the written multiple link table items and the multiple flag bits into a link table data packet, and writing the link table data packet into a shared memory, wherein the multiple flag bits form a link table head of the link table data packet, and the multiple groups of configuration information to be updated form a data part of the link table data packet.

In a second aspect, an embodiment of the present application provides an apparatus for configuring configuration information of a hardware accelerator, where the apparatus configures the hardware accelerator with configuration information in a plurality of link table entries, and the apparatus includes:

a determining unit, configured to determine to-be-updated configuration information of each link table entry in the plurality of link table entries, to obtain a plurality of sets of to-be-updated configuration information, where each set of to-be-updated configuration information includes partial configuration information of configuration information in a corresponding link table entry;

the writing unit is used for writing each group of configuration information to be updated in the plurality of groups of configuration information to be updated into the corresponding link table item to obtain a plurality of written link table items;

a generating unit, configured to generate a flag bit corresponding to configuration information according to whether each piece of configuration information in the configuration information is written into each of the plurality of linked list items through the hardware accelerator, so as to obtain a plurality of flag bits;

the write-in unit is further configured to pack the written multiple linked list items and the multiple flag bits into a linked list data packet, and write the linked list data packet into a shared memory, where the multiple flag bits form a linked list header of the linked list data packet, and the multiple sets of configuration information to be updated form a data portion of the linked list data packet.

In a third aspect, an embodiment of the present application provides an electronic device, including a processor, a memory, a communication interface, and one or more programs, where the one or more programs are stored in the memory and configured to be executed by the processor, and the program includes instructions for executing the steps in the first aspect of the embodiment of the present application.

In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, where the computer-readable storage medium stores a computer program for electronic data exchange, where the computer program enables a computer to perform some or all of the steps described in the first aspect of the embodiment of the present application.

In a fifth aspect, embodiments of the present application provide a computer program product, where the computer program product includes a non-transitory computer-readable storage medium storing a computer program, where the computer program is operable to cause a computer to perform some or all of the steps as described in the first aspect of the embodiments of the present application. The computer program product may be a software installation package.

The embodiment of the application has the following beneficial effects:

it can be seen that, in the configuration method, apparatus, and storage medium for configuration information of a hardware accelerator provided in this embodiment of the present application, a plurality of sets of configuration information to be updated are obtained by determining configuration information to be updated of each of a plurality of linked list items, where each set of configuration information to be updated includes partial configuration information of configuration information in a corresponding linked list item; writing each group of configuration information to be updated in the multiple groups of configuration information to be updated into the corresponding link table item to obtain multiple written link table items; thus, all configuration information in each of the plurality of link entries does not need to be written into the link entries; generating a flag bit corresponding to the configuration information according to whether each piece of configuration information in the plurality of linked list items is written into each linked list item in the plurality of linked list items or not by the hardware accelerator to obtain a plurality of flag bits; the written multiple linked list items and the multiple flag bits are packaged into a linked list data packet and written into a shared memory, wherein the multiple flag bits form a linked list head of the linked list data packet, and the multiple groups of configuration information to be updated form a data part of the linked list data packet, so that by setting the linked list head in the linked list, all the configuration information does not need to be written into the linked list items for summarizing through packaging the linked list head and the effective configuration information to be updated, and the memory size of the linked list is reduced, thereby reducing the storage space requirement; configuration time of a plurality of linked list items is also reduced, so that time consumed for linked list management can be reduced.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1A is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure;

fig. 1B is a schematic flowchart of a method for configuring hardware accelerator configuration information according to an embodiment of the present disclosure;

fig. 1C is a schematic illustration showing configuration information corresponding to a plurality of link entries according to an embodiment of the present application;

fig. 1D is a schematic diagram illustrating a plurality of sets of configuration information to be updated corresponding to a plurality of link entries according to an embodiment of the present application;

fig. 1E is a schematic illustration showing a flag bit corresponding to configuration information generated by a hardware accelerator according to an embodiment of the present application;

FIG. 1F is a schematic diagram illustrating an example of writing a linked list packet to a shared memory according to an embodiment of the present disclosure;

fig. 1G is an illustration schematic diagram of a link head according to an embodiment of the present application.

FIG. 2A is a flowchart illustrating another configuration method for configuration information of a hardware accelerator according to an embodiment of the present disclosure;

fig. 2B is a schematic diagram illustrating an arrangement of virtual address spaces according to an embodiment of the present disclosure;

FIG. 3 is a flowchart illustrating another method for configuring hardware accelerator configuration information according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

fig. 5A is a schematic structural diagram of a configuration apparatus for configuring hardware accelerator configuration information according to an embodiment of the present application;

FIG. 5B is a schematic diagram of a modified arrangement of configuration means for configuring information for the hardware accelerator depicted in FIG. 5A;

fig. 5C is a schematic structural diagram of still another variant of the configuration means for configuring information of the hardware accelerator depicted in fig. 5A.

Detailed Description

In order to make the technical solutions of the present application better understood, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first," "second," and the like in the description and claims of the present application and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

The electronic device related to the embodiments of the present application may include various handheld devices, vehicle-mounted devices, wearable devices (smart watches, smart bracelets, wireless headsets, augmented reality/virtual reality devices, smart glasses), computing devices or other processing devices connected to wireless modems, and various forms of User Equipment (UE), Mobile Stations (MS), terminal devices (terminal device), and the like, which have wireless communication functions. For convenience of description, the above-mentioned devices are collectively referred to as electronic devices.

The following describes embodiments of the present application in detail.

Referring to fig. 1A, fig. 1A is a schematic structural diagram of an electronic device disclosed in an embodiment of the present application, the electronic device 100 includes a processor 110, a hardware accelerator 120, and a shared memory 130, wherein the hardware accelerator 120 and the shared memory 130 are respectively connected to the processor 110, and wherein,

the processor 110 is configured to determine configuration information to be updated of each of a plurality of linked list items, to obtain a plurality of sets of configuration information to be updated, where the configuration information to be updated includes partial configuration information of the hardware accelerator; and writing each group of configuration information to be updated in the plurality of groups of configuration information to be updated into the corresponding link table entry to obtain a plurality of written link table entries.

A hardware accelerator 120, configured to generate a flag bit corresponding to each configuration information in the plurality of linked list items according to whether each configuration information in the plurality of linked list items is written into each linked list item in the plurality of linked list items, so as to obtain a plurality of flag bits; and packaging the written multiple link table entries and the multiple flag bits into a link table data packet, and writing the link table data packet into the shared memory 130, where the multiple flag bits form a link table header of the link table data packet, and the multiple sets of configuration information to be updated form a data portion of the link table data packet.

Therefore, when the hardware accelerator 120 uses any link table entry of the plurality of link table entries, the processor 110 reads the link table packet stored in the shared memory 130, and determines the configuration information to be updated corresponding to any link table entry according to the flag bit information corresponding to the link table entry in the link table header; and updates the configuration information to be updated in the data portion corresponding to any link table entry to the hardware accelerator 120.

Referring to fig. 1B, fig. 1B is a schematic flowchart of a configuration method of hardware accelerator configuration information according to an embodiment of the present application, which is applied to the electronic device shown in fig. 1A, and configures the hardware accelerator by using configuration information in a plurality of link entries, as shown in fig. 1B, the configuration method of hardware accelerator configuration information according to the present application includes:

101. and determining the configuration information to be updated of each link table item in the plurality of link table items to obtain a plurality of groups of configuration information to be updated, wherein each group of configuration information to be updated comprises part of configuration information of the configuration information in the corresponding link table item.

Wherein, the configuration information in the plurality of link table entries includes CFM₁、CFM₂、CFM₃、...、CFM_nN is a positive integer, in a specific implementation, in order to reduce software and hardware interaction overhead, multiple link entries may be configured at a time, and specific contents of the configuration information included in different link entries may be repeated and also have different information contents, so that a set of configuration information to be updated corresponding to some link entries in the multiple link entries may include a CFM₁、CFM₂、CFM₃、...、CFM_nAll of (1), a group of configuration information to be updated corresponding to some link table entries includes CFM₁、CFM₂、CFM₃、...、CFM_nThus, it is not necessary that all the link entries in the plurality of link entries have n pieces of configuration information written into the link table.

Each piece of configuration information corresponding to a first link table item in the plurality of link table items belongs to configuration information to be updated; and the last configuration information corresponding to each link table item in the plurality of link table items belongs to the configuration information to be updated.

Referring to fig. 1C, fig. 1C is a schematic diagram illustrating configuration information corresponding to multiple link items according to an embodiment of the present application, where the configuration information between different link items is related, and some configuration information in different link items may be identical. Therefore, except for the first Link List Item (LLI), the configuration information in other link list items different from the previous link list item all belong to the configuration information to be updated, and the configuration information in other link list items is the same as the configuration information of the previous link list item.

Optionally, the configuration information of the hardware accelerator corresponding to each link entry includes multiple items of configuration information, and in step 101, the determining the configuration information to be updated, which is required to be configured in each link entry of the multiple link entries in the configuration information of the hardware accelerator, to obtain multiple sets of configuration information to be updated may include the following steps:

and aiming at the ith link table item in the plurality of link table items, comparing the plurality of items of configuration information corresponding to the ith link table item with the plurality of items of configuration information corresponding to the (i-1) th link table item to obtain at least one different item of configuration information to be updated, wherein i is an integer greater than 1.

Referring to fig. 1D, fig. 1D is a schematic diagram illustrating a plurality of sets of configuration information to be updated corresponding to a plurality of link entries according to an embodiment of the present disclosure, where a set of configuration information to be updated in a first link entry includes a CFM₁、CFM₂、CFM₃、...、CFM_nAll of (1), the set of configuration information to be updated in the second linked list item includes CFM₂、CFM₃And CFM_nCFM in the second linked list item₂、CFM₃And CFM_nAnd the CFM in the first linked list item₂、CFM₃And CFM_nIs different, and a set of configuration information to be updated in the third linked list item includes CFM₁、CFM₄And CFM_nCFM in the third chaining table entry₁、CFM₄And CFM_nAnd the CFM in the second linked list item₁、CFM₄And CFM_nAre different in their information content.

102. And writing each group of configuration information to be updated in the plurality of groups of configuration information to be updated into the corresponding link table entry to obtain a plurality of written link table entries.

In the embodiment of the present application, a plurality of link entries may be generally configured at a time to reduce overhead of software and hardware interaction, and for each link entry in the plurality of link entries, configuration information to be updated corresponding to the link entry may be written into the link entry.

Optionally, in the step 102, writing each of the multiple sets of configuration information to be updated into the corresponding link table entry to obtain multiple link table entries after writing, the method may include the following steps:

21. executing write operation on each configuration information corresponding to the first link table item in the plurality of link table items according to the address sequence of the virtual address space;

22. if the xth configuration information CFM corresponding to the ith link table item in the plurality of link table items_xXth configuration information CFM corresponding to (i-1) th link table entry_(i-1)xThe same, the xth configuration information CFM corresponding to the ith link table item is skipped_xWherein the CFM_ixConfiguring information for any one of the ith link table items, wherein x is a positive integer;

23. if the xth configuration information CFM_ixBelonging to the configuration information to be updated, and CFM (computational fluid dynamics) the configuration information_ixAnd writing the data into the ith link table entry.

Wherein the configuration information CFM_ixIs the xth configuration information, configuration information CFM in the ith link table entry_(i-1)xIs the xth configuration information in the (i-1) th link table entry.

The electronic device may access the virtual address space, and write a set of configuration information to be updated corresponding to each link table entry from top to bottom in the address order of the virtual address space, as shown in fig. 1D, for the first link table entry LLI₁Link Table item LLI₁Each piece of configuration information in the set of configuration information needs to be updated, and n CFMs can be written; for other link table entries than the first link table entry, if some configuration information CFM in the ith link table entry_ixAnd the previous link table entry LLI_i-1Configuration information CFM of_(i-1)xIf the two are identical, skip the write operation, for example, for the second chain table entry LLI₂Assuming only CFM₂₂、CFM₂₃、CFM_2nNeed to be updated, when only CFM is written₂₂、CFM₂₃、CFM_2n(ii) a For the third LLI₃Assuming only CFM₃₁、CFM₃₄、CFM_3nNeed to be moreNew, then only CFM is written at this time₃₁、CFM₃₄、CFM_3n。

103. And generating a flag bit corresponding to the configuration information according to whether each piece of configuration information in the plurality of linked list items is written into each linked list item in the plurality of linked list items or not by the hardware accelerator to obtain a plurality of flag bits.

When the electronic device writes the configuration information into each of the plurality of linked list items, a flag bit corresponding to each of the configuration information may be generated by the hardware accelerator, and the flag bit is used to identify whether the corresponding configuration information is the configuration information to be updated, so that when the hardware accelerator uses the plurality of linked list items, whether the corresponding configuration information belongs to the configuration information to be updated may be directly determined according to the flag bit.

Optionally, in step 103, generating, by the hardware accelerator, a flag bit corresponding to each configuration information in the plurality of linked list items according to whether each configuration information in the plurality of linked list items is written into each linked list item in the plurality of linked list items may include the following steps:

31. if the configuration information CFM corresponding to each of the plurality of link entries is aimed at_jExecuted write operations, generating with the hardware accelerator the configuration information CFM_jCorresponding flag bit 1, the configuration information CFM_jIs any configuration information, and j is a positive integer;

32. if not aiming at the configuration information CFM_jPerforming a write operation, generating with the configuration information CFM by the hardware accelerator_jThe corresponding flag bit is 0.

For each configuration information in each link table entry, if a write operation is performed on the configuration information, a flag bit 1 corresponding to the configuration information is generated, and if a write operation is not performed on the configuration information, a flag bit 0 corresponding to the configuration information is generated, please refer to fig. 1E, where fig. 1E is a schematic diagram illustrating that a CFM is written in a first link table entry to generate a flag bit corresponding to configuration information of a hardware accelerator according to an embodiment of the present application, where the CFM is written in the first link table entry₁、CFM₂、CFM₃、...、CFM_nThus, the corresponding CFM in the first linked list item₁、CFM₂、CFM₃、...、CFM_nFlag bit 1 is set, and CFM is written in the second chain table item₂、CFM₃、CFM_nThus, the corresponding CFM in the second linked list item₂、CFM₃、CFM_nFlag bit 1 is set, except CFM in the second linked list item₂、CFM₃、CFM_nThe other configuration information is correspondingly provided with a flag bit 0, and the third chain table entry is written with CFM₁、CFM₄、CFM_nThus, the corresponding CFM in the second linked list item₁、CFM₄And CFM_nFlag bit 1 is set, except CFM in the third linked list item₁、CFM₄And CFM_nThe other configuration information corresponds to the set flag bit 0. Therefore, by setting the corresponding flag bit for each configuration information, the condition whether the configuration information executes the write operation can be more directly marked, which is convenient for managing the linked list.

104. And packaging the written multiple link table items and the multiple flag bits into a link table data packet, and writing the link table data packet into a shared memory, wherein the multiple flag bits form a link table head of the link table data packet, and the multiple groups of configuration information to be updated form a data part of the link table data packet.

Referring to fig. 1F, fig. 1F is a schematic diagram illustrating a linked list for writing a linked list data packet into a shared memory according to an embodiment of the present disclosure, where a linked list in the shared memory is composed of a linked list header and a data portion, where the linked list header includes a plurality of flag bits V1-1, V1-2, and V1-3.

Optionally, each row in the head of the chain table includes m flag bits, where m is a positive integer greater than 1, and in the step 104, the method further includes:

if the total number n of the flag bits corresponding to each chain table entry is not an integral multiple of m, filling reserved bits with residual vacant bits behind the last flag bit in the n flag bits in the last row of the n flag bits corresponding to each chain table entry in the chain table header.

In a specific implementation, the total number of flag bits corresponding to each of the chain table entries is n, if n is an integer multiple of m, where each row of the chain table header includes m flag bits, n flag bits corresponding to each chain table entry may be just written into a storage space of n/m rows of the shared memory, and if n is not an integer multiple of m, flag bits corresponding to configuration information in different chain table entries may appear in the same row of the chain table header, for example, n flag bits corresponding to a first chain table entry are written into the shared memory, and a last flag bit V1-n in the n flag bits is not located at a row end position of the row, n flag bits corresponding to a second chain table entry may be immediately followed by a last flag bit V1-n corresponding to the first chain table entry, so as to prevent interference of a flag bit storage space between adjacent chain table entries, the n flag bits corresponding to each chain table entry may be followed by the last flag bit in the row where the last flag bit in the n flag bits corresponding to the chain table entries is located Please refer to fig. 1G, where fig. 1G is a schematic diagram illustrating a head of a chain table according to an embodiment of the present disclosure, where each row of the head of the chain table includes 8 flag bits, and the remaining empty bits in the last row of the n flag bits corresponding to the first chain table entry, except for the flag bits, may also be filled with a reserved bit R, where the value of the reserved bit R may be 0, for example, so as to prevent interference between the chain table entries, the head of the chain table, and the storage space of the data portion.

It can be seen that, in the embodiment of the present application, multiple sets of configuration information to be updated are obtained by determining configuration information to be updated of each of multiple link items, where each set of configuration information to be updated includes part of configuration information in a corresponding link item; writing each group of configuration information to be updated in the plurality of groups of configuration information to be updated into a corresponding link table item to obtain a plurality of written link table items; thus, all configuration information in each of the plurality of link entries does not need to be written into the link entries; generating a flag bit corresponding to the configuration information according to whether each piece of configuration information in the plurality of linked list items is written into each linked list item in the plurality of linked list items or not by a hardware accelerator to obtain a plurality of flag bits; the written multiple linked list items and multiple flag bits are packaged into a linked list data packet and written into a shared storage, the multiple flag bits form a linked list head of the linked list data packet, and multiple groups of configuration information to be updated form a data part of the linked list data packet, so that by setting the linked list head in the linked list, all the configuration information does not need to be written into the linked list items by packaging the linked list head and the effective configuration information to be updated, the memory size of the linked list is reduced, and the storage space requirement is reduced; configuration time of a plurality of linked list items is also reduced, so that time consumed for linked list management can be reduced.

Referring to fig. 2A, fig. 2A is a schematic flowchart illustrating a method for configuring configuration information of a hardware accelerator according to an embodiment of the present application, where the method includes:

201. creating a virtual address space through the hardware accelerator, and storing configuration information in a plurality of link items which need to be configured by the hardware accelerator to the virtual address space.

Referring to fig. 2B, fig. 2B is a schematic diagram illustrating an arrangement of virtual address spaces according to an embodiment of the present disclosure, where a hardware accelerator may implement a section of virtual address space: address add to address add + (n-1) × 4, virtual address space including all configuration information CFM of hardware accelerator needing configuration₁、CFM₂、CFM₃、...、CFM_nThe virtual address space does not occupy the actual memory space, and can be used for temporarily recording the configuration information in a plurality of linked list items.

Wherein, CFM in virtual address space₁、CFM₂、CFM₃、...、CFM_nConfiguration information to be configured for each link table entry.

202. And accessing the virtual address space in the hardware accelerator to obtain the configuration information in a plurality of link items which need to be configured by the hardware accelerator.

Wherein the configuration of the configuration information may be accomplished by accessing the virtual address space. The electronic device may access a virtual address space in the hardware accelerator to obtain configuration information corresponding to each of the plurality of link items, and specifically, may access the virtual address space in an order from top to bottom according to the virtual address space, and sequentially read the plurality of configuration information corresponding to each of the plurality of link items.

203. Determining the configuration information to be updated of each link table item in the plurality of link table items to obtain a plurality of groups of configuration information to be updated, wherein each group of configuration information to be updated comprises part of configuration information of the configuration information in the corresponding link table item, and each configuration information in a first link table item in the plurality of link table items belongs to the configuration information to be updated; the configuration information in the ith link table item in the plurality of link table items, which is different from the configuration information in the previous link table item, belongs to the configuration information to be updated, and i is a positive integer greater than 1; and the last configuration information in each of the plurality of link table items belongs to the configuration information to be updated.

204. And writing each group of configuration information to be updated in the plurality of groups of configuration information to be updated into the corresponding link table entry to obtain a plurality of written link table entries.

205. And generating a flag bit corresponding to the configuration information according to whether each piece of configuration information in the plurality of linked list items is written into each linked list item in the plurality of linked list items or not by the hardware accelerator to obtain a plurality of flag bits.

206. And packaging the written multiple link table items and the multiple flag bits into a link table data packet, and writing the link table data packet into a shared memory, wherein the multiple flag bits form a link table head of the link table data packet, and the multiple groups of configuration information to be updated form a data part of the link table data packet.

The specific implementation process of the steps 203-206 can refer to the corresponding description in the steps 101-104, and will not be described herein again.

207. And when the hardware accelerator uses any link table item in the plurality of link table items, determining the configuration information to be updated corresponding to the link table item according to the flag bit information corresponding to the link table item in the link table head.

After the linked list comprising a plurality of linked list items is obtained, when the hardware accelerator uses the linked list, the configuration information to be updated can be directly judged through the flag bit in the head of the linked list, so that the data part of the linked list data packet is not required to be accessed in a large amount of time, the time for accessing the memory space of the data part is saved, and the configuration efficiency of the hardware accelerator is improved.

208. And updating the configuration information to be updated corresponding to any link table entry in the data part into the hardware accelerator through the hardware accelerator.

The information to be configured in each link table item in the link table can be updated to the hardware accelerator according to the flag bit of the link table head, so that the updating time can be reduced when the hardware accelerator uses the link table.

It can be seen that, in the embodiment of the present application, multiple sets of configuration information to be updated are obtained by determining configuration information to be updated of each of multiple link items, where each configuration information in a first link item in the multiple link items belongs to the configuration information to be updated; the configuration information in the ith link table item in the plurality of link table items, which is different from the configuration information in the previous link table item, belongs to the configuration information to be updated; the last configuration information in each link table item in the plurality of link table items belongs to the configuration information to be updated, and each group of configuration information to be updated in the plurality of groups of configuration information to be updated is written into the corresponding link table item to obtain a plurality of written link table items; thus, all configuration information in each of the plurality of link entries does not need to be written into the link entries; generating a flag bit corresponding to the configuration information according to whether each piece of configuration information in the plurality of linked list items is written into each linked list item in the plurality of linked list items or not by a hardware accelerator to obtain a plurality of flag bits; packaging the written multiple link table items and multiple flag bits into a link table data packet, writing the link table data packet into a shared memory, and judging configuration information to be updated through the multiple flag bits in the head of the link table when the hardware accelerator uses the multiple link table items; the configuration information in the data part is updated to the hardware accelerator through the hardware accelerator, so that the configuration information and the updating time of the hardware accelerator for updating when the linked list is used can be reduced by setting the linked list head in the linked list, and packing the linked list head and the effective configuration information to be updated.

Referring to fig. 3, fig. 3 is a schematic flowchart of another configuration method for configuration information of a hardware accelerator according to an embodiment of the present application, and the method is applied to an electronic device, and the method includes:

creating a virtual address space through a hardware accelerator, and storing configuration information in a plurality of linked list items which need to be configured by the hardware accelerator to the virtual address space; and accessing the virtual address space in the hardware accelerator to obtain the configuration information in a plurality of link items which need to be configured by the hardware accelerator.

Determining the configuration information to be updated of each link table item in the plurality of link table items to obtain a plurality of groups of configuration information to be updated, wherein each group of configuration information to be updated comprises part of configuration information of the configuration information in the corresponding link table item, and each configuration information in a first link table item in the plurality of link table items belongs to the configuration information to be updated; the configuration information in the ith link table item in the plurality of link table items, which is different from the configuration information in the previous link table item, belongs to the configuration information to be updated, and i is a positive integer greater than 1; and the last configuration information in each of the plurality of link table items belongs to the configuration information to be updated.

Writing the configuration information to be updated corresponding to each chain table entry into the chain table entry from top to bottom according to the sequence of the virtual address space, wherein for a first chain table entry, n items of configuration information need to be written, and for a second chain table entry, the configuration information to be updated comprises a second item of configuration information CFM₂The third configuration information CFM₃And the nth configuration information CFM_nTo update configuration information CFM₂、CFM₃、CFM_nExecuting write operation, and skipping the write operation aiming at the configuration information aiming at other configuration information corresponding to the second link table item; for the third link table item, the configuration information to be updated includes the first configuration information CFM₁The fourth configuration information CFM₄And the nth configurationInformation, CFM of configuration information to be updated₁、CFM₄、CFM_nExecuting write operation, and skipping the write operation aiming at the configuration information aiming at other configuration information corresponding to the third link table item; and the like, completing the writing of a plurality of link table entries.

In the process of writing the configuration information, the hardware accelerator generates a flag bit corresponding to the configuration information according to whether each item of configuration information corresponding to each link table item has executed a write operation, wherein if the write operation is executed for the configuration information, a flag bit 1 corresponding to the configuration information is generated, otherwise, a flag bit 0 corresponding to the configuration information is generated. If the total number n of the flag bits corresponding to each chain table entry is not an integral multiple of m, filling reserved bits with residual vacant bits behind the last flag bit in the n flag bits in the last row of the n flag bits corresponding to each chain table entry in the chain table header.

After a plurality of groups of configuration information to be updated are written into a plurality of corresponding chain table items, the hardware accelerator writes the flag bit information and the plurality of chain table items into the shared memory, wherein the plurality of flag bits form a chain table head, and the configuration information of the plurality of chain table items forms a data part.

Therefore, when the hardware accelerator uses the linked list, whether the corresponding configuration information needs to be updated is judged through the flag bit in the head of the linked list, and then the configuration information to be updated of the data part is updated to the hardware accelerator.

It can be seen that, in the embodiment of the present application, a write operation is performed on each configuration information corresponding to a first link entry in a plurality of link entries according to an address order of a virtual address space; for the xth configuration information CFM corresponding to the ith link table item in the plurality of link table items_ixIf the xth configuration information CFM_ixNot belonging to the configuration information to be updated, skipping the CFM for the xth configuration information_(i-1)xWherein CFM_ixConfiguring information for any one of the ith link table items, wherein x is a positive integer; if the xth configuration information CFM_ixBelonging to the configuration information to be updated, CFM_ixWriting into the ith link table entry, thus, not requiring all of the entries in each of the plurality of link table entriesWriting the configuration information into the link table entry; the memory size of the linked list is reduced, so that the storage space requirement is reduced; configuration time of a plurality of linked list items is also reduced, so that time consumed for linked list management can be reduced; if the configuration information CFM corresponding to each of the plurality of link entries_jWrite operations have been performed, generating and configuring information CFM by hardware accelerator_jCorresponding flag bit 1, configuration information CFM_jIs any configuration information, and j is a positive integer; if not aiming at the configuration information CFM_jPerforming write operations, generating and configuring information CFM through hardware accelerator_jAnd if the total number of the plurality of zone bits is not an integral multiple of m, filling reserved bits in the remaining vacant positions except the plurality of zone bits in the head of the chain table, so that whether the configuration information executes the write operation can be marked more directly by setting the corresponding zone bit through each configuration information, and the management of the chain table is facilitated.

The following is a device for implementing the configuration method of the hardware accelerator configuration information, and specifically includes:

in accordance with the above, please refer to fig. 4, where fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure, the electronic device includes: a processor 410, a communication interface 430, and a memory 420; and one or more programs 421, the one or more programs 421 stored in the memory 420 and configured to be executed by the processor, the programs 421 including instructions for:

determining the configuration information to be updated of each link table item in the plurality of link table items to obtain a plurality of groups of configuration information to be updated, wherein each group of configuration information to be updated comprises part of configuration information of the configuration information in the corresponding link table item;

writing each group of configuration information to be updated in the multiple groups of configuration information to be updated into the corresponding link table item to obtain multiple written link table items;

generating a flag bit corresponding to the configuration information according to whether each piece of configuration information in the plurality of linked list items is written into each linked list item in the plurality of linked list items or not by the hardware accelerator to obtain a plurality of flag bits;

and packaging the written multiple link table items and the multiple flag bits into a link table data packet, and writing the link table data packet into a shared memory, wherein the multiple flag bits form a link table head of the link table data packet, and the multiple groups of configuration information to be updated form a data part of the link table data packet.

In a possible example, the configuration information of the hardware accelerator corresponding to each link entry includes multiple items of configuration information, and in the aspect of determining the configuration information to be updated, which is required to be configured in each link entry of the multiple link entries in the configuration information of the hardware accelerator, and obtaining multiple sets of configuration information to be updated, the program 421 includes instructions for performing the following steps:

and aiming at the ith link table item in the plurality of link table items, comparing the plurality of items of configuration information corresponding to the ith link table item with the plurality of items of configuration information corresponding to the (i-1) th link table item to obtain at least one different item of configuration information to be updated, wherein i is an integer greater than 1.

In one possible example, each piece of configuration information corresponding to a first link entry in the plurality of link entries belongs to configuration information to be updated; and the last configuration information corresponding to each link table item in the plurality of link table items belongs to the configuration information to be updated.

In one possible example, the program 421 further includes instructions for performing the steps of:

creating a virtual address space through the hardware accelerator, and storing configuration information in a plurality of linked list items which need to be configured by the hardware accelerator to the virtual address space;

and accessing the virtual address space in the hardware accelerator to obtain the configuration information in a plurality of link items which need to be configured by the hardware accelerator.

In one possible example, in the aspect that each of the multiple sets of configuration information to be updated is written into the corresponding link table entry, so as to obtain multiple written link table entries, the program 421 includes instructions for performing the following steps:

executing write operation on each configuration information corresponding to the first link table item in the plurality of link table items according to the address sequence of the virtual address space;

if the xth configuration information CFM corresponding to the ith link table item in the plurality of link table items_xXth configuration information CFM corresponding to (i-1) th link table entry_(i-1)xThe same, the xth configuration information CFM corresponding to the ith link table item is skipped_xWherein the CFM_ixConfiguring information for any one of the ith link table items, wherein x is a positive integer;

if the xth configuration information CFM_ixBelonging to the configuration information to be updated, and CFM (computational fluid dynamics) the configuration information_ixAnd writing the data into the ith link table entry.

In one possible example, in terms of generating, by the hardware accelerator, a flag bit corresponding to each of the configuration information in the plurality of linked list items according to whether each of the configuration information in the plurality of linked list items is written into each of the plurality of linked list items, and obtaining a plurality of flag bits, the program 421 includes instructions for:

if the configuration information CFM corresponding to each of the plurality of link entries is aimed at_jExecuted write operations, generating with the hardware accelerator the configuration information CFM_jCorresponding flag bit 1, the configuration information CFM_jIs any configuration information, and j is a positive integer;

if not aiming at the configuration information CFM_jPerforming a write operation, generating with the configuration information CFM by the hardware accelerator_jThe corresponding flag bit is 0.

In one possible example, each row in the head of the chain table includes m flag bits, m being a positive integer greater than 1, the program 421 further includes instructions for:

if the total number of the plurality of flag bits is not an integral multiple of m, filling reserved bits with the rest vacant bits except the plurality of flag bits in the chain table header.

In one possible example, the program 421 further includes instructions for performing the steps of:

when the hardware accelerator uses any link table item in the plurality of link table items, determining the configuration information to be updated corresponding to the link table item according to the flag bit information corresponding to the link table item in the link table head;

and updating the configuration information to be updated corresponding to any link table entry in the data part into the hardware accelerator through the hardware accelerator.

Referring to fig. 5A, fig. 5A is a schematic structural diagram of a configuration apparatus of configuration information of a hardware accelerator according to this embodiment, where the configuration apparatus 500 of configuration information of a hardware accelerator is applied to an electronic device, the electronic device includes a hardware accelerator, the hardware accelerator is configured by using configuration information in a plurality of link table entries, the apparatus 500 includes a determining unit 501, a writing unit 502, and a generating unit 503, where,

the determining unit 501 is configured to determine the configuration information to be updated of each link entry in the plurality of link entries, to obtain a plurality of sets of configuration information to be updated, where each set of configuration information to be updated includes part of configuration information of the configuration information in the corresponding link entry;

the writing unit 502 is configured to write each of the multiple sets of configuration information to be updated into the corresponding link table entry, so as to obtain multiple link table entries after writing;

the generating unit 503 is configured to generate, by the hardware accelerator, a flag bit corresponding to each configuration information in the plurality of linked list items according to whether each configuration information in the plurality of linked list items is written into each linked list item in the plurality of linked list items, so as to obtain a plurality of flag bits;

the writing unit 502 is further configured to pack the written multiple link table entries and the multiple flag bits into a link table data packet, and write the link table data packet into a shared memory, where the multiple flag bits form a link table header of the link table data packet, and the multiple sets of configuration information to be updated form a data portion of the link table data packet.

Optionally, the determining unit 501 is specifically configured to:

and aiming at the ith link table item in the plurality of link table items, comparing the plurality of items of configuration information corresponding to the ith link table item with the plurality of items of configuration information corresponding to the (i-1) th link table item to obtain at least one different item of configuration information to be updated, wherein i is an integer greater than 1.

Optionally, each configuration information corresponding to a first link entry in the plurality of link entries belongs to the configuration information to be updated; and the last configuration information corresponding to each link table item in the plurality of link table items belongs to the configuration information to be updated.

Alternatively, as shown in fig. 5B, fig. 5B is a modified apparatus of the configuration apparatus of the hardware accelerator configuration information depicted in fig. 5A, which may further include, compared with fig. 5A: the creating unit 504 and the accessing unit 505 are specifically as follows:

the creating unit 504 is configured to create a virtual address space through the hardware accelerator, and store configuration information in a plurality of linked list items that the hardware accelerator needs to configure to the virtual address space;

the access unit 505 is configured to access a virtual address space in the hardware accelerator, and obtain configuration information in a plurality of link table entries that the hardware accelerator needs to configure.

Optionally, in the aspect that each group of configuration information to be updated in the multiple groups of configuration information to be updated is written into the corresponding link table entry to obtain multiple written link table entries, the writing unit 502 is specifically configured to:

executing write operation on each configuration information corresponding to the first link table item in the plurality of link table items according to the address sequence of the virtual address space;

if the xth configuration information CFM corresponding to the ith link table item in the plurality of link table items_xXth configuration information CFM corresponding to (i-1) th link table entry_(i-1)xThe same, the xth configuration information CFM corresponding to the ith link table item is skipped_xWherein the CFM_ixIs the ithAny configuration information in the chain table item, wherein x is a positive integer;

if the xth configuration information CFM_ixBelonging to the configuration information to be updated, and CFM (computational fluid dynamics) the configuration information_ixAnd writing the data into the ith link table entry.

Optionally, in terms of generating, by the hardware accelerator, a flag bit corresponding to the configuration information according to whether each piece of configuration information in the plurality of linked list items is written into each linked list item in the plurality of linked list items, and obtaining a plurality of flag bits, the generating unit 503 is specifically configured to:

if the configuration information CFM corresponding to each of the plurality of link entries is aimed at_jExecuted write operations, generating with the hardware accelerator the configuration information CFM_jCorresponding flag bit 1, the configuration information CFM_jIs any configuration information, and j is a positive integer;

if not aiming at the configuration information CFM_jPerforming a write operation, generating with the configuration information CFM by the hardware accelerator_jThe corresponding flag bit is 0.

Optionally, each row in the head of the chain table includes m flag bits, m is a positive integer greater than 1, and the generating unit 503 is further configured to:

if the total number of the plurality of flag bits is not an integral multiple of m, filling reserved bits with the rest vacant bits except the plurality of flag bits in the chain table header.

Optionally, as shown in fig. 5C, fig. 5C is a further variant of the configuration apparatus of the hardware accelerator configuration information depicted in fig. 5A, which may further include, compared with fig. 5A: the processing unit 506 is specifically as follows:

the processing unit 506 is configured to determine, when the hardware accelerator uses any link table entry in the plurality of link table entries, to-be-updated configuration information corresponding to the link table entry according to flag bit information corresponding to the link table entry in the link table header; and the number of the first and second groups,

and updating the configuration information to be updated corresponding to any link table entry in the data part into the hardware accelerator through the hardware accelerator.

It can be seen that the configuration device for configuration information of a hardware accelerator described in the embodiment of the present application is applied to an electronic device, and obtains multiple sets of configuration information to be updated by determining configuration information to be updated of each link entry in multiple link entries, where each set of configuration information to be updated includes part of configuration information in a corresponding link entry; writing each group of configuration information to be updated in the plurality of groups of configuration information to be updated into a corresponding link table item to obtain a plurality of written link table items; thus, all configuration information in each of the plurality of link entries does not need to be written into the link entries; generating a flag bit corresponding to the configuration information according to whether each piece of configuration information in the plurality of linked list items is written into each linked list item in the plurality of linked list items or not by a hardware accelerator to obtain a plurality of flag bits; the written multiple linked list items and multiple flag bits are packaged into a linked list data packet and written into a shared storage, the multiple flag bits form a linked list head of the linked list data packet, and multiple groups of configuration information to be updated form a data part of the linked list data packet, so that by setting the linked list head in the linked list, all the configuration information does not need to be written into the linked list items by packaging the linked list head and the effective configuration information to be updated, the memory size of the linked list is reduced, and the storage space requirement is reduced; configuration time of a plurality of linked list items is also reduced, so that time consumed for linked list management can be reduced.

It can be understood that the functions of each program module of the configuration apparatus for configuration information of a hardware accelerator in this embodiment may be specifically implemented according to the method in the foregoing method embodiment, and the specific implementation process may refer to the relevant description of the foregoing method embodiment, which is not described herein again.

Embodiments of the present application also provide a computer storage medium, where the computer storage medium stores a computer program for electronic data exchange, the computer program enabling a computer to execute part or all of the steps of any one of the methods described in the above method embodiments, and the computer includes an electronic device.

Embodiments of the present application also provide a computer program product comprising a non-transitory computer readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps of any of the methods as described in the above method embodiments. The computer program product may be a software installation package, the computer comprising an electronic device.

It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present application is not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required in this application.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the above-described division of the units is only one type of division of logical functions, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of some interfaces, devices or units, and may be an electric or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit may be stored in a computer readable memory if it is implemented in the form of a software functional unit and sold or used as a stand-alone product. Based on such understanding, the technical solution of the present application may be substantially implemented or a part of or all or part of the technical solution contributing to the prior art may be embodied in the form of a software product stored in a memory, and including several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the above-mentioned method of the embodiments of the present application. And the aforementioned memory comprises: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.

Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer-readable memory, which may include: flash Memory disks, Read-Only memories (ROMs), Random Access Memories (RAMs), magnetic or optical disks, and the like.

The foregoing detailed description of the embodiments of the present application has been presented to illustrate the principles and implementations of the present application, and the above description of the embodiments is only provided to help understand the method and the core concept of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.